Data clock jitter in supersampling multiplex transmission

An estimate of the signal/noise ratio (SNR) degradation at the output of a data clock timing recovery circuit for multiplexed transmission using supersampling is presented. Both the effects of sampling clock jitter and data edge uncertainty are accounted for to determine the performance degradation as a function of the sampling frequency/data bit rate ratio D.     

Jitter requirements of the sampling clock in software radio receivers

The effective number of bits of an analog-to-digital converter (ADC) is not only limited by the quantization step inaccuracy but also by sampling time uncertainty. According to a commonly used model, the error caused by timing jitter, integrated over the whole bandwidth, should not be bigger than the quantization noise, for a full swing input signals at the maximum input frequency. This results in unfeasible phase noise requirements for the sampling clock in software radio receivers with direct RF sampling. However, for a radio receiver not the total integrated error is relevant, but only the error signal in the channel bandwidth. This paper explores the clock jitter requirements for a software radio application, using a more realistic model and taking into account the power spectrum of both the input signal and the spectrum of the sampling clock jitter. Using this model, we show that the clock jitter requirements are very similar to reciprocal mixing requirements of superheterodyne receivers.     

4-bit FLASH ADC行为级建模与仿真

基于Matlab/Simulink的平台,设计并实现了一种新型的单通道4-bit FLASH ADC行为级仿真模型,模型充分考虑到时钟抖动、失调电压、迟滞效应、比较器噪声等非理想特性,使整个系统更逼近实际电路。在输入信号为1 GHz,采样时钟频率为500 MHz时,对非理想模型进行时域及频域分析,创建的模型和系统仿真结果可为ADC系统中的误差、静态特性及动态特性研究提供借鉴。     

高速CMOS闪烁型模数转换器中的误差源研究

对高速CMOS闪烁型模数转换器中的六种误差源进行了研究.每个误差源会潜在的限制模数转换器的线性度和信噪比.这些误差源包括基准电压的非理想因素、前置放大器引入的输入有关的时间延迟、比较器的回程噪声、时钟抖动与分布特性、温度计码中的火花码、比较器的亚稳态.在每种误差源研究的基础上,给出了相应的电路解决技术,使得吉赫频率范围中等分辨率的CMOS闪烁型ADC成为现实.     

Signal Reconstruction Errors in Jittered Sampling

One of the most significant types of error in digital signal processing (DSP) systems working with wideband signals is the error introduced by the analog-to-digital (AD) and digital-to-analog (DA) converters. This paper presents an accurate and simple method to evaluate the performance of AD/DA converters affected by clock jitter, which is based on the analysis of the mean square error (MSE) between the reconstructed signal and the original one. Using an approximation of the linear minimum MSE (LMMSE) filter as reconstruction technique, we derive analytic expressions of the MSE. In particular, through asymptotic analysis, we are able to simply evaluate the performance of digital signal reconstruction as a function of the clock jitter, number of quantization bits, signal bandwidth and sampling rate.      

A 2.5-V BiCMOS comparator with current-mode interpolation

A high-speed latched comparator based on a current-mode architecture is presented. It achieves a sampling speed of 150 MS/s at 2.5 V supply, with a power consumption lower than conventional schemes. Its very low kickback noise makes it especially suitable for differential analog-to-digital converters (ADCs). Moreover, it supports precise 2X interpolation in current mode at full clock speed, allowing a further reduction of the ADC power consumption. The comparator was implemented in a 0.8 μm BiCMOS technology     

Analyzing the effect of the phase-jitter in the operation of second order phase-locked loops

Phase-locked loops (PLLs) are designed to extract timing signals in telecommunication networks. Noise, cross-talk, inter-symbol interference, quantization noise, and signal distortion are responsible for oscillations in the time between two successive transitions of the clock or data signal. It appears as an accidental phase modulation superposed to the original signal. This phenomenon is called timing jitter and affects the integrity of the data recovering process and, as a consequence, the error bit rate is increased. This problem has been studied by treating the jitter as a band limited noise process and tolerance masks for the jitter amplitude and frequency are recommended for several network architectures. Here, we develop a simple model with the continuous phase deviations of the clock signals considered as periodic signals in the band of the real disturbances. Comparisons with the stochastic approach are presented.     

分数倍延时数字滤波器设计

在时分交替ADC结构中,由于各子通道ADC采样时钟的偏差,导致通道采样信号误差,严重影响时分交替ADC的动态性能.针对时分交替ADC中子通道的时钟偏差,在信号精确重构的理论依据下,采用基函数分段拟合和频域逼近的方式设计延时低通滤波器.通过改变基函数的定义域,推导了[-Ts,0]内误差校正的理论基础,并结合基函数设计和频...     

Analogue to digital convertor architecture with a signal leveldetector

A new signal level detector for a flash-type A/D convertor is introduced. It operates like a comparator with the 1-of-n encoder of flash-type A/D convertors. Because the clock signal can be omitted in the application of the comparator, clock feedthrough noise is not a problem. A resolution of up to 8 bits in A/D conversion is feasible     

Influence of Metastability Errors on SNR in Successive-Approximation A/D Converters

We present a theory for metastability error power in SuccessiveApproximation A/D converters. The traditional measure, BER, does not accountfor the error influence on signal quality, only the error rate. The metastability error is instead compared with noise, and aSignal-to-Metastability-error-Ratio, SMR, is suggested as a new measure. Suppressing SMR below SNR imposes a gain requirement on the comparator.     

折叠内插A/D转换器中分布式T/H电路的建模分析

分析了折叠内插A/D转换器中前置放大器和分布式采样保持电路的失真和对系统动态性能的影响,利用Hspice和Matlab进行了电路行为级的建模,分别对带宽受限、输入失调电压、时钟抖动和偏移等进行了仿真。最后,对数据进行了分析综合。所述结论可用来估计折叠内插A/D转换器中的失真,作为设计参考。     

Power-efficient metastability error reduction in CMOS flash A/Dconverters

A power and area efficient technique to reduce metastability errors in high-speed flash A/D converters is described. Pipelining to reduce error rates in an n-bit flash converter is accomplished with a bit pipeline scheme requiring n latches per pipeline stage instead of 2 ⁿ-1. A 7-b, 80 MHz prototype converter is implemented in 1.2-μm CMOS with measured metastability error rates of less than 10 ^-12 errors/cycle. The measured power is 307.2 mW with an 80-MHz sampling frequency. Without metastability error reduction circuitry, the estimated metastability error rate for the converter is 10^-4 errors/cycle. Achieving an equivalent error rate with two pipeline stages of 2ⁿ-1 latches would require 3.48 times the power for the metastability error reduction circuitry. This corresponds to a reduction in total power by a factor of 1.24 compared with the comparator pipelined converter for Nyquist frequency inputs     

An 8-bit 100-MHz full-Nyquist analog-to-digital converter

An 8-bit 100-MHz full-Nyquist analog-to-digital (A/D) converter using a folding and interpolation architecture is presented. In a folding system a multiple use of comparator stages is implemented. A reduction in the number of comparators, equal to the number of times the signal is folded, is obtained. However, every quantization level requires a folding stage, thus no reduction in input circuitry is found. Interpolation between the outputs of the folding stages generates additional folding signals without the need for input stages. A reduction in input circuitry equal to the number of interpolations is obtained. The converter is implemented in an oxide-isolated bipolar process, requiring 800 mW from a single 5.2-V supply. A high-level model describing distortion caused by timing errors is presented. Considering clock timing accuracies needed to obtain the speed requirement, this distortion is thought to be the main speed limitation     

Static linearity error analysis of subranging A/D converters

An 8- to 10-bit CMOS A/D converter with a conversion rate of more than 16 megasample/second is required in consumer video systems. Subranging architecture is widely used to realize such A/D converters. This architecture, however, exhibits a reference voltage error caused by resistor ladder loadings. The error has been discussed with respect to a flash A/D converter by Dingwall. However, it can not be applied for a subranging A/D converter as it is. The analysis of this error is very important in realizing the desired accuracy of a subranging A/D converter. This paper describes a static analysis to improve the linearity, and reports the results of this analysis for two typical types, one with individual comparator arrays for coarse and fine A/D conversions, and the other with the same comparator array for both conversions. This analysis makes it clear that a subranging A/D converter has unique saw-tooth characteristic in fine linearity errors. Furthermore, this analysis clarifies what conditions are necessary to achieve the desired accuracy. It is necessary, for example, that the product of the total input capacitance of the comparators C, the conversion rate f _sand the total ladder resistance R is less than 0.03 in A/D converters with individual comparator arrays and 0.016 in A/D converters with the same comparator array in order to achieve 10-bit accuracy.     

An 8-bit 150-MHz CMOS A/D converter

This paper describes an 8-bit 5-stage pipelined and interleaved analog-to-digital converter that performs analog processing only by means of open-loop circuits such as differential pairs and source followers to achieve a high conversion rate. The concept of sliding interpolation is proposed to obviate the need for a large number of comparators or interstage digital-to-analog converters and residue amplifiers. The pipelining scheme incorporates distributed sampling between the stages so as to relax the linearity-speed tradeoffs in the sample-and-hold circuits, A clock edge reassignment technique is also introduced that suppresses timing mismatches in interleaved systems, and a punctured interpolation method is proposed that reduces the integral nonlinearity error with negligible speed or power penalty. Fabricated in a 0.6-μm CMOS technology, the converter achieves differential and integral nonlinearities of 0.62 and 1.24 LSB, respectively, and a signal-to-(noise+distortion) ratio of 43.7 dB at a sampling rate of 150 MHz. The circuit draws 395 mW from a 3.3-V supply and occupies an area of 1.2×1.5 mm²     

Time interleaved converter arrays

High-speed monolithic converters normally use a variation of the flash technique, which 2/SUP n/ comparators in parallel to obtain a fast n-bit conversion. Although this method allows for high converter bandwidth, it is not very area efficient, and results in large die sizes for even modest resolution converters. In the technique presented here, a number of small but area efficient converters are operated in a time-interleaved fashion to achieve the bandwidth of a flash circuit, but in a substantially smaller area. This technique is analyzed with respect to noise and distortion resulting from nonideal array characteristics, and is demonstrated by way of a four-way array test-chip. This chip consists of four time-interleaved 7-bit weighted-capacitor A/D converters fabricated in a 10 /spl mu/m metal-gate CMOS process. Full 7-bit linearity is maintained up to a 2.5 MHz conversion rate, with operation at reduced linearity continuing to approximately 4 MHz. The design of this chip, and anticipated characteristics if fabricated in a modern 4-5 /spl mu/m process are described.     

A new high-speed periodic-threshold comparator for use in aJosephson A/D converter

A Josephson comparator based on a nonhysteric one-junction superconducting quantum interference device (SQUID) for use in a periodic-threshold A/D (analog-to-digital) converter is discussed. Simulations show that a 4-bit A/D converter using this comparator could have a sampling rate of >20 GHz with an analog signal bandwidth of >10 GHz. This performance represents a factor-of-greater-than-five improvement over that of other periodic-threshold A/D converters, which are based on two- or three-junction SQUIDs     

An Analytical Approach for Quantifying Clock Jitter Effects in Continuous-Time Sigma–Delta Modulators

Continuous-time sigma–delta modulators (CTSDMs) may suffer severe performance degradation from the timing error in a quantizer clock. We present an analytical approach to quantify the performance loss due to clock jitter in a CTSDM. Unlike many prior works that model the timing error of clocks as additive white Gaussian phase noise, we propose a jitter model that exhibits an auto-regression form, so we term it auto regressive (AR) jitter. This AR jitter model shows exactly the same jitter behavior as that of a clock generated by practical phase-locked loops. Based on this AR jitter model, we establish an analytical approach to examine the intricate effects of clock uncertainty on CTSDM system performance. We demonstrate the validity of the proposed analytical method by showing its excellent agreement with simulation results. The analytical method enables a profound insight into the problem of how clock jitter degrades the system performance and also provides a guideline on how to minimize the detrimental effects of clock jitter.     

一种无需导频的适用于差分OFDM系统的符号与采样钟联合同步方法

该文提出了一种适用于OFDM系统的联合符号和采样钟同步校正方法,其中同步校正是在数字域通过改变对接收过采样信号的插值(interpolation)和抽取(decimation)实现的。这种方法在发送端相邻载波间采用差分QPSK调制,在接收端利用QPSK的差分解调信号获得同步误差信号,从而获得关于OFDM符号同步和采样钟同步调整的算法,其特点是无需专门的同步导频信号。所提出算法的同步性能在高斯白噪声信道和多径衰落信道均得到验证。     

SNR Enhancement Algorithm Using Multiple Chirp Symbols with Clock Drift for Accurate Ranging

A signal‐to‐noise ratio (SNR) enhancement algorithm using multiple chirp symbols with clock drift is proposed for accurate ranging. Improvement of the ranging performance can be achieved by using the multiple chirp symbols according to Cramer‐Rao lower bound; however, distortion caused by clock drift is inevitable practically. The distortion induced by the clock drift is approximated as a linear phase term, caused by carrier frequency offset, sampling time offset, and symbol time offset. SNR of the averaged chirp symbol obtained from the proposed algorithm based on the phase derotation and the symbol averaging is enhanced. Hence, the ranging performance is improved. The mathematical analysis of the SNR enhancement agrees with the simulations.