Monitoring optical network performance degradation due to amplifier noise

The relationship between optical performance as monitored within a network and the end terminal optical signal-to-noise ratio (OSNR) and bit error ratio (BER) is measured for the case of performance degradation due to amplified spontaneous emission noise. Measurements on 10-Gb/s signals reveal that performance monitoring sensitivity to OSNR levels of 26 dB is sufficient for identifying degradations that impact the end terminal BER.     

Practical charge-transfer amplifier design architectures for low-power flash A/D converters

Two improved charge-transfer amplifiers (CTAs), used as zero-static-bias comparator preamplifiers in flash analog-digital converters, are proposed. The first improvement eliminates the capacitive coupling at the amplifier input, reducing area and input capacitance. The second eliminates the need for a common-mode output reference voltage by deriving the common-mode output from a switched average of the power supplies. In the latter, nearly a full-scale input range is achieved while preserving the low-power low offset characteristics of earlier CTAs. Voltage comparator devices were constructed in 0.6-/spl mu/m double-poly, triple-metal CMOS to test the prototype CTA architectures. Input common-mode range and offset performance consistent with simulation data is demonstrated with a 10X reduction in input capacitance. Measured dynamic power dissipation on the order of 3-6 /spl mu/W/MSPS is observed. The experimental CTA preamplifiers occupy roughly 0.015 mm/sup 2/.     

A high-speed offset cancelling distributed sample-and-hold architecture for flash A/D converters

A 6-bit high-speed analog-to-digital converter was implemented utilizing a novel distributed sample-and-hold architecture capable of sampling and subtracting the input preamplifier's offset. This architecture offers substantial improvement in the high-speed operation of the converter. Compared to the prior-art, the effective number of bits improves 0.8 bit. The spurious free dynamic range improvement is over 12 dB. In addition the implemented technique uses half the number of capacitors compared to similar designs. The converter achieves over 5.2 bit resolution up to the Nyquist input signal frequency. A simple but effective design methodology is also presented.     

A/D和D/A转换器

7846RP 16位D/A转换器适合于空间飞行应用,根据 轨道不同,可以承受高于100krad（千拉德）的辐射。该转 换器具有正和负基准输入特性,并有一个片上输出放大器, 用户可以选择单极或者双极输出。     

Analysis of the PLL jitter due to power/ground and substrate noise

Phase-locked loops (PLL) in radio-frequency (RF) and mixed analog-digital integrated circuits (ICs) experience substrate coupling due to the simultaneous circuit switching and power/ground (P/G) noise which translate to a timing jitter. In this paper. an analysis of the PLL timing jitter due to substrate noise resulting from P/G noise and large-signal switching is presented. A general comprehensive stochastic model of the substrate and P/G noise sources in very large-scale integration (VLSI) circuits is proposed. This is followed by calculation of the phase noise of the constituent voltage-controlled oscillator (VCO) in terms of the statistical properties of substrate and P/G noise. The PLL timing jitter is then predicted in response to the VCO phase noise. Our mathematical method is utilized to study the jitter-induced P/G noise in a CMOS PLL, which is designed and simulated in a 0.25-/spl mu/m standard CMOS process. A comparison between the results obtained by our mathematical model and those obtained by HSPICE simulation prove the accuracy of the predicted model.     

Offset averaging in flash and folding A/D converters using second-order active resistive networks

A novel approach to average the random offsets in flash and folding A/D converters is introduced. The proposed method uses second-order active resistive networks and, compared to previously reported methods employing passive resistive grids, a better offset reduction is achieved without sacrificing the signal gain. Both behavioural and transistor-level simulation results confirm the performance of the proposed technique.     

Cancellation performance degradation of a fully adaptive Yagi array due to inner-element coupling

The effect of inner-element coupling on the cancellation performance of a fully adaptive Yagi array is considered. Graphs of the output residue power as functions of interference-to-noise ratio and bandwidth with and without the inner-coupling effect are presented. It is seen that mutual coupling, like any other frequency-dependent error source, poses a severe limitation to the ability of the array to counteract sidelobe interference.     

Accurate modeling of noise in switched-C /spl Delta//spl Sigma/ analog-to-digital converters

An accurate physical model of switched-capacitor /spl Delta//spl Sigma/ analog-to-digital converters (ADCs) noise is presented. Noise artifacts for various ADC blocks are captured using simple equations. Model is verified against measured 0.25-/spl mu/m high dynamic range ADC test chip for a wireless receiver. Design guidelines based on the proposed model are discussed.     

Full-speed testing of A/D converters

Improved computer-aided analog-to-digital converter (ADC) characterization methods based on the code density test and spectral analysis using the fast Fourier transform are described. The code density test produces a histogram of the digital output codes of an ADC sampling a known input. The code density can be interpreted to compute the differential and integral nonlinearities, gain error, offset error, and internal noise. Conversion-rate and frequency-dependent behavior can also be measured.     

Characterization and modeling of RF substrate coupling effects in 3D integrated circuit stacking

This work addresses parasitic substrate coupling effects in 3D integrated circuits due to Through Silicon Vias (TSV). Electrical characterizations have been performed on dedicated test structures in order to extract electrical models of substrate coupling phenomena when RF signals are propagated in TSV. A good compatibility between RF measurements and RF simulations allows validating modeling tools for predictive studies. Next, parametric studies are performed in order to study impact of TSV design and materials on substrate coupling noise.     

Performance degradation of phase-modulated systems due to nonlinear phase noise

The error probability is calculated for phase-modulated systems with nonlinear phase noise. Using the assumption that the phase of amplifier noise and nonlinear phase noise are independent of each other, the error probability and penalty are calculated for both phase-shift keying (PSK) and differential phase-shift keying (DPSK) systems. The mean nonlinear phase shift must be less than about 1.00 and 0.63 rad for a penalty less than 1 dB for PSK and DPSK systems, respectively.     

Trimless high precision ratioed resistors in D/A and A/D converters

Investigations into realization of high precision ratioed resistors in standard CMOS and BiCMOS processes have been carried out. The results indicate that the layout of the resistors can be optimized with respect to area and matching requirements to yield relative accuracy better than 0.25%. Using an intermeshed ladder architecture, fast converters with resolution up to 10 b are realizable without trimming     

Dynamic testing of high-speed A/D converters

The proposed digital techniques determine the transfer characteristics of A/D converters under dynamic operating conditions. Characteristic parameters are derived from the digital outputs of converters. Measurements show the discrepancy between static and dynamic performances.     

Systematic design of double-sampling /spl Sigma//spl Delta/ A/D converters with a modified noise transfer function

Double-sampling /spl Sigma//spl Delta/ analog-digital converters (ADCs) are sensitive to path mismatch which causes quantization noise to fold into the signal band. A recent solution for this problem consists of modifying the noise transfer function (NTF) of the modulator such that it has one or several zeros at the Nyquist frequency, next to those in the baseband. In this brief, we present a systematic design strategy for such ADCs. It consists of finding optimal pole positions for the modified NTF. This can be combined with optimizing the zeros as well. Next, we introduce several efficient structures that have enough degrees of freedom to realize the optimized pole positions.     

A new approach to the modeling of converters for SPICE simulation

An approach to the modeling of DC-DC converters for SPICE simulation is developed in which the average current in the energy-storage inductor is first simulated in a SPICE subcircuit for both the continuous and discontinuous modes of operation. The inductor current is then weighted and redistributed to related branches of the circuit to simulate the average input and output currents of the converter. Based on this technique, various converter models, including that of the Cuk converter with coupled inductors, which are valid for both continuous and discontinuous modes of operation, are developed     

A COMPUTER-AIDED UNIFIED APPROACH TO MODELING PWM AND RESONANT CONVERTERS

This letter puts forward a method of modeling for the steady-state and small signal dynamic analysis on PWM, quasi-resonant and series/（parallel） resonant switching converters based on pulse-waveform integral approach. As an example, PWM and quasi-resonant converters are used to discuss the principle of the approach. The results are compared with those in the relative literatures. Computer aided analysis are made to confirm the correctness.