Fully depleted SOI CMOS logic gates for low-voltage applications

Approaches are discussed to the design of low-voltage, low-power VLSI circuits based on SOI nanotransistors. Computer simulations are run to analyze the switching performance of NOT, 2NAND, and 2NOR gates implemented in CMOS technology with fully depleted SOI nanotransistors of different design parameters. The delay and switching power are investigated as functions of supply voltage over a range lying below 1 V, for different values of back-gate bias. The possibility is investigated of operating the transistors of a logic gate in subthreshold mode. This approach is shown to provide a significant reduction in switching power under the right conditions.     

全耗尽CMOS/SOI工艺

对全耗尽 CMOS/ SOI工艺进行了研究 ,成功地开发出成套全耗尽 CMOS/ SOI抗辐照工艺 .其关键工艺技术包括 :氮化 H2 - O2 合成薄栅氧、双栅和注 Ge硅化物等技术 .经过工艺投片 ,获得性能良好的抗辐照 CMOS/ SOI器件和电路 (包括 10 1级环振、2 0 0 0门门海阵列等 ) ,其中 ,n MOS:Vt=0 .7V,Vds=4 .5～ 5 .2 V,μeff=4 6 5 cm2 / (V· s) ,p MOS:Vt=- 0 .8V ,Vds=- 5～ - 6 .3V,μeff=2 6 4 cm2 / (V· s) .当工作电压为 5 V时 ,0 .8μm环振单级延迟为 4 5 ps     

全耗尽CMOS/SOI工艺

对全耗尽CMOS/SOI工艺进行了研究,成功地开发出成套全耗尽 CMOS/SOI抗辐照工艺.其关键工艺技术包括:氮化H2-O2合成薄栅氧、双栅和注Ge硅化物等技术.经过工艺投片,获得性能良好的抗辐照CMOS/SOI器件和电路(包括101级环振、2000门门海阵列等),其中,nMOS:Vt=0.7V,Vds=4.5～5.2V,μeff=465cm2/(V*s),pMOS:Vt=-0.8V,Vds=-5～-6.3V,μeff=264cm2/(V*s).当工作电压为5V时,0.8μm环振单级延迟为45ps.     

Fully integrated dual-band VCOs with power controlled by body voltage in 130 nm CMOS/SOI for multi-standard applications

In this paper, the design of two VCOs for wireless multi-standard applications is presented. The oscillation frequencies are 5.2 and 3.3 GHz. These circuits have been produced using CMOS/SOI technology, with body voltage to control power consumption and phase noise performance. A new architecture for multi-standard applications is proposed. Five standards are covered by these structures: GSM (900 MHz), GPS (1.5 GHz), DCS (1.8 GHz), Bluetooth (2.45 GHz) and 802.11 a (5.8 GHz). The tuning range can vary from 2.45 to 5.8 GHz for the first VCO and from 850 MHz to 1.9 GHz for the second by using frequency divider. The main idea is to use only two MOS varactors to cover the entire frequency span. The first one is needed to get the matched frequency variation and the second to adjust the oscillation frequency. Such VCOs can be made thanks to CMOS/SOI technology advantages, high-Q passives and body voltage biasing that allow current change and power dissipation in the VCO core. These circuits were produced with a view to producing a single VCO covering all these standards. Switched resonators were therefore studied. At a frequency offset of 100 kHz, the single side band phase noise measurements were −89 and −93 dBc/Hz at 5.2 and 3.6 GHz respectively.     

全耗尽SOI MOSFET及CMOS／SOI电路的研究

采用ＳＩＭＯＸ材料，研制了一种全耗尽ＣＭＯＳ／ＳＯＩ模拟开关电路，研究了全耗尽ＳＯＩ ＭＯＳ场效应晶体管的阈值电压与背栅偏置的依赖关系，对漏源击穿的Ｓｎａｐｂａｃｋ特性进行分析，介绍了薄层ＣＭＯＳ／ＳＩＭＯＸ制作工艺，给出了全耗尽ＣＭＯＳ／ＳＯＩ电路的测试结果。     

全耗尽CMOS／SOI技术的研究进展

ＳＯＩ材料技术的成熟，为功耗低，抗干扰能力强，集成度高，速度快的ＣＭＯＳ／ＳＯＩ器件的研制提供了条件，分析比较了ＣＭＯＳ／ＳＯＩ器件与体硅器件的差异，介绍了国外薄膜全耗尽ＳＯＩ技术的发展和北京大学微电子所的研究成果。     

Fully depleted CMOS/SOI device design guidelines for low-powerapplications

We report the fully depleted (FD) CMOS/SOI device design guidelines for low-power applications. Optimal technology, device and circuit parameters are derived and compared with bulk CMOS based design. The differences and similarities are summarized. Device design guidelines using devices with L=0.1 μm for FDSOI low-power applications are presented using an empirical drain saturation current model fitted to experimental data. The model is verified in the deep-submicron regime by two-dimensional (2-D) simulation. For L=0.1 μm FDSOI low-power technology, optimum speed and lower-power occurs at V_dd=3V_th and V_dd=1.5 V_th, respectively. Optimum buried oxide thickness is found to be between 300 and 400 nm for low-power applications. Optimum transistor sizing is when the driver device capacitance is 0.3 times the total load capacitance. Similarly optimum gate oxide thickness is when the driver device gate capacitance is 0.2-0.6 times the total load capacitance for performance and 0.1-0.2 for low-power, respectively. Finally optimum stage ratio for driving large loads is around 2-4 for both high-performance and low-power     

An SOI LDMOS/CMOS/BJT technology for integrated power amplifiersused in wireless transceiver applications

This paper describes a SOI LDMOS/CMOS/BJT technology that can be used in portable wireless communication applications. This technology allows the complete integration of the front-end circuits with the baseband circuits for low-cost/low-power/high-volume single-chip transceiver implementation. The LDMOS transistors (0.35 μm channel length, 3.8 μm drift length, 4.5 GHz f_T and 21 V breakdown voltage), CMOS transistors (1.5 μm channel length, 0.8/-1.2 V threshold voltage), lateral NPN transistor (18 V BV_CBO and h _FE of 20), and high Q-factor (up to 6.1 at 900 MHz and 7.2 at 1.8 GHz) on-chip inductors are fabricated. A fully-functional high performance integrated power amplifier for 900 MHz wireless transceiver application is also demonstrated     

Fully-depleted SOI CMOS for analog applications

Fully-depleted (FD) SOI MOSFETs offer near-ideal properties for analog applications. In particular their high transconductance to drain current ratio allows one to obtain a higher gain than from bulk devices, and the reduced body effect permits one to fabricate more efficient pass gates. The excellent behavior of SOI MOSFETs at high temperature or at gigahertz frequencies is outlined as well     

高速全耗尽CMOS/SOI2000门门海阵列

本文对全耗尽CMOS/SOI 2000门门海进行了研究,阵列采用宏单元结构,每个宏单元包括2×8个基本单元和8条布线通道,其尺寸为:92μm×86μm.2000门门海阵列采用0.8μm全耗尽工艺,实现了101级环形振荡器和4~128级分频器电路,在工作电压为5V时,0.8μm全耗尽CMOS/SOI 101级环振的单级延迟为45ps.     

Fully integrated CMOS fractional-N frequency divider for wide-band mobile applications with spurs reduction

A spurs reduction fractional-N frequency divider with a frequency range which is 3.5 times larger than that of a conventional fractional-N divider is presented in this paper. A 1.2-GHz quadrature voltage-controlled oscillator (VCO) is designed as the input source of the frequency divider. The circuit was fabricated using the 0.25-/spl mu/m CMOS technology. The power consumption of the frequency divider and the quadrature VCO are 3 and 6 mW, respectively, at a 2-V supply.     

CMOS photodiode with enhanced responsivity for the UV/blue spectralrange

A new photodiode for the UV/blue spectral range, which can be integrated monolithically with CMOS circuits, is presented. Such optoelectronic integrated circuits (OEICs) with a high sensitivity in the UV/blue spectral range are needed in near-future optical storage systems like digital versatile disk (DVD) or digital video recording (DVR). At 400 nm, our so-called finger photodiode achieves a responsivity of 0.23 A/W corresponding to a quantum efficiency η of 70% [with an antireflection coating (ARC)] and rise and fall times of 1.0 ns and 1.1 ns, respectively. The finger photodiode can be used in the red spectral range, too. At 638 nm, the responsivity is 0.49 A/W (η=95%) and rise and fall times of less than 2.3 ns are achieved. For the integration of the finger photodiode in an industrial 1 μm twin-well CMOS process, only one additional mask is needed in order to block out the threshold voltage implantation in the photo-active region     

Nanopatterned UV curable hydrogels for biomedical applications

With an increasing use of emerging patterning technologies such as UV-NIL in biotechnological applications there is at the same time a raising demand for new material for such applications. Here we present a PEG based precursor mixed with a photoinitiator to make it UV sensitive as a new material aimed at biotechnological applications. Using HSQ patterned quartz stamps we observed excellent pattern replication indicating good flow properties of the resist. We were able to obtain imprints with <20 nm residual layer. The PEG based resist has hydrogel properties and it swelling in water was observed by AFM.     

Fully integrated 10 GHz CMOS VCO

A differential voltage-controlled oscillator has been designed to operate in the 10 GHz band using a 0.25 μm CMOS process and low Q integrated inductors. The low gain and low Q problems of the components are overcome by the deployment of the cascode configuration with negative conductance generation to enhance the loop gain and Q value. PMOS varactors are used for varying the oscillating frequency from 9.7 to 11.4 GHz. The phase noise at 400 kHz offset is from -101 dB/Hz at the low frequency end to -87 dB/Hz at the high frequency end     

Fully integrated CMOS UWB pulse generator

The design of a fully integrated CMOS ultra-wideband (UWB) pulse generator for the 3.1-10.6 GHz frequency band is presented. The pulse generation is based on the filter impulse response technique. With such a technique, the pulse matches the FCC mask with no need for an expensive external filter. The layout of this circuit in a 0.13 mum CMOS technology shows a surface area of less than 0.57 mm² and a power consumption of around 20 mW     

Vertically integrated SOI circuits for low-power and high-performance applications

Vertical integration offers numerous advantages over conventional structures. By stacking multiple-material layers to form double gate transistors and by stacking multiple device layers to form multidevice-layer integration, vertical integration can emerge as the technology of choice for low-power and high-performance integration. In this paper, we demonstrate that the vertical integration can achieve better circuit performance and power dissipation due to improved device characteristics and reduced interconnect complexity and delay. The structures of vertically integrated double gate (DG) silicon-on-insulator (SOI) devices and circuits, and corresponding multidevice-layer (3-D) SOI circuits are presented; a general double-gate SOI model is provided for the study of symmetric and asymmetric SOI CMOS circuits; circuit speed, power dissipation of double-gate dynamic threshold (DGDT) SOI circuits are investigated and compared to single gate (SG) SOI circuits; potential 3-D SOI circuits are laid out. Chip area, layout complexity, process cost, and impact on circuit performance are studied. Results show that DGDT SOI CMOS circuits provide the best power-delay product, which makes them very attractive for low-voltage low-power applications. Multidevice-layer integration achieves performance improvement by shortening the interconnects. Results indicate that up to 40% of interconnect performance improvements can be expected for a 4-device-layer integration.     

基于手机应用的集成无源器件滤波器的线性180纳米绝缘体硅天线开关模组

A broadband monolithic linear single pole, eight throw （SP8T） switch has been fabricated in 180 nm thin film silicon-on-insulator （SOI） CMOS technology with a quad-band GSM harmonic filter in integrated passive devices （IPD） technology, which is developed for cellular applications. The antenna switch module （ASM） features 1.2 dB insertion loss with filter on 2G bands and 0.4 dB insertion loss in 3G bands, less than -45 dB isolation and maximum -103 dB intermodulation distortion for mobile front ends by applying distributed architecture and adaptive supply voltage generator.     

Fully integrated CMOS nano-particle assembly circuit for biological detections

Recently, along with the booming of research and production of CMOS Integrated Bio-sensing System, selective assembly of organic nano-particles on the on-chip electrodes, which serves for specific bio-sensing and detection purposes, is in high demand in areas like biological analysis and detection, DNA probing and surveying systems and etc. In this paper, a fully integrated bio-circuit targeting at electrical selective assembly of charged nano-particles is proposed and designed in SMIC 0.18 μm CMOS mixed signal process. The proposed circuit integrates the 16 pixels of 19 μm × 19 μm electrode array, counter electrode, potentiostat circuit, digital decoding circuit, as well as control logics on a single chip, and provides a rail-to-rail range of assembling voltage, a potential resolution of 8 bit, and a maximal assembling current up to 459 μA, biased at a current of 1 μA. Meanwhile, a novel electrode-reuse scheme is also proposed to further simplify the architecture and save chip area as well, without degrading the functionalities. Experimental results from on-chip selective assembly of 50 nm polystyrene nano-particles are included and discussed to verify the feasibility of the proposed circuits.     

Fully integrated 5.35-GHz CMOS VCOs and prescalers

Two 5.35-GHz monolithic voltage-controlled oscillators (VCOs) and two prescalers have been fabricated in a digital 0.25-μm CMOS process. One VCO uses p⁺/n-well diodes, while the other uses MOS varactors, Q of 57 at 5.5 GHz and 0 V bias (low-Q condition) for a p ⁺/n-well varactor has been achieved. For an MOS varactor, it is possible to achieve a quality factor of 140 at 5.5 GHz. The tuning ranges of the VCOs are >310 MHz, and their phase noise is <-116.5 dBc/Hz at a 1-MHz offset while consuming ~7 mW power at V_DD=1.5 V. The low phase noise is achieved by using only PMOS transistors in the VCO core and by optimizing the resonator layout. The prescalers utilize a variation of the source-coupled logic. The power consumption is 4.1 mW at 1.5-V V_DD and 5.4 GHz. By widening the transistors in the first three divide-by-two stages, the maximum operating frequency is increased to 9.96 GHz at V_DD=2.5 V     

45ps的超高速全耗尽CMOS/SOI环振

亚微米全耗尽 SOI( FDSOI) CMOS器件和电路经过工艺投片 ,取得良好的结果 ,其中工作电压为 5V时 ,0 .8μm全耗尽 CMOS/ SOI1 0 1级环振的单级延迟仅为 45ps;随着硅层厚度的减薄和沟道长度的缩小 ,电路速度得以提高 ,0 .8μm全耗尽 CMOS/ SOI环振比 0 .8μm部分耗尽 CMOS/ SOI环振快 30 % ,比 1 μm全耗尽 CMOS/ SOI环振速度提高 1 5% .