用于实时目标检测的高速可编程视觉芯片

视觉芯片是一种高速、低功耗的智能视觉处理系统芯片,在生产生活中有广阔的应用前景。文中提出了一种新型的可编程视觉芯片架构,该架构的设计考虑了传统计算机视觉算法和卷积神经网络的运算特点,使其能够同时高效地支持这两类算法。该视觉芯片集成了可编程的多层次并行处理阵列、高速数据传输通路和系统控制模块,并采用65 nm标准CMOS工艺制程流片。测试结果表明:视觉芯片在200 MHz系统时钟下达到413GOPS的峰值运算性能,能够高效地完成包括完成人脸识别、目标检测等多种计算机视觉和人工智能算法。该视觉芯片在可编程度、运算性能以及能耗效率等方面都大大超越了其他视觉芯片。     

A programmable focal-plane MIMD image processor chip

An 80×78 pixels vision chip for focal-plane image processing is presented. The chip employs a Multiple-Instruction-Multiple-Data (MIMD) architecture to provide five spatially processed images in parallel. The size, configuration, and coefficients of the spatial kernels are programmable. The chip's architecture allows the photoreceptor cells to be small and parked densely by performing all computations on the read-out, away from the array. The processing core uses digitally programmed current-mode analog computation. Operating at 9.6 K frames/s in 800-lux ambient light, the chip consumes 4 mW from a 2.5-V power supply. Performing 11×11 spatial convolutions, an equivalent computation (5.5 bit scale-accumulate) rate of 12.4 GOPS/mW is achieved using 22 mm² in a 1.2-μm CMOS process. The application of the chip to line-segment orientation detection is also presented     

A general-purpose processor-per-pixel analog SIMD vision chip

A smart-sensor VLSI circuit suitable for focal-plane low-level image processing applications is presented. The architecture of the device is based on a fine-grain software-programmable SIMD processor array. Processing elements, integrated within each pixel of the imager, are implemented utilising a switched-current analog microprocessor concept. This allows the achievement of real-time image processing speeds with high efficiency in terms of silicon area and power dissipation. The prototype 21 /spl times/ 21 vision chip is fabricated in a 0.6 /spl mu/m CMOS technology and achieves a cell size of 98.6 /spl mu/m /spl times/ 98.6 /spl mu/m. It executes over 1.1 giga instructions per second (GIPS) while dissipating under 40 mW of power. The architecture, circuit design and experimental results are presented in this paper.     

Mixed signal SIMD processor array vision chip for real-time image processing

A prototype vision chip has been designed that incorporates a 20 × 64 array of processing elements on a 31 μm pitch. Each processor element includes 14 bits of digital memory in addition to seven analogue registers. Digital operands include NOR and NOT with operations of diffusion, subtraction, inversion and squaring available in the analogue domain. The cells of the array can be configured as an asynchronous propagation network allowing operations such as flood filling to occur with times of ~1 μs across the array. Exploiting this feature allows the chip to recognise the difference between closed and open shapes at 30,000 frames per second. The chip is fabricated in 0.18 μm CMOS technology.     

硬件检索机芯片

在当前飞速发展的信息时代,随着信息量不断爆炸性增长,对信息的快速检索也提出了更高的要求。现在,单片半导体存储器的容量已达到了G位,单个硬盘的容量已超过了百G字节,基本保证了对大数据量信息存储的要求。但如何从海量存储器中快速地检索到需要的信息,这也就成为了一个严峻的课题。     

A programmable analog neural network chip

A generic chip is implemented in CMOS to facilitate studying networks by building them in analog VLSI. By utilizing the well-known properties of charge storage and charge injection in a novel way, the authors have achieved a high enough level of complexity (>10³ weights and 10 bits of analog depth) to be interesting, in spite of the limitation of a modest 6.00×3.5-mm² die size required by a multiproject fabrication run. If the cell were optimized to represent fixed-weight networks by eliminating weight decay and bidirectional weight changes, the density could easily be increased by a factor of 2 with no loss in resolution. Once a weight change vector has been written to the RAM cells, charge transfers can be clocked at a rate of 2 MHz, corresponding to peak learning rates of 2×10⁹ weight changes/second and exceeding the throughput of `neural network accelerators' by two orders of magnitude     

A configurable convolution chip with programmable coefficients

Describes the architecture and implementation of a bit-level configurable convolver array. The systolic field supports a configuration during operation in terms of number of taps and coefficient word length. A chip has been designed in 1.5- mu m CMOS using a full-custom design style which contains 112586 transistors on an active area of 46 mm/sup 2/. The configurability consumes only 9% of that area. The prototypes are shown to be fully functional up to 20 MHz. An extension of the architecture for optimized calculation of transformations is also presented.<>     

A programmable CORDIC chip for digital signal processingapplications

A chip implementing the coordinate rotation digital computer (CORDIC) algorithm is described. It contains a 10-MHz 16-b fixed-point CORDIC arithmetic unit, 2-kb RAM, a controller, and input/output (I/O) registers. A modified data-path architecture allows cross-wire free data flow. The chip design involved development of optimized carry-select adders and a modified programmable-logic-array (PLA) cell layout, which allows speed increase in single-layer metal technology. The authors designed, fabricated, and tested a general-purpose fully parallel programmable CORDIC chip in CMOS technology and developed optimal iteration sequences     

真正的单芯片可编程SOC

可编程的SOC:两芯片系统与真正单 芯片系统 系统级集成仍然是半导体产业中的 标题新闻。正在进行的工作把几乎是全 部的系统功能集成到单个硅片上。片上 系统（SOC）可以提供更好的性能、更低 的功耗、更小的印制板空间,以及更低的 成本,因而受到人们的青睐。片上系统传 统上一直是用掩模ASIC去实现。但是, ASIC的不可重用的工程费用达到每次设 计25万美元或更多,最低订购量大,设 计周期长。因此,只适合在批量大、能够 承受得起这种成本的项目上使用。 几家IC厂商已经推出一种新的混合 型SOC器件,即可编程片上系统。它们     

A new semi-flat architecture for high speed and reduced area CORDIC chip

In this contribution we present a new CORDIC architecture called ‘semi-flat’ which reduces considerably the latency time and the amount of hardware. In our semi-flat architecture the first rotations are executed with an unfolded scheme but the remaining iterations are flattened using a fast redundant addition tree. Detailed comparisons with other major contributions show that our semi-flat redundant CORDIC is 30% faster and occupy 39% less silicon area.     

高速单片数字相关器VLSI结构研究

提出了一种高速单片数字相关器VLSI结构设计方法,结合扩频解扩芯片的实际需要,设计了包含16路数字相关器、集成规模达20万门的试验芯片,采用0.5μm三层金融CMOS工艺制造,测试表明,在3.3V工作电压和60MHz工作频率下,芯片的各项性能均达到设计要求。     

A programmable multi-channel CMOS pulser chip to drive ultrasonicarray transducers

This paper describes the development of a 16-channel programmable pulse generator Application Specific Integrated Circuit (ASIC). The General Purpose Pulser Chip (GPPC-16) can supply pulses delayed by up to 0.5 ms with a 1 ns time resolution. By employing novel design techniques, this has been achieved in standard CMOS technology. The design employs a CMOS delay line in conjunction with a phase-locked-loop. In this way a 16-phase clock is generated, which can drive 16 programmable counters. Currently the chip is being used to drive ultrasonic transducer arrays. The construction of these piezoelectric polymer arrays is also briefly discussed     

A machine vision system for high speed object tracking using a moments algorithm

A system has been developed for tracking the motion of objects in two dimensions in real-time. The system consists of a conventional CCD camera linked to a transputer-based frame grabber and an array of nine transputers. A parallel moments algorithm is used to extract the co-ordinates of the object's centre of gravity and orientation at field rate, i.e. 60 Hz. Since the position data are made available in real-time—with a small time delay—the system has the potential for inclusion in a feedback loop. Results are presented for tracking the trajectory of a chocolate bar diverted by an air jet. The potential of the system for higher sampling rates—up to 200 Hz—is discussed.     

Bi-i: a standalone ultra high speed cellular vision system

The Bi-i standalone cellular vision system is introduced and discussed. In the first part, the underlying sensor and system level architectures are presented and various implementations are overviewed. This computing platform consists of state-of-the-art sensing, cellular sensing-processing, digital signal processing and communication devices that make it possible to use the system as an ideal computing platform for combined topographic and non-topographic calculations in sensing-processing-actuation scenarios. In the second part of the paper, ultra-high frame rate laboratory experiments are shown and discussed to highlight the most peculiar features of the system and its applicability in various industrial quality control areas. The overview underlines the potentials of the Bi-i vision system for unmanned intelligent vehicle applications in visual exploration, identification, tracking and navigation.     

A 640-Mb/s 2048-bit programmable LDPC decoder chip

A 14.3-mm/sup 2/ code-programmable and code-rate tunable decoder chip for 2048-bit low-density parity-check (LDPC) codes is presented. The chip implements the turbo-decoding message-passing (TDMP) algorithm for architecture-aware (AA-)LDPC codes which has a faster convergence rate and hence a throughput advantage over the standard decoding algorithm. It employs a reduced complexity message computation mechanism free of lookup tables, and features a programmable network for message interleaving based on the code structure. The chip decodes any mix of 2048-bit rate-1/2 (3,6)-regular AA-LDPC codes in standard mode by programming the network, and attains a throughput of 640 Mb/s at 125 MHz for 10 TDMP-decoding iterations. In augmented mode, the code rate can be tuned up to 14/16 in steps of 1/16 by augmenting the code. The chip is fabricated in 0.18-/spl mu/m six-metal-layer CMOS technology, operates at a peak clock frequency of 125 MHz at 1.8 V (nominal), and dissipates an average power of 787 mW.     

A programmable analog cellular neural network CMOS chip for highspeed image processing

A high speed analog image processor chip is presented. It is based on the cellular neural network architecture. The implementation of an analog programmable CNN-chip in a standard CMOS technology is discussed. The control parameters or templates in all cells are under direct user control and are tunable over a continuous value range from 1/4 to 4. This tuning property is implemented with a compact current scaling circuit based on MOS transistors operating in the linear region. A 4×4 CNN prototype system has been designed in a 2.4 μm CMOS technology and successfully tested. The cell density is 380 cells/cm² and the cell time constant is 10 μs. The current drain for a typical template is 40 μA/cell. The real-time image processing capabilities of the system are demonstrated. From this prototype it is estimated that a 128×128 fully programmable analog image processing system can be integrated on a single chip using a standard digital submicron CMOS technology. This work demonstrates that powerful high speed programmable analog processing systems can be built using standard CMOS technologies     

A wide speed range and high precision position and velocity measurements chip with serial peripheral interface

This paper presents a VLSI chip, with a serial peripheral interface (SPI), that obtains position and velocity measurements from incremental optical encoder feedback. It combines period and frequency countings to provide velocity estimates with good dynamic behavior over a wide speed range (10 Hz-50 MHz). By sensing the velocity of the encoder, it reserves the computational power of a supervisory microcontroller, and subsequently enhances the performance of the total system. It is compact with lower power consumption when compared to traditional FPGA implementations. Although designed for use in the control unit of a medical robot with 34-axes and tight space and power constraints, it can be readily used in other applications. It is implemented in a 2P3 M 0.5 μm CMOS process and consumes 4.82 mW power with active area of 0.45 mm².     

基于单片机的程控放大器设计

设计了一种基于单片机的程控放大器.设计主要包括三大部分,即以单片机、模拟开关以及所连的电阻网络作为核心,键盘输入和液晶显示模块.采用CD4053模拟开关,STC89C52单片机,用LCD128*64进行实时显示放大倍数,从而达到程控放大的目的.