High Heat Flux Two-Phase Cooling in Silicon Multimicrochannels

This paper presents performances of two-phase cooling of a chip at very high heat flux with refrigerant R236fa in a silicon multimicrochannel heat sink. This heat sink was composed of 134 parallel channels, 67 $mu {hbox {m}}$ wide, 680 $mu {hbox {m}}$ high, and 20 mm long, with 92-$mu {hbox {m}}$ -thick fins separating the channels. The base heat flux was varied from 3 to 255 ${hbox {W/cm}}^{2}$ , the volume flow rate from 0.18 to 0.67 l/min, and the exit vapor quality from 0 to 80%. The working pressure and saturation temperature were set at 273 kPa and 25 $^{circ}{hbox {C}}$, respectively. The present database includes 1040 local heat transfer coefficients. The base temperature of the chip could be maintained below 52 $^{circ}{hbox {C}}$ while dissipating 255 ${hbox {W/cm}}^{2}$ with 10 $~^circ{hbox {C}}$ of inlet subcooling and 90 kPa of pressure drop. A comparison of the respective performances with an extrapolation of the present results shows that two-phase cooling should be able to cool the chip 13 K lower than liquid cooling for the same pumping power at a base heat flux of 350 ${hbox {W/cm}}^{2}$.      

Near-Infrared p-i-n Ge-on-Si Photodiodes for Silicon Integrated Receivers

We investigate and characterize p-i-n near-infrared photodiodes fabricated in Ge-on-Si by reduced-pressure chemical vapor deposition, a technology compatible with silicon processing. The detectors exhibit remarkably low dark current densities of 1 ${hbox{mA/cm}}^{2}$ at unity reverse bias and high responsivities of 200 mA/W at 1.55 $mu{hbox{m}}$. We evaluated their small-signal resistance, capacitance, and bandwidth as well as eye-diagrams at 2.5 and 10 Gbit/s .      

Advanced Low-Noise X-Ray Readout ASIC for Radiation Sensor Interfaces

A VLSI readout front-end architecture, dedicated for X-ray imaging, using specific capacitive silicon detectors, with capacitance ranging from 2 to 10 pF, is described. Critical design issues such as the noise optimization and the shaper implementation technique are addressed and the first performance—test results of a fabricated prototype in a 0.35- $mu{hbox {m}}$ 3.3-V CMOS process, are presented. Important feature of the design is the novel ${CR-RC}^{2}$ pulse-shaper configuration since in this section, transconductor circuits are used in order to provide a broad range of continuous variable peaking time, programmable gain and adjustable undershoot while still maintaining the noise performance and the required linearity of the specific radiation detection application. Regarding the readout ASIC performance characteristics, the power consumption is 1 mW per channel, the equivalent noise charge at 1.81- $mu{hbox {s}}$ peaking time is 382 ${rm e}^{-}$ plus 21 ${rm e}^{-}$ per picofrard of detector capacitance. The topology achieves a conversion gain equal to 3.31 mV/fC and a linearity of 0.69%.      

A Hybrid Electrooptic Microring Resonator-Based $1 times 4times 1$ ROADM for Wafer Scale Optical Interconnects

Pairing high-quality factor $(Q)$ silicon-on-insulator microring resonators with rapidly tunable organic electrooptic claddings has allowed the first demonstration of a silicon-organic hybrid electrooptic reconfigurable optical add/drop multiplexer (ROADM). A coplanar electrode geometry provides up to 0.36 GHz/V of electrooptic voltage tuning for each channel, corresponding to an electrooptic coefficient of $r_{33}=64 hbox{pm/V}$ at wavelengths around 1550 nm. Individual ring resonator devices have 40- $mu{hbox {m}}$ ring radii, 2.7-nm free spectral range, and tuning ranges of 180 GHz. The $1times 4times 1$ ROADM has a footprint of less than 1 ${hbox {mm}}^{2}$ and has been shown to reconfigure in less than a microsecond.      

Novel Design of a 2.5-GHz Fully Integrated CMOS Butler Matrix for Smart-Antenna Systems

This paper presents a novel design of monolithic 2.5-GHz 4 $,times,$4 Butler matrix in 0.18- $mu$m CMOS technology. To achieve a full integration of smart antenna system monolithically, the proposed Butler matrix is designed with the phase-compensated transformer-based quadrature couplers and reflection-type phase shifters. The measurements show an accurate phase distribution of ${hbox{45}}{pm}{hbox{3}}^{circ}, ~{hbox{135}} pm {hbox{4}}^{circ}, ~ -{hbox{45}} pm {hbox{3}}^{circ}, ~{hbox{and}}~ -{hbox{135}} pm {hbox{4}}^{circ}$ with amplitude imbalance less than 1.5 dB. The antenna beamforming capability is also demonstrated by integrating the Butler matrix with a 1$,times,$ 4 monopole antenna array. The generated beams are pointing to $-{hbox{45}}^{circ}, ~ -{hbox{15}}^{circ}$ , 15$^{circ}$, and 45$^{circ}$, respectively, with less than 1$^{circ}$ error, which agree very well with the predictions. This Butler matrix consumes no dc power and only occupies the chip area of 1.36 $,times,$1.47 mm$^{2}$ . To our knowledge, this is the first demonstration of the single-chip Butler matrix in CMOS technology.      

Enhanced Hot Spot Cooling Using Bonded Superlattice Microcoolers With a Trench Structure

In this paper, we describe how to use Si/SiGe superlattice microcoolers to cool the target hot spots and how a trench structure could enhance its cooling performance. The microcooler chip is gold fusion bonded with a 65 $mu{hbox {m}}$ -thick silicon chip, where heaters are fabricated on the opposite of fusion bonding layer to simulate the hot spots. Our 3-D electrothermal simulations showed that with a trench structure, the maximum cooling and cooling power density could be doubled at hot spot region. Our experimental prototype also demonstrated a maximum cooling of ${sim 2}~^{circ} {hbox {C}}$ reduction at hot spot or a maximum cooling power density of 110 $~{hbox {W/cm}}^{2}$ with trench structure as compared with the 0.8 $^{circ}{hbox {C}}$ cooling without trench structure. This two-chip bonded configuration will allow the integration of spot coolers and ICs without impact on microelectronics processing process. It could be a potential on-chip hot spot cooling solution.      

Low-Threshold Strained Quantum-Well GaSb-Based Lasers Emitting in the 2.5- to 2.7-$mu$ m Wavelength Range

GaInAsSb–GaSb strained quantum-well (QW) ridge waveguide diode lasers emitting in the wavelength range from 2.51 to 2.72 $ mu{hbox {m}}$ have been grown by molecular beam epitaxy. The devices show ultralow threshold current densities of 44 $hbox{A}/{hbox {cm}}^{2}$ (${L}rightarrow infty $) for a single QW device at 2.51 $ mu{hbox {m}}$, which is the lowest reported value in continuous-wave operation near room temperature (15 $^{circ}hbox{C}$) at this wavelength. The devices have an internal loss of 3 ${hbox {cm}}^{-1}$ and a characteristic temperature of 42 K. By using broader QWs, wavelengths up to 2.72 $mu{hbox {m}}$ could be achieved.      

A Compact Four-Wavelength Quantum-Cascade Laser Source

A four-wavelength quantum-cascade (QC) laser source that operates using a single current channel is presented. The source includes two different heterogeneous cascade QC lasers, one with emission wavelengths of 7.0 $mu{hbox {m}}$ and 11.2 $mu{hbox {m}}$, and the other with 8.7 $mu{hbox {m}}$ and 12.0 $mu{hbox {m}}$ . For 3.0-mm and 3.5-mm cavity lengths, QC lasers with emission wavelengths of 8.7, 11.2, and 12.0 $mu{hbox {m}}$ have threshold current densities within less than a factor of 2, which allows them to be conveniently driven in series by a single current source.      

Active Matrix OTFT Display With Anodized Gate Dielectric

A complete process for an active-matrix (AM) organic thin-film transistor (OTFT) polymer dispersed liquid crystal (PDLC) display is presented. Evaporated pentacene is used as semiconductor. The display comprises 64$times$64 pixel, each with a pixel pitch of $({hbox{312.5}} times {hbox{312.5}}) mu{hbox{m}}^2$. The AM display is fabricated with standard photolithographic processes. Since all process temperatures are below 180$^{circ}$C the processes for the AM backplane can be easily transferred to plastic substrates like PEN or PET. Due to the thin anodically oxidized ${hbox{Al}}_2$ ${hbox{O}}_3$ gate dielectric with a thickness of 60 nm and $varepsilon_{rm r}=9$, driving voltages between 10 and 12 V are sufficient. To protect the pentacene against the PDLC, it is encapsulated with sputtered ${hbox{Ta}}_2 {hbox{O}}_5$ layer. After the passivation a field effect mobility of 0.2 ${hbox{cm}}^{2}/{hbox{V}}cdot{hbox{s}}$ is obtained for the OTFTs.      

A Fluxless and Low-Temperature Flip Chip Process Based on Insertion Technique

For heterogeneous materials assembly, the thermal expansion mismatch between the chip and the substrate is a roadblock for flip chip bonding of ultrafine-pitch $(leq 10 mu{hbox {m}})$ and large diagonal devices ( $geq$20 mm). Residual strains in bumps and device warpage have been calculated to evaluate the thermomechanical limits of a conventional flip chip soldering process using micro bumping. As a solution to overcome these limits, this paper describes a new patented flip-chip technology representing a technological breakthrough compared to conventional methods such as soldering or bonding through conductive adhesives. Electrical connections are performed by the insertion of metallic micro-tips in a ductile material. As a low-temperature process and fluxless technology, this method is adapted to fine-pitch and large devices. As a proof of concept, we present the bonding results obtained on fine-pitch large arrays of daisy chains with 500 $times$ 500 contacts and 30-$mu{hbox {m}}$ pitch. The electrical contact has been demonstrated and characterized in terms of resistance and yield.      

17 GHz RF Front-Ends for Low-Power Wireless Sensor Networks

A 17 GHz low-power radio transceiver front-end implemented in a 0.25 $mu{hbox {m}}$ SiGe:C BiCMOS technology is described. Operating at data rates up to 10 Mbit/s with a reduced transceiver turn-on time of 2 $mu{hbox {s}}$, gives an overall energy consumption of 1.75 nJ/bit for the receiver and 1.6 nJ/bit for the transmitter. The measured conversion gain of the receiver chain is 25–30 dB into a 50 $Omega$ load at 10 MHz IF, and noise figure is 12 $pm$0.5 dB across the band from 10 to 200 MHz. The 1-dB compression point at the receiver input is $-$37 dBm and ${hbox{IIP}}_{3}$ is $-$25 dBm. The maximum saturated output power from the on-chip transmit amplifier is $-$1.4 dBm. Power consumption is 17.5 mW in receiver mode, and 16 mW in transmit mode, both operating from a 2.5 V supply. In standby, the transceiver supply current is less than 1 $mu{hbox {A}}$.      

A $Q$ -Band Four-Element Phased-Array Front-End Receiver With Integrated Wilkinson Power Combiners in 0.18-$mu{{hbox{m}}}$ SiGe BiCMOS Technology

A four-element phased-array front-end receiver based on 4-bit RF phase shifters is demonstrated in a standard 0.18- $mu{{hbox{m}}}$ SiGe BiCMOS technology for $Q$-band (30–50 GHz) satellite communications and radar applications. The phased-array receiver uses a corporate-feed approach with on-chip Wilkinson power combiners, and shows a power gain of 10.4 dB with an ${rm IIP}_{3}$ of $-$13.8 dBm per element at 38.5 GHz and a 3-dB gain bandwidth of 32.8–44 GHz. The rms gain and phase errors are $leq$1.2 dB and $leq {hbox{8.7}}^{circ}$ for all 4-bit phase states at 30–50 GHz. The beamformer also results in $leq$ 0.4 dB of rms gain mismatch and $leq {hbox{2}}^{circ}$ of rms phase mismatch between the four channels. The channel-to-channel isolation is better than $-$35 dB at 30–50 GHz. The chip consumes 118 mA from a 5-V supply voltage and overall chip size is ${hbox{1.4}}times {hbox{1.7}} {{hbox{mm}}}^{2}$ including all pads and CMOS control electronics.      

AlN/GaN Insulated-Gate HEMTs With 2.3 A/mm Output Current and 480 mS/mm Transconductance

High-electron mobility transistors (HEMTs) based on ultrathin AlN/GaN heterostructures with a 3.5-nm AlN barrier and a 3-nm $hbox{Al}_{2}hbox{O}_{3}$ gate dielectric have been investigated. Owing to the optimized AlN/GaN interface, very high carrier mobility $(sim!!hbox{1400} hbox{cm}^{2}/hbox{V}cdothbox{s})$ and high 2-D electron-gas density $(sim!!kern1pthbox{2.7} times hbox{10}^{13} /hbox{cm}^{2})$ resulted in a record low sheet resistance $(sim !!hbox{165} Omega/hbox{sq})$. The resultant HEMTs showed a maximum dc output current density of $simkern1pt$2.3 A/mm and a peak extrinsic transconductance $g_{m,{rm ext}} sim hbox{480} hbox{mS/mm}$ (corresponding to $g_{m,{rm int}} sim hbox{1} hbox{S/mm}$). An $f_{T}/f_{max}$ of 52/60 GHz was measured on $hbox{0.25} times hbox{60} muhbox{m}^{2}$ gate HEMTs. With further improvements of the ohmic contacts, the gate dielectric, and the lowering of the buffer leakage, the presented results suggest that, by using AlN/GaN heterojunctions, it may be possible to push the performance of nitride HEMTs to current, power, and speed levels that are currently unachievable in AlGaN/GaN technology.      

Very High-Temperature Joints Between Si and Ag–Copper Substrate Made at Low Temperature Using InAg System

We present a fluxless bonding process between silicon and Ag–copper dual-layer substrate using electroplated indium/silver solder. The nucleation mechanism of In plated over Ag layer is first investigated. It is interesting to discover that In atoms react with underlying Ag to from ${hbox {AgIn}}_{2}$ compound layer during electroplating. A novel Ag laminating technique on Cu substrates is developed. The Ag cladding functions as a strain buffer to manage the large mismatch in coefficient of thermal expansion (CTE) between semiconductors such as Si (3 ${hbox {ppm}}/^{circ}{hbox {C}}$) and Cu (17 ${hbox {ppm}}/^{circ}{hbox {C}}$) substrates. To bond Si chips to the Ag layer on copper substrates, In-based alloy (InAg) is used. A fluxless bonding process is developed between Si/Cr/Au/Ag and Cu/Ag/In/Ag. The process is performed in 50-militorr vacuum to suppress solder oxidation. No flux is used. The resulting joints consist of three distinct layers of Ag, ${hbox {Ag}}_{2}{hbox {In}}$ and Ag. Microstructure and composition of the joints are examined using scanning electron microscope (SEM) with energy dispersive X-ray spectroscopy (EDX). Bonded samples are further annealed to convert the ${hbox {Ag}}_{2}{hbox {In}}$ phase into solid solution phase (Ag). The joint has a melting temperature above 850 $^{circ}{hbox {C}}$. This technique presents our success in overcoming the very large CTE mismatch between silicon and copper. It can be applied to mounting numerous high-power silicon devices to Cu substrates for various industrial applications.      

A Silicon Monolithic Phase-Inverter Rat-Race Coupler Using Spiral Coplanar Striplines and Its Application in a Broadband Gilbert Mixer

This paper realized a broadband uniplanar phase-inverter rat-race coupler using a standard silicon process, and then analyzed this coupler under a lossy condition. A phase inverter is employed in this coupler, not only to extend the operation bandwidth, but also to generate balanced outputs by providing equal lossy paths, while symmetrical spiral-shaped coplanar striplines (CPSs) are also utilized to shrink the coupler size, as well as to construct a phase inverter in the middle of one of spiral CPSs. The lossy CPS, when designed as a distortionless line, has a real characteristic impedance, and thus, perfect port matching of the coupler can be achieved at the center frequency. The operation frequency of this silicon monolithic rat-race coupler with the size of 0.5 ${hbox {mm}}^{2}$ is extremely wide and ranges from 5 to 23 GHz. The dissipated loss, transmission coefficient, and isolation of the rat-race coupler are approximately 5.5, $-$8, and below $-$25 dB, respectively. In addition, a wideband Gilbert micromixer with an integrated uniplanar phase-inverter rat-race coupler at the local oscillator port is demonstrated using 0.35-$mu{hbox {m}}$ SiGe BiCMOS technology. This mixer works from 2.5 to 13 GHz with 12-dB conversion gain, $-$16-dBm ${rm IP}_{1 {rm dB}}$, $-$4-dBm ${rm IIP}_{3}$, and 14-dB noise figure. The chip size of the mixer with an integrated coupler is approximately 1.4 mm $times$ 1.4 mm.      

A Sub-0.2$^{circ}/$ hr Bias Drift Micromechanical Silicon Gyroscope With Automatic CMOS Mode-Matching

This paper describes a system architecture and CMOS implementation that leverages the inherently high mechanical quality factor (Q) of a MEMS gyroscope to improve performance. The proposed time domain scheme utilizes the often-ignored residual quadrature error in a gyroscope to achieve, and maintain, perfect mode-matching (i.e., $sim$0 Hz split between the high-Q drive and sense mode frequencies), as well as electronically control the sensor bandwidth. A CMOS IC and control algorithm have been interfaced with a 60 $mu{hbox {m}}$ thick silicon mode-matched tuning fork gyroscope $({rm M}^{2}mathchar"707B {rm TFG})$ to implement an angular rate sensing microsystem with a bias drift of 0.16$^{circ}/{hbox{hr}}$. The proposed technique allows microsystem reconfigurability—the sensor can be operated in a conventional low-pass mode for larger bandwidth, or in matched mode for low-noise. The maximum achieved sensor Q is 36,000 and the bandwidth of the microsensor can be varied between 1 to 10 Hz by electronic control of the mechanical frequencies. The maximum scale factor of the gyroscope is 88 ${hbox{mV}}/^{circ}/{hbox{s}}$ . The 3$~$ V IC is fabricated in a standard 0.6 $ mu{hbox {m}}$ CMOS process and consumes 6 mW of power with a die area of 2.25 ${hbox {mm}}^{2}$.      

Fluxless Bonding of Silicon to Ag–Copper Using In–Ag With Two UBM Designs

A fluxless process of bonding silicon to Ag-cladded copper using electroplated In–Ag multilayer structure is developed. The Ag cladding on the copper substrate is a stress buffer to deal with the large mismatch in coefficient of thermal expansion (CTE) between semiconductors such as Si (3 ${hbox {ppm}}/^{circ}{hbox {C}}$) and Cu (17 ${hbox {ppm}}/^{circ}{hbox {C}}$). To manufacture Ag on copper substrate, two techniques are developed. The first is an electroplating process to fabricate a thick Ag layer. The second technique is a novel laminating process that bonds Ag foil directly on Cu substrate. On Si chips, two underbump metallurgy (UBM) structures are designed, Si/Cr/Au and Si/Cr/Ni/Au. To produce a solder layer, Si chips are electroplated with In followed by thin Ag. The thin Ag cap layer prevents oxidation of the inner In region. To achieve a fluxless feature, the bonding process is performed in a vacuum environment (50 mtorrs) to suppress indium oxidation. Compared to bonding in air, the oxygen content is reduced by a factor of 15 200. Using Cr/Au UBM structure, the silicon chip was detached from Cu substrate. The broken interface lies between Si/Cr and ${hbox {Ag}}_{2}{hbox {In}}$ IMC on Cu substrate. Using a new UBM design of Si/Cr/Ni/Au, high-quality joints are produced that comprise of three distinct layers of ${hbox {In}}_{7}{hbox {Ni}}_{3}$, ${hbox {Ag}}_{2}{hbox {In}}$ , and Ag. Microstructure and composition of the joints are studied using a scanning electron microscope (SEM) with energy dispersive X-ray spectroscopy (EDX).      

Low-Stress Thermosonic Copper Ball Bonding

Thermosonic ball bonding processes on test chips with Al metallized bonding pads are optimized with one Au and two Cu wire types, all 25 $mu{hbox {m}}$ diameter, obtaining average shear strengths of more than 120 MPa. The process temperature is $sim {hbox {110}}~^{circ}{hbox {C}}$. Ball bonds made with Cu wire show at least 15% higher shear strength than those made with Au wire. The estimated maximum shear strength $c_{pk}$ value determined for Cu ball bonding $(c_{pk}=3.7pm 1.2)$ is almost 1.5 times as large as that of the Au ball bonding process $(c_{pk}=2.3pm 0.9)$, where $LSL$ is 65.2 MPa. However, the ultrasound level required for Cu is approximately 1.3 times than that required for Au. Consequently, about 30% higher ultrasonic forces induced to the bonding pad are measured using integrated real-time microsensors. The accompanying higher stresses increase the risk of underpad damage. One way to reduce ultrasonic bonding stresses is by choosing the softer of the two Cu wire types, resulting in a measured ultrasonic force reduction of about 5%. A second way is to reduce the ultrasound level. While this causes the average shear strength to fall by 15%, the ultrasonic force falls by 9%. The $c_{pk}$ value does not change significantly, suggesting that a successful Cu ball bonding operation can be run with about 0.9 times the conventionally optimized ultrasound level. The process adjusted in this way reduces the extra stress observed with Cu wire compared to that observed with Au wire by 42%.      

$S$ - and $C$ -Band Ultra-Compact Phase Shifters Based on All-Pass Networks

Ultra-compact phase shifters are presented. The proposed phase-shifting circuits utilize the lumped element all-pass networks. The transition frequency of the all-pass network, which determines the size of the circuit, is set to be much higher than the operating frequency. This results in a significantly small chip size of the phase shifter. To verify this methodology, 5-bit phase shifters have been fabricated in the $S$ - and $C$ -band. The $S$ -band phase shifter, with a chip size of 1.87 mm $,times,$0.87 mm (1.63 mm $^{2}$), has achieved an insertion loss of ${hbox{6.1 dB}} pm {hbox{0.6 dB}}$ and rms phase-shift error of less than 2.8$^{circ}$ in 10% bandwidth. The $C$ -band phase shifter, with a chip size of 1.72 mm $,times,$0.81 mm (1.37 mm $^{2}$), has demonstrated an insertion loss of 5.7 dB $pm$ 0.8 dB and rms phase-shift error of less than 2.3 $^{circ}$ in 10% bandwidth.      

A Noise-Coupled Time-Interleaved Delta-Sigma ADC With 4.2 MHz Bandwidth, ${-}$ 98 dB THD, and 79 dB SNDR

This paper describes a wideband high-linearity $Delta Sigma $ ADC. It uses noise coupling combined with time interleaving. Two versions of a two-channel time-interleaved noise-coupled $Delta Sigma $ ADC were realized in a 0.18- $mu{hbox {m}}$ CMOS technology. Noise coupling between the channels increases the effective order of the noise-shaping loops, provides dithering, and prevents tone generation in all loops. Time interleaving enhances the effects of noise coupling. Using a 1.5 V supply, the device achieved excellent linearity (${rm SFDR} > {hbox {100~dB}}$, ${rm THD}= -{hbox {98~dB}}$) and an SNDR of 79 dB in a 4.2 MHz signal band.