LDPC译码方法研究及实现

本文主要研究了低密度校验码（LDPC码）的编译码方法及其硬件实现。在讨论几种主要的LDPC码的编译码方法的基础上，对LDPC译码错误产生原因进行了分析，提出了一种改进的置信传播译码算法——最小和算法，该算法在几乎没有增加运算复杂度的情况下，明显地提高了译码性能。同时，本文基于几何思想的LDPC码为例，提出了并串结合的FPGA实现方法，给出了仿真结果。     

LDPC编译码算法分析

低密度奇偶校验(LDPC)码是一种线性分组码,其纠错能力可以接近香农极限。针对LDPC码的编译码问题,分析了校验矩阵的构造方法。给出了LDPC码的编码算法以及算法的实现结构。分析了基于软判决的置信传播(BP)译码算法,并给出了可以进一步降低计算复杂度的简化译码方法。通过仿真对比了不同的译码算法在高斯信道下的译码性能。     

准循环LDPC码的部分并行译码算法

IEEE802.16e标准定义的准循环低密度奇偶校验(LDPC)码是一种线性分组码。针对LDPC码校验矩阵的稀疏准循环特性,对基于部分并行结构的归一化最小和(NMS)译码算法进行了研究,给出了译码信息量化和信息交换的方法。通过数值仿真验证了译码算法在高斯信道中的译码性能,并利用现场可编程门阵列(FPGA)对该译码算法进行了实现。     

一种全并行LDPC译码器及FPGA实现方法

低密度校验(Low-Density Parity-Check)码作为迄今为止性能接近香农限的前向纠错码(FEC)之一,在无线通信、卫星通信和无线网络技术等领域获得了广泛的应用。随着 5G 技术的发展,通信系统对传输速率的需求逐渐增加,更高的传输速率对 LDPC 译码器的吞吐量提出了更高的要求。本文给出了一种全并行 LDPC 译码器设计,并采用理论分析和仿真结果分析相结合的方法,对 LDPC 码的并行译码方法进行了研究,给出了全并行译码器的 FPGA 实现方法。     

多进制LDPC码编译码研究

低密度奇偶校验(LDPC)码是当前广泛应用的信道编码方式.多进制LDPC码在各类噪声的干扰下,纠错性能仍然极好,是如今信道编码学者重点研究方向.主要研究多进制LDPC码的编码和译码方法,通过软件仿真,分别对比不同编码和译码方法的纠错性能,并分析造成纠错性能差异的原因.主要对一种由二进制LDPC码中元素替换得到的四进制LDPC码,通过软件进行仿真分析,并最终得到5/6码率,采用16符号正交幅度调制(16QAM)方式的四进制LDPC码的编码结构.     

Rice信道下LDPC码密度进化的研究

应用低密度奇偶校验(LDPC)码译码消息的密度进化可以得到码集的噪声门限,依此评价不同译码算法的性能,并可以用来优化非正则LDPC码的次数分布对。该文首先以Rice信道下正则LDPC码为例,讨论了不同量化阶数及步长时BP,BP-based 和offset BP-based 3种译码算法的DDE(Discrete Density Evolution)分析,接着在offset BP-based译码算法的DDE分析基础上,采用差分进化方法对Rice信道下非正则LDPC码的次数分布对进行了优化,得出了相应的噪声门限。最后,给出了Rice信道下码率为1/2的优化非正则LDPC码的概率聚集函数(PMF)进化曲线。     

硬件可实现的LDPC译码算法研究

低密度奇偶校验(LDPC)码有着较强的纠错能力,已被确定为第四代移动通信技术中首选码字。分析对比了几种LDPC译码算法的过程,基于硬件可实现性这一研究热点,对传统的译码算法进行了优化,提出一种易于硬件实现的LDPC译码算法。仿真结果表明:归一化最小和算法在不增加迭代次数,码长较长的情况下也有着很好的译码性能,适合在LDPC译码器的硬件实现中推广。     

一种动态加权的LDPC译码方法

为了加快低密度奇偶校验（LDPC）码的译码速度,有效改善LDPC码的译码性能,针对校验节点更新过程中的对数似然比（LLR）值的大小,设计了一种LDPC码的动态加权译码方法。以IEEE 802.16e标准的奇偶校验矩阵为例,根据LLR值的变化规律,利用增长因子和抑制因子对和积译码算法和最小和译码算法进行动态加权。仿真结果显示,基于动态加权的译码方法相对于传统译码方法误码率都有明显改进,译码复杂度也有所降低。     

非正则LDPC码在AWGN信道中的性能研究

简单介绍了非正则低密度奇偶校验(Low Density Parity Check,LDPC)码的结构。研究了其对数域概率译码的和积算法(Sum Product Algorithm,SPA),并对该算法的主要公式进行了推导,给出了其迭代核心部分的C语言实现伪码。对一种基于802.16e直接编码法生成的非正则LDPC码在高斯信道下进行了仿真分析,表明中短码长的非正则LDPC码已经具有优异的纠错性能。     

低复杂度的LDPC码联合编译码构造方法研究

LDPC码因为其具有接近香农限的译码性能和适合高速译码的并行结构,已经成为纠错编码领域的研究热点。LDPC码校验矩阵的构造是基于稀疏的随机图,所以该类码字编码和译码的硬件实现比较复杂。以单位阵的循环移位阵为基本单元,构造LDPC码的校验矩阵,降低了LDPC码在和积算法下的译码复杂度。同时考虑到LDPC码的编码复杂度,给出了一种可以简化编码的结构。针对该方案构造的LDPC码,提出了消除其二分图上的短圈的方法。通过大量的仿真和计算分析,本文比较了这种LDPC码和随机构造的LDPC码在误码率性能,圈长分布以及最小码间距估计上的差异。     

光通信中一种基于有限域循环子群的QC-LDPC码构造方法

基于有限域循环子群方法提出了一种结构简单,可以灵活选择码长、码率,并且编译码复杂度低的准循环低密度奇偶校验(QC-LDPC)码构造方法。利用此方法构造出适合光通信系统传输的规则QC-LDPC(5334,4955)码。仿真结果表明该码型利用和积迭代译码算法在加性高斯白噪声信道中取得了很好的性能,比已广泛应用于光通信中的经典RS(255,239)码具有更好的纠错性能。因此所构造的QC-LDPC(5334,4955)码能较好地适用于高速长距离光通信系统。     

A CLASS OF LDPC CODE''''S CONSTRUCTION BASED ON AN ITERATIVE RANDOM METHOD

This letter gives a random construction for Low Density Parity Check (LDPC) codes, which uses an iterative algorithm to avoid short cycles in the Tanner graph. The construction method has great flexible choice in LDPC code's parameters including codelength, code rate, the least girth of the graph, the weight of column and row in the parity check matrix. The method can be applied to the irregular LDPC codes and strict regular LDPC codes. Systemic codes have many applications in digital communication, so this letter proposes a construction of the generator matrix of systemic LDPC codes from the parity check matrix. Simulations show that the method performs well with iterative decoding.     

Quasi-cyclic LDPC codes using overlapping matrices and their layered decoders

Quasi-cyclic (QC) low-density parity-check (LDPC) codes have the parity-check matrices consisting of circulant matrices. Since QC LDPC codes whose parity-check matrices consist of only circulant permutation matrices are difficult to support layered decoding and, at the same time, have a good degree distribution with respect to error correcting performance, adopting multi-weight circulant matrices to parity-check matrices is useful but it has not been much researched. In this paper, we propose a new code structure for QC LDPC codes with multi-weight circulant matrices by introducing overlapping matrices. This structure enables a system to operate on dual mode in an efficient manner, that is, a standard QC LDPC code is used when the channel is relatively good and an enhanced QC LDPC code adopting an overlapping matrix is used otherwise. We also propose a new dual mode parallel decoder which supports the layered decoding both for the standard QC LDPC codes and the enhanced QC LDPC codes. Simulation results show that QC LDPC codes with the proposed structure have considerably improved error correcting performance and decoding throughput.     

LDPC码相关技术研究

文章首先简要介绍了LDPC码适于新一代移动通信应用的良好特性,接着阐述了码的结构和二分图分析方法,对LDPC码的几种基本编码技术进行了讨论,最后论述了LDPC码的MP译码算法基本思想,并对MP算法集合中的特例信度传播算法(BP)进行了评述.     

Estimation of the exponent of the decoding error probability for a special generalized LDPC code

A special construction of a generalized low-density parity-check (LDPC) code and a low-complexity algorithm for his code decoding are proposed. A lower estimate of the exponent of the decoding error probability is obtained for the considered code and the decoding algorithm. This estimate leads the conclusion that, in an ensemble of considered LDPC codes, there are codes with rates as high as the code capacity and the exponent of the decoding error probability exceeds zero.     

A CLASS OF LDPC CODE’S CONSTRUCTION BASED ON AN ITERATIVE RANDOM METHOD

This letter gives a random construction for Low Density Parity Check （LDPC） codes, which uses an iterative algorithm to avoid short cycles in the Tanner graph. The construction method has great flexible choice in LDPC code＇s parameters including codelength, code rate, the least girth of the graph, the weight of column and row in the parity check matrix. The method can be applied to the irregular LDPC codes and strict regular LDPC codes. Systemic codes have many applications in digital communication, so this letter proposes a construction of the generator matrix of systemic LDPC codes from the parity check matrix. Simulations show that the method performs well with iterative decoding.     

Optimal Overlapped Message Passing Decoding of Quasi-Cyclic LDPC Codes

Efficient hardware implementation of low-density parity-check (LDPC) codes is of great interest since LDPC codes are being considered for a wide range of applications. Recently, overlapped message passing (OMP) decoding has been proposed to improve the throughput and hardware utilization efficiency (HUE) of decoder architectures for LDPC codes. In this paper, we first study the scheduling for the OMP decoding of LDPC codes, and show that maximizing the throughput gain amounts to minimizing the intra- and inter-iteration waiting times. We then focus on the OMP decoding of quasi-cyclic (QC) LDPC codes. We propose a partly parallel OMP decoder architecture and implement it using FPGA. For any QC LDPC code, our OMP decoder achieves the maximum throughput gain and HUE due to overlapping, hence has higher throughput and HUE than previously proposed OMP decoders while maintaining the same hardware requirements. We also show that the maximum throughput gain and HUE achieved by our OMP decoder are ultimately determined by the given code. Thus, we propose a coset-based construction method, which results in QC LDPC codes that allow our optimal OMP decoder to achieve higher throughput and HUE.     

空间耦合LDPC码在AWGN信道下的性能分析

空间耦合LDPC(Spatially Coupled LDPC,SC-LDPC)码由于阈值饱和特性,被证明是未来无线通信系统的有力候选码型。SC-LDPC码是一种卷积LDPC码,在二元无记忆对称信道下采用置信传播译码算法时具有逼近香农限的性能。对SC-LDPC码的构造及其经典的置信传播译码算法进行了阐述,并在加性高斯白噪声信道下进行了性能仿真和分析。仿真结果表明,SC-LDPC码的约束长度越长或最大迭代次数越大,其性能就越逼近香农容量限。SC-LDPC码在误码率为10-5、最大迭代次数为100时,码长20000比码长10000大约有0.68 dB的增益;在误码率为10-5、码长为10000时,最大迭代次数100的SC-LDPC码比最大迭代次数10的码大约有0.66 dB的增益。仿真结果有效验证了SCLDPC码在无线通信系统中的良好性能。     

A Flexible LDPC/Turbo Decoder Architecture

Low-density parity-check (LDPC) codes and convolutional Turbo codes are two of the most powerful error correcting codes that are widely used in modern communication systems. In a multi-mode baseband receiver, both LDPC and Turbo decoders may be required. However, the different decoding approaches for LDPC and Turbo codes usually lead to different hardware architectures. In this paper we propose a unified message passing algorithm for LDPC and Turbo codes and introduce a flexible soft-input soft-output (SISO) module to handle LDPC/Turbo decoding. We employ the trellis-based maximum a posteriori (MAP) algorithm as a bridge between LDPC and Turbo codes decoding. We view the LDPC code as a concatenation of n super-codes where each super-code has a simpler trellis structure so that the MAP algorithm can be easily applied to it. We propose a flexible functional unit (FFU) for MAP processing of LDPC and Turbo codes with a low hardware overhead (about 15% area and timing overhead). Based on the FFU, we propose an area-efficient flexible SISO decoder architecture to support LDPC/Turbo codes decoding. Multiple such SISO modules can be embedded into a parallel decoder for higher decoding throughput. As a case study, a flexible LDPC/Turbo decoder has been synthesized on a TSMC 90 nm CMOS technology with a core area of 3.2 mm². The decoder can support IEEE 802.16e LDPC codes, IEEE 802.11n LDPC codes, and 3GPP LTE Turbo codes. Running at 500 MHz clock frequency, the decoder can sustain up to 600 Mbps LDPC decoding or 450 Mbps Turbo decoding.     

光通信系统中LDPC码的构造及其编译码算法分析

针对低密度奇偶校验（LDPC）码的相关理论和LDPC码自身特性以及光通信系统具有低噪声、高信噪比的传输特点进行分析后,提出了光通信系统中LDPC码型的构造方法,这为光通信系统中LDPC码型的构造和仿真分析奠定了基础。并对光通信系统中LDPC码的编译码算法进行了深入分析与研究,得到一些有利于降低其编译码算法复杂度的重要结论,这有助于降低其编译码器的设计与实现复杂度。