A Shared Buffer Memory ATM Access Switch

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Fault tolerance in Clos–Knockout multicast ATM switch

In this paper, we propose a new architecture for multicast ATM switches with fault tolerant capability based on the Clos–Knockout switch. In the new architecture, each stage has one more redundant switch module. If one switch module is faulty, the redundant module would replace the faulty one. On the other hand, under the fault‐free condition, the redundant modules in the second and third stages will provide additional alternative internal paths, and hence improve the performance. The performance analysis shows that the cell loss probability is lower than the original architecture when all modules are fault free, and the reliability of the original architecture is improved. Copyright © 2002 John Wiley & Sons, Ltd.     

An experimental ATM switch for BISDN studies

This paper describes the architecture, functionality and performance of an experimental ATM switch being developed at the Telecom Australia Research Laboratories as part of its investigations into the broadband ISDN. The proposed switch architecture consists of parallel omega networks preceded by a Batcher bitonic sorting network. The switching fabric has no internal cell buffering. Cell buffering is provided only on the switch outputs for cells simultaneously contending for the same output port. The switch fabric and cell buffers include mechanisms for providing prioritized servicing of queued cells and prioritized discarding of cells based on priority fields contained within the cell header. Components of the switch are currently being implemented in 2 μm CMOS VLSI.     

A multistage ATM switch with interstage buffers

Asynchronous transfer mode (ATM) is the transport technique for the broadband ISDN recommended by CCITT (I.121). Many switches have been proposed to accommodate the ATM that requires fast packet switching capability.^1-8 The proposed switches for the broadband ISDN can be classified as being of input queueing or output queueing type. Those of the input queueing type have a throughput performance which is approximately 58 per cent that of the output queueing type. However, output queueing networks require larger amounts of hardware than input queueing networks. In this paper, we propose a new multistage switch with internal buffering that approaches a maximum throughput of 100 per cent as the buffering is increased. The switch is capable of broadcasting and self-routeing. It consists of two switching planes which consist of packet processors, 2 x 2 switching elements, distributors and buffers located between stages and in the output ports. The internal data rate of the proposed switch is the same as that of the arriving information stream. In this sense, the switch does not require speed-up. The switch has log₂ N stages that forward packets in a store-and-forward fashion, thus incurring a latency of log₂ N time periods. Performance analysis shows that the additional delay is small.     

矢量空间秘密共享-多重签名方案

本文把矢量空间秘密共享方案与多重签名方案结合起来,提出了一种新的签名方案,即矢量空间秘密共享-多重签名方案,并对该方案的安全性进行了分析.在该方案中,任何参与者的授权子集能容易地产生群签名,而参与者的非授权子集不可能产生有效的群签名,验证者可通过验证方法验证个体签名和群签名的合法性.该方案能保证一个参与者的授权子集的群签名不能被其他参与者子集所伪造,而且可以跟踪被怀疑的伪造者并将其曝光.该方案能抵御各种可能的攻击.     

ATM基本交换单元的研究与实现

文章提出并实现了一种共享缓存式ＡＴＭ基本交换单元的设计方案,该交换单元有６条输入输出线路,它由１０片大容量ＦＰＧＡ组成。通过简单的电路修改,用两片超大容量ＦＰＧＡ可以实现９×９或１８×１８共享缓存的ＡＴＭ基本交换单元。     

Queuing analysis of shared‐buffer ATM switches with grouped output channels

Shared buffering and channel grouping are powerful techniques with great benefits in terms of both performance and implementation. Shared‐buffer switches are known to have better performance and better utilization than input or output queued switches. With channel grouping, a cell is routed to a group of channels instead of a specific output channel. In this way, congestion due to output contention can be minimized and the switch performance can therefore be greatly improved. Although each technique is well known by itself in the traditional study of queuing systems, their combined use in ATM networks has not been much explored previously. In this paper, we develop an analytical model for a shared‐buffer ATM switch with grouped output channels. The model is then used to study the switch performance in terms of cell loss probability, cell delay and throughput. In particular, we study the impact of the channel grouping factor on the buffer requirements. Our results show that grouping the output channels in a shared‐buffer ATM switch leads to considerable savings in buffer space. Copyright © 2001 John Wiley & Sons, Ltd.     

实用化的ATM接入交换机

ＡＴＭ技术的核心是ＡＴＭ交换,ＡＴＭ交换的实现有多种方法,本文介绍一种实用的ＡＴＭ交换机,它具有结构简单,升级容易,配置灵活的特点,可广泛应用于宽带接入网中。     

A fast parallel-tree switch architecture for ATM networks

In this paper we present a novel fast packet switch architecture based on Banyan interconnection networks, called parallel-tree Banyan switch fabric (PTBSF). It consists of parallel Banyans (multiple outlets) arranged in a tree topology. The packets enter at the topmost Banyan. Internal conflicts are eliminated by using a conflict-free 3 × 4 switching element which distributes conflicting cells over different Banyans. Thus, cell loss may occur only at the lowest Banyan. Increasing the number of Banyans leads to a noticeable decrease in cell loss rate. The switch can be engineered to provide arbitrarily high throughput and low cell loss rate without the use of input buffering or cell pre-processing. The performance of the switch is evaluated analytically under uniform traffic load and by simulation, under a variety of asynchronous transfer mode (ATM) traffic loads. Compared to other proposed architectures, the switch exhibited stable and excellent performance with respect to cell loss and switching delay for all studied conditions as required by ATM traffic sources. The advantages of PTBSF are modularity, regularity, self-routing, low processing overhead, high throughput and robustness, under a variety of ATM traffic conditions. © 1998 John Wiley & Sons, Ltd.     

实用化的ATM交换机中组播通信的实现

ＡＴＭ是面向连接的技术,实现组播通信／广播通信是ＡＴＭ交换机优越于现有ＳＴＭ交换的重大体现,也是ＡＴＭ技术能否在现有网络基础上普遍应用的关键。在共享缓存型ＡＴＭ交换机冲,组播通信的实现是一项重点和难点,本文介绍我院研制的共享缓存型ＡＴＭ交换机中组播通信的设计与实现方法。     

FAULT-TOLERANT DESIGN OF BATCHER–BANYAN CLASS ATM SWITCHES

Many proposed packet switching systems for high-speed networks have employed the Batcher–banyan fabric due to its modular structure, self-routeing functionality, and distributed conflict-resolving mechanism. In this paper, we present a systematic fault-tolerant design for the Batcher–banyan class of switches. Our first concern is the development of an on-line error detection mechanism which is the prerequisite of any effective fault tolerant operation. Based on the technique developed by Davis, we propose a general fault-testing technique and verify it for a variety of unique-path self-routeing networks. Furthermore, we extend this method to Batcher sorting networks and construct a fault-tolerant Batcher sorter. Lastly, after contemplating the technique constraints and system performance, we deploy the above techniques into different levels of the Batcher–banyan networks and achieve a fault-tolerant version of the StarBurst switch, a member of the Batcher–banyan class of switches.     

Dynamic buffer management using per‐queue thresholds

Shared buffer switches consist of a memory pool completely shared among output ports of a switch. Shared buffer switches achieve low packet loss performance as buffer space is allocated in a flexible manner. However, this type of buffered switches suffers from high packet losses when the input traffic is imbalanced and bursty. Heavily loaded output ports dominate the usage of shared memory and lightly loaded ports cannot have access to these buffers. To regulate the lengths of very active queues and avoid performance degradations, threshold‐based dynamic buffer management policy, decay function threshold, is proposed in this paper. Decay function threshold is a per‐queue threshold scheme that uses a tailored threshold for each output port queue. This scheme suggests that buffer space occupied by an output port decays as the queue size of this port increases and/or empty buffer space decreases. Results have shown that decay function threshold policy is as good as well‐known dynamic thresholds scheme, and more robust when multicast traffic is used. The main advantage of using this policy is that besides best‐effort traffic it provides support to quality of service (QoS) traffic by using an integrated buffer management and scheduling framework. Copyright © 2006 John Wiley & Sons, Ltd.     

An approximate analysis of shared‐buffer channel‐grouped ATM switches under imbalanced traffic

Grouping output channels in a shared‐buffer ATM switch has shown to provide great saving in buffer space and better throughput under uniform traffic. However, uniform traffic does not represent a realistic view of traffic patterns in real systems. In this paper, we extend the queuing analysis of shared‐buffer channel‐grouped (SBCG) ATM switches under imbalanced traffic, as it better represent real‐life situations. The study focuses on the impact of the grouping factor and other key switch design parameters on the performance of such switches as compared to the unichannel allocation scheme in terms of cell loss probability, throughput, mean cell delay and buffer occupancy. Numerical results from both the analytical model and simulation are presented, and the accuracy of the analysis is presented. Copyright © 2005 John Wiley & Sons, Ltd.     

ATM交换机设计

本文提出一种宽带交换的新设计思想,它以异步传送模式为前提,能够保证各种宽带和窄带业务的综合交换。     

ATM业务量管理及其对ATM交换机设计的影响

ＡＴＭ网络允诺为各种通信业务在同一个通信网络中提供满足各自服务质量的要求的服务。为此，ＡＴＭ网络体系应能提供业务量管理（ｕｔａｆｆｉｃ ｍａｎａｇｅｍｅｎｔ）功能以支持网络业务千差万别的服务质量要求。本文首先阐述了ＡＴＭ论坛（ＡＴＭ Ｆｏｒｍ）中所定义的ＡＴＭ业务种类，它们各自的服务质量要求，以及为保证服务质量所应采用的管理策略。ＡＴＭ交换机是网络中的关键部件，其不同的设计思想对网络中不同业务服务     

Waiting time distribution of an ATM switch routing two‐class traffic with two service rates

In this article we analyse the waiting time of an arbitrary packet in an output buffered space division switch routing two‐class traffic, e.g. in a multimedia environment. For the purpose of the analysis, the switch is modelled as a priority, discrete time, batch arrival queueing system, with a single server having two service rates. The results of the analysis are verified in various ways, including obtaining previously published results as special cases. The fundamental contribution of this article is the assumption of two service rates, one for each class, rather than the typical assumption of one service rate for both classes. This assumption is useful in that it accounts for the different quality of service (QoS) needs of each class. Another contribution is the introduction of a new approach to analyse the waiting time—an approach not based on the system occupancy as is typical in the published literature. Copyright © 2003 John Wiley & Sons, Ltd.     

ATM中突发业务的缓存性能分析

主要讨论突发业务情况下的ATM缓存的排队性能.首先采用状态转移概率进行模型分析,然后再给出信元丢失率和信元延时的分布.     

SDH光纤网和ATM交换机简述

简述Ｂ－ＩＳＤＮ的两大基础：ＳＤＨ光纤网和ＡＴＭ交换机的基本知识，前半部分是讲ＳＤＨ光纤网的由来、网络拓朴、信息负载与包络及双环结构与设备。后半部分是讲ＡＴＭ信元交换、ＡＴＭ适配层、信息业务类型。     

ATM实时网络中的容错方法

分布式网络由于采用冗余资源等方式而屏蔽系统故障已得到广泛应用。本文提出了一种解决ＡＴＭ分布式实时网络系统时钟同步的方案,它可以在容错下解决系统时钟同步问题。     

Pushout with virtual thresholds buffer management scheme in a shared buffer ATM switch

In this paper we investigate the performance metrics of buffer management schemes. In general, the selective pushout (SP) scheme can support very low loss probability of the high‐priority cells, but it may cause unfairness of buffer allocation among different output queues and high overall cell loss probability. In order to fit the dynamic required performance metrics of ATM switches, a novel buffer management scheme called pushout with virtual thresholds (PVT) is proposed. In the PVT scheme, each output queue is guaranteed to increase in length until its virtual threshold (VT). Simulation results show the PVT can dynamically achieve the fairness and low overall cell loss probability or very low loss probability of the high priority cells by adequately adjusting the VT. Specially, when the VT = 0, the PVT control can be viewed as the SP control. Copyright © 2003 John Wiley & Sons, Ltd.