FDSTDL: Low-power technique for FinFET domino circuits

Major issues in designing low-power high-speed VLSI circuits are propagation delay, power consumption, and noise tolerance. This paper describes fin field-effect transistor (FinFET) technology for the design of low-power VLSI circuits. FinFET uses two gates (front and back) in place of a single gate as in complementary metal-oxide–semiconductor (CMOS) technology for better control of the channel. A new technique foot driven stack transistor domino logic (FDSTDL) is proposed for designing domino logic circuits in order to reduce leakage power and propagation delay. In this paper, 2-, 4-, 8-, and 16-input domino OR gates are designed and simulated using existing and proposed techniques in CMOS and FinFET technology. Simulation is done on the 32 nm predictive technology model (PTM) node using HSPICE on a direct current (DC) supply voltage of 0.9 V. The proposed circuit is simulated in two modes of FinFET, short gate (SG) mode, and low power (LP) mode. The proposed technique shows maximum power reduction of 43.45% in SG mode in comparison with conditional stacked keeper domino logic (CSK-DL) technique and maximum delay reduction of 38.66% in LP mode in comparison with coarse-mesh finite difference (CMFD) technique at a frequency of 200 MHz.     

A global delay model for domino cmos circuits with application to transistor sizing

Domino CMOS circuits have played important roles in the design of high-speed VLSI chips such as 32-bit microprocessors and their family chips. Many researchers have worked on the characterization of the delay time and optimal design of domino CMOS circuits using circuit simulators as the main CAD tools. This paper presents a global analytical delay model for an important class of domino CMOS circuits wherein a multitude of n-channel transistors form a series connection. the new model is shown to predict the delay time from the precharging clock edge to the 0.5 V_DD output level with less than 10% error as compared to that from SPICE simulation over the entire design space. the delay model has been applied efficiently to the design automation of domino CMOS circuits modules.     

Transistor size optimization in digital circuits using ant colony optimization for continuous domain

In this paper, ant colony optimization (ACO) algorithm is presented, as a tool to find transistor sizes in digital circuits. Performance of ACO has been tested on four digital circuits, of different complexity, to find optimum balance between power and delay of circuits. Optimization problem has been set up by first, formulating an objective function, to be minimized, for each circuit and then finding the values of variables of circuits, using optimization algorithm. For the purpose of examining the results, circuits are optimized using genetic algorithm (GA) also. Results show that, ACO performs better than GA, for all the four circuits, in finding optimized transistor sizes. Copyright © 2012 John Wiley & Sons, Ltd.     

A three-terminal piecewise-linear modelling approach to dc analysis of transistor circuits

The simulation of electronic circuits by computer has become an important part of present-day circuit analysis and design, especially in the area of integrated circuit design. One of the goals in computer simulation of integrated circuits is to have a program ‘package’ for which the input consists of chip fabrication data (mask dimensions, impurity profiles, material data such as carrier lifetimes) and the output displays the complete circuit response. This requires both an efficient modelling approach and a fast circuit analysis method. In this paper a simulation method is described which generates dc responses (in the form of operating points or transfer characteristics) of transistor circuits directly from physical parameter data. The basis of the method is a two-dimensional piecewise-linear approach to the dc modelling of bipolar transistors. The model is directly used in a piecewise-linear circuit analysis program to simulate the dc response of a given circuit.     

The average capacitor current method for delay calculation in MOS circuits

The transient response of metal-oxide-semiconductor (MOS) gates is a topic covered in most textbooks on digital integrated circuits and very-large-scale-integration (VLSI) design. One method often used to calculate first-order estimates of gate delays is the average capacitor current method. Using this method, the delay is calculated assuming that the capacitor current is constant and equal to the average of the capacitor current values at the limits of the time interval of interest. In this paper, this method is discussed and compared with other methods of delay calculation using integration and curve-fitting techniques familiar to electrical and computer engineering students. Since the computation of the capacitor current is relatively complicated because it requires the calculation of the MOS transistor currents, for propagation delay calculation there is no benefit in calculating the capacitor current twice. A single current calculation, corresponding to the familiar midpoint integration method, is sufficient to get the same or better accuracy as that of the average capacitor current method. The two-point Gauss quadrature formula is shown to provide excellent results with two capacitor current evaluations.     

Device circuit co‐design to reduce gate leakage current in VLSI logic circuits in nano regime

In this paper, nanoscale metal–oxide–semiconductor field‐effect transistor (MOSFET) device circuit co‐design is presented with an aim to reduce the gate leakage curren t in VLSI logic circuits. Firstly, gate leakage current is modeled through high‐k spacer underlap MOSFET (HSU MOSFET). In this HSU MOSFET, inversion layer is induced in underlap region by the gate fringing field through high‐k dielectric (high‐k) spacer, and this inversion layer in the underlap region acts as extended source/drain region. The analytical model results are compared with the two‐dimensional Sentaurus device simulation. Good agreement is obtained between the model and Sentaurus simulation. It is observed that modified HSU MOSFET had improved off current, subthreshold slope, and drain‐induced barrier lowering characteristics. Further, modified HSU MOSFET is also analyzed for gate leakage in generic logic circuits. Copyright © 2015 John Wiley & Sons, Ltd.     

A fast method for process reliability analysis of CNFET-based digital integrated circuits

Due to aggressive technology scaling in electronic of digital integrated circuits, the circuit reliability is becoming an ever-increasing challenge. In nanoscale technologies, the physical and chemical properties of materials are fundamentally different compared to the larger scales. Therefore, it is necessary to revise the conventional reliability assessment techniques considering their applicability to nanoscale integrated circuits. This paper presents a method for evaluating the circuit reliability at the transistor level of abstraction considering the physical characteristics of the transistors. The proposed method considers various parameters, including the probability of different types of a transistor failure, the topology of logic gates and the logical values of the applied input vectors. Experimental results show that the proposed approach provides accurate transistor-level circuit reliability evaluations (with < 4% inaccuracy) as compared to a reference method based on Monte Carlo HSPICE simulations in addition to more than 800 times speedup. Moreover, to show the comprehensiveness and extensibility of the proposed reliability analysis method for the technologies beyond conventional MOSFETs, it is applied to carbon nanotube field-effect transistor (CNFET) technology as one of the most promising candidates for future CMOS circuits. The obtained results re-acknowledge that in order to achieve a more accurate reliability estimation approach for CNFET circuits, it is necessary to consider the open and short failure probability values individually instead of considering them in the form of a single transistor failure probability.     

An accurate reference-generating circuit for successive approximation current mode A/D converters

As pressures increase on VLSI designers to use a lower supply voltage of 3.3 V rather than the present 5 V, current mode signal-processing techniques will surely become increasingly important and attractive. This paper presents the design of a reference-generating (RG) circuit which employs a current mode divide-by-two circuit. Current dividers are usually implemented by using resistor networks or weighted transistors. the division accuracy of such solutions is limited by resistor or transistor mismatch. In this study the proposed divide-by-two circuit does not rely on well-matched components and high-gain op amps to achieve high accuracy. This paper also addresses the relationship among the operation and accuracy of the division process, the transistor mismatch and the resolution of a converter which employs the RG circuit. the proposed RG circuit can be implemented not only for medium-speed successive approximation current mode A/D converters but also for A/D converter arrays achieving a high conversion rate.     

A modified macro model approach for SPICE based simulation of single electron transistor

A new macro model of single electron transistor (SET) for SPICE based simulation of SET circuits is proposed. Two voltage controlled current sources and some scaling factors are incorporated in the existing model to derive our model. The V–I characteristics of the proposed SET is promising enough to be used as the basic element for designing circuits based on SETs. A comparison with the previous models establishes the fact that our model efficiently removes the drawbacks of the existing models. Our model also agrees well with the results obtained from popular SIMON simulator. To verify the accuracy, we have designed a SET inverter cell and investigated its characteristics. The work includes the effect of the parameters on the noise margin and voltage transfer characteristics of the inverter circuit. Further, to verify the applicability, a multi peak negative differential resistance circuit based on the proposed model is designed and simulated.     

A tabular source approach to modelling and simulating device and circuit noise in the time domain

Simulation of device and circuit noise at low frequencies is often carried out as part of a small‐signal ac analysis. Moreover, circuit simulators with rf analysis capabilities usually specify circuit performance in terms of S parameters and model high‐frequency noise in terms of noise waves and correlation matrices. It is also unusual to find circuit simulators that extend noise simulation to the time domain. This is particularly true for software packages developed from SPICE 2g6 or 3f5. This paper introduces a simple tabular noise source technique, which adds time‐domain noise to semiconductor device models and integrated circuit macromodels. The proposed technique is suitable for use with any general purpose circuit simulator. To demonstrate the power of the suggested approach the text describes time‐domain noise extensions to the SPICE diode, BJT, JFET, MOSFET and MESFET models. These noise extensions have been implemented and tested with the ‘Quite universal circuit simulator’ (Qucs). Copyright © 2011 John Wiley & Sons, Ltd.     

Time domain sensitivity of high-speed VLSI interconnects

An adjoint method based on the asymptotic wave-form evaluation (AWE) technique is described for the time domain sensitivity analysis of VLSI interconnect networks that contain linear lumped and distributed elements. the network sensitivity, which is approximated by a set of poles and residues sensitivities, can be evaluated efficiently with respect to all network components and interconnect parameters. Owing to the recursive relationship between the time moments of distributed networks, the conventional adjoint approach could not be applied directly. Instead, an alternative approach is presented which solves this problem by introducting the concept of adjoint moments for networks with distributed elements. Examples and comparisons with the sensitivity determined by perturbation are presented. the proposed technique is useful for the identification of critical circuit elements and the performance optimization of high-speed VLSI designs.     

Competitive evolutionary algorithms for building performance database of a microwave transistor

In this work, the simultaneous trade‐off relations among the noise figure F, gain G_T, input V_in, and output V_out VSWRs of a microwave transistor operated at a certain (V_DS, I_DS, f) condition are obtained fast and as accurate as the corresponding analytical results using multiobjective optimization process without any need for expertise on the microwave device, circuit, and noise. Three powerful evolutionary algorithms, cuckoo search, firefly, and differential evolution, are implemented comparatively as a study case to obtain the trade‐off relations of a typical low‐noise amplifier transistor NE3511S02 for its operation between 9 and 17 GHz at V_DS = 2 V and I_DS = 10 mA. Finally, differential evolution is found as the most successful algorithm to demonstrate the typical trade‐off relations of NE3511S02. It can be concluded that these trade‐off relations being obtained by using a signal and noise model of the transistor enable performance database covering all the (F ≥ F_min, G_T, V_in ≥ 1, V_out ≥ 1) quadruples with their (Z_S, Z_L) termination pairs using solely an evolutionary optimization process. Thus, a small signal transistor can be identified by its performance database to be used in the design optimization of high‐performance low‐noise amplifiers with the full device capacity.     

基于布尔可满足性的层次化通路时延故障测试

针对现代VLSI电路趋向于层次化的设计,本文提出了基于布尔可满足性的层次化通路时延故障测试方法,采用面向模块级的增量布尔可满足性合取范式的提取,从高到低层次化实现了关键通路的判别及子式生成.利用电路的时延测试条件蕴涵并转化为相应的约束子句,有利于将冲突尽早提前,以减少搜索空间.通过将已有的判别模块储存起来,作为学习子句,避免重复判别,极大的加快了子式的提取且降低了求解的规模和难度.仿真结果表明本文方案具有测试时间短、效率高,特别适合于具有模块化、规则化结构的层次化设计电路.     

Efficient output waveform evaluation of a CMOS inverter based on short‐circuit current prediction

A novel approach for obtaining the output waveform, the propagation delay and the short‐circuit power dissipation of a CMOS inverter is introduced. The output voltage is calculated by solving the circuit differential equation only for the conducting transistor while the effect of the short‐circuit current is considered as an additional charge, which has to be discharged through the conducting transistor causing a shift to the output waveform. The short‐circuit current as well as the corresponding discharging current are accurately predicted as functions of the required time shift of the output waveform. A program has been developed that implements the proposed method and the results prove that a significant speed improvement can be gained with a minor penalty in accuracy. Copyright © 2002 John Wiley & Sons, Ltd.     

基于RLC模型的集成电路互连线串扰估计

本文提出了一个新的基于RLC模型的高速集成电路互连线串扰峰值估计公式,在考虑了电感效应的基础上建立了RLC电路模型,对CMOS电路器件作了线性假设,推导出了当侵略线输入单位斜升信号时的互连串扰时域表达式。计算机仿真结果表明,该公式的结果相对于HSPICE仿真的误差绝对值小于10%,可被应用于集成电路版图综合的布局规划模型中,能够在高速、高密度VLSI的设计阶段预测信号性能。     

Analysing the operation of the basic pass transistor structure

Pass transistor logic has become important for the design of low‐power high‐performance digital circuits due to the smaller node capacitances and reduced transistors count it offers. However, the acceptance and application of this logic depends on the availability of supporting automation tools, e.g. timing simulators, that can accurately analyse the performance of large circuits at a speed, significantly faster than that of SPICE based tools. In this paper, a simple and robust modelling technique for the basic pass transistor structure is presented, which offers the possibility of fast timing analysis for circuits that employ pass transistors as controlled switches. The proposed methodology takes advantage of the physical mechanisms in the pass transistor operation. The obtained accuracy compared to SPICE simulation results is sufficient for a wide range of input and circuit parameters. Copyright © 2006 John Wiley & Sons, Ltd.     

Noise‐tolerant dynamic CMOS circuits design by using true single‐phase clock latching technique

In this paper, a true‐single‐phase clock latching based noise‐tolerant (TSPCL‐NT) design for dynamic CMOS circuits is proposed. A TSPCL‐NT dynamic circuit can isolate and filter noise before the noise enters into the dynamic circuit. Therefore, it cannot only greatly enhance the noise tolerance of dynamic circuits but also release the signal contention between the feedback keeper and the pull‐down network effectively. As a result, noise tolerance of dynamic circuits can be improved with lower sacrifice in power consumption and operating speed. In the 16‐bit TSPCL‐NT Manchester adder, the average noise threshold energy can be enhanced by 3.41 times. In the meanwhile, the power‐delay product can be improved by 5.92% as compared with the state‐of‐the art 16‐bit XOR‐NT Manchester adder design under TSMC 90 nm CMOS process. Copyright © 2014 John Wiley & Sons, Ltd.     

Noise‐immune dual‐rail dynamic circuit for wide fan‐in gates in asynchronous designs

Dual‐rail dynamic logic circuits can provide inverting and noninverting outputs, especially for asynchronous designs, to implement complicated gates at the cost of approximately doubling the area and power consumption. In this paper, a new dual‐rail dynamic circuit is proposed which has lower die area consumption and higher noise immunity without dramatic speed degradation for even wide fan‐in gates for asynchronous circuits. The main idea in the proposed circuit is that voltage due to the current of the pulldown network (PDN) is compared with the reference voltage to provide two complementary outputs. The reference voltage almost corresponds to the leakage current of the PDN with all transistors being off. The proposed circuit is compared with conventional dual‐rail circuits such as differential domino logic and differential cross‐coupled domino logic. Simulation results for 32‐bit‐wide OR gates designed using high‐performance 16‐nm predictive technology model demonstrate significant performance advantages such as 66% power reduction and at least 2.86× noise‐immunity improvement at the same delay compared to the differential domino circuits. © 2012 Institute of Electrical Engineers of Japan. Published by John Wiley & Sons, Inc.     

基于分布式RLC耦合模型的互连线尺寸优化

随着晶体管制造尺寸的越来越小,集成密度的越来越高,耦合电容与电感之间所引起的相邻互连线间的干扰噪声成倍增加,对高速高密度纳米级超大规模集成电路造成极大危害。基于分布式RLC耦合互连模型详细的模拟了金属互连线的延迟及串扰,对32nm CMOS工艺下的不同互连线尺寸进行模拟,仿真给出了在不同的厚度下延迟与串扰之间的关系,优化互连线的几何尺寸能有效的减小互连线的串扰噪声和延迟。结果表明:互连线宽W同互连线节距P之比在W/P=0.6时是获得最小时间延迟的最佳尺寸。