A hybrid time-domain technique for simulation of high-density integrated optical circuits

This paper presents a new simulation method for modeling and simulation of high-density integrated optical circuits based on high index contrast (HIC) waveguides with complex topology. The method combines the time-domain reflective beam propagation method (TD-RBPM) and the slow-wave finite-difference time-domain method and is hence referred to as the time-domain hybrid BPM (TD-HBPM). It is capable of handling arbitrary optical integrated circuits with perpendicularly located input and output ports. The application to the two HIC optical circuits shows the accuracy and efficiency of this method.     

Applications of PSPICE simulation software to the study ofoptoelectronic integrated circuits and devices

Software models for Si and GaAs pin photodetectors are described, for use in the simulation of optoelectronic integrated circuits (OEICs). These preliminary models, which include the effects of dark current and lumped internal impedance, are completely integrable with PSPICE software, and may be used to study the operating characteristics of independent devices and cascaded components in complex OEICs. Parametric device dependence on applied bias, doping density, and wavelength of incident light are also established. The simulation of more advanced OEICs can be implemented with the subsequent modeling of other passive and active components, including waveguide modulators and light emitting sources. The use of PSPICE simulation software in the study of optoelectronic devices and circuits described should find wide application in upper division core or elective optical electronic courses and laboratories     

Fast alternating direction implicit method for efficient transient thermal simulation of integrated circuits

This paper presents fast alternating direction implicit (FADI) method for efficient transient thermal simulation of integrated circuits. The FADI method is formulated from Peaceman–Rachford's ADI and Douglas–Gunn's ADI methods. The update procedure of the proposed method has basic implicit form that features derivative‐free right‐hand side and hence, better efficiency and conciseness. Subsequently, through the basic implicit form of FADI method, the relationship between classical Peaceman–Rachford's and Douglas–Gunn's ADI methods can be clarified and elucidated in detail. A unified boundary condition that can cater to common kinds of boundary conditions in thermal simulation is also introduced. To further accelerate FADI method, the graphics processing unit is also utilized through Compute Unified Device Architecture implementation. It is shown that high efficiency gain can be achieved using the proposed FADI method through large time step size and data parallelism, while maintaining stability and good accuracy. As numerical illustration, an integrated circuit structure with microchannel cooling is demonstrated. Numerical results further ascertain the cooling effect of the microchannels. Copyright © 2015 John Wiley & Sons, Ltd.     

Large-scale photonic integrated circuits

100-Gb/s dense wavelength division multiplexed (DWDM) transmitter and receiver photonic integrated circuits (PICs) are demonstrated. The transmitter is realized through the integration of over 50 discrete functions onto a single monolithic InP chip. The resultant DWDM PICs are capable of simultaneously transmitting and receiving ten wavelengths at 10 Gb/s on a DWDM wavelength grid. Optical system performance results across a representative DWDM long-haul link are presented for a next-generation optical transport system using these large-scale PICs. The large-scale PIC enables significant reductions in cost, packaging complexity, size, fiber coupling, and power consumption.     

Thermal issues in next-generation integrated circuits

The drive for higher performance has led to greater integration and higher clock frequency of microprocessor chips. This translates into higher heat dissipation and, therefore, effective cooling of electronic chips is becoming increasingly important for their reliable performance. We systematically explore the limits for heat removal from a model chip in various configurations. First, the heat removal from a bare chip by pure heat conduction and convection is studied to establish the theoretical limit of heat removal from a bare die bound by an infinite medium. This is followed by an analysis of heat removal from a packaged chip by evaluating the thermal resistance due to individual packaging elements. The analysis results allow us to identify the bottlenecks in the thermal performance of current generation packages, and to motivate lowering of thermal resistance through the board-side for efficient heat removal to meet ever increasing reliability and performance requirements.     

Development of an electrothermal simulation tool for integrated circuits: Application to a two-transistor circuit

In this paper a methodology for performing electrothermal analyses on integrated circuits is introduced. Using the relaxation method, standard electrical and thermal simulators, which are often used in the design process, are coupled through an efficient interface program. The simulator is capable of performing steady-state and transient analysis at device and chip levels. A variable-time-step technique has been implemented to reduce the computational time for a given set of computational resources. The simulator has been validated on different structures such as the bipolar junction transistor to predict the temperature distribution and the device performance in an amplifier circuit and an integrated current-mirror circuit. The simulation results are compared to experimental results to verify the performance of the electrothermal simulator and the accuracy of the thermal model. Simulation results demonstrate that the approach is suitable to model the thermal effects of integrated circuits in a more time-efficient, accurate and user-friendly fashion.     

Analysis of unbounded and bounded circuits considering finite substrate extent and inhomogeneous dielectric layer

A generalized method of lines algorithm is presented for characterizing unbounded and bounded circuits. Finite substrate extent and inhomogeneous dielectric layers are rigorously considered in this field‐based model. Radiating properties of unbounded regular and irregular microstrip patch resonators and arrays are studied with emphasis on effects of mutual coupling and finite dielectric extent on complex resonant frequencies. In addition, unbounded loss effects for microstrip open‐end and 90° angular bend deposited on finite substrate as well as chip‐to‐chip discontinuities are also investigated. Our developed algorithm incorporates an absorbing boundary condition using the Padé approximation to simulate any potential radiation and leakage losses for resonator structures while an improved lossy absorbing boundary condition (LABC) that can handle both propagating and evanescent waves is used to determine the unbounded effects for waveguiding structures. Results indicate interesting properties of the finite extent of dielectric substrate on resonance and radiation characteristics, and also on unbounded radiation and leakage losses. Copyright © 2000 John Wiley & Sons, Ltd.     

Circuit-level modeling of soft errors in integrated circuits

This paper describes the steps necessary to develop a soft-error methodology that can be used at the circuit-simulation level for accurate nominal soft-error prediction. It addresses the role of device simulations, statistical simulation, analytical soft-error rate (SER) model development, and SER-model calibration. The resulting approach is easily automated and generic enough to be applied to any type of circuit for estimation of the nominal SER.     

基于投影积分的气-电耦合园区综合能源系统动态仿真方法

在充分考虑电力、燃气系统及其相互转化特性的基础上,建立了气-电耦合园区综合能源系统动态仿真模型,并根据动态过程的时间尺度对刚性系统进行划分;在此基础上,基于投影积分理论,提出一种适用于气-电耦合园区综合能源系统的高效率动态仿真方法,采用内部积分器以小步长的显式和隐式欧拉法交替求解来精细刻画快动态过程,采用外部积分器以可变大步长二阶牛顿插值高效求解慢动态过程,且在计算过程中能够有效计及故障扰动等事件的影响;对算法的数值精度进行分析。基于典型算例的算法测试表明,所提方法能够有效实现多场景下的气-电耦合系统快速稳定求解,在保证精度的前提下有效提升仿真效率。     

Optoelectronic-VLSI: photonics integrated with VLSI circuits

Optoelectronic-VLSI (OE-VLSI) technology represents the intimate integration of photonic devices with silicon VLSI electronics. We review the motivations and status of emerging OE-VLSI technologies and examine the performance of OE-VLSI technology versus conventional wire-bonded OE packaging. The results suggest that OE-VLSI integration offers substantial power and speed improvements even when relatively small numbers of photonic devices are driven with commodity complementary metal-oxide-semiconductor logic technologies     

用于大规模集成电路的多级布局规划设计

本文提出了一种适用于处理大规模集成电路设计的布图规划问题的V型多级不可分割固定边框布图规划算法。该算法以追求电路设计在短耗时前提下的最短布线为目的,同时满足电路原本的面积边框限制。通过计算机仿真,实验结果体现了所提出多级布局规划算法的有效性。     

Photonic integrated circuits fabricated using ion implantation

Intermixing the wells and barriers of quantum-well (QW) laser heterostructures generally results in an increase in the bandgap energy and is accompanied by changes in the refractive index. A technique, based on ion implantation-induced QW intermixing, has been developed to enhance the quantum-well intermixing (QWI) rate in selected areas of a wafer. Such processes offer the prospect of a powerful and simple fabrication route for the integration of discrete optoelectronic devices and for forming photonic integrated circuits     

Hybrid integration of VCSEL's to CMOS integrated circuits

Three hybrid integration techniques for bonding vertical-cavity surface-emitting lasers (VCSELs) to CMOS integrated circuit chips have been developed and compared in order to determine the optimum method of fabricating VCSEL based smart pixels for optical interconnects and free-space optical processing. Each of the three bonding techniques used different ways of attaching the VCSEL to the integrated circuit and making electrical contacts to the n- and p-mirrors. All three techniques remove the substrate from the VCSEL wafer leaving an array of individual VCSELs bonded to individual pixels. The 4×4 and/or 8×8 arrays of bonded VCSELs produced electrical and optical characteristics typical of unbonded VCSELs. Threshold voltages down to 1.5 V and dynamic resistance as low as 30 Ω were measured, indicating good electrical contact was obtained. Optical power as high as ~10 mW for a VCSEL with a 20-μm aperture and 0.7 mW with a 6-μm aperture were observed. The VCSELs were operated at 200 Mb/s (our equipment limit) with the rise and fall times of the optical output <1 nS     

Interpolation and reinitialization in time-domain simulation of power electronic circuits

This paper presents a new interpolation–reinitialization method for transient simulations in both forced commutation and natural commutation conditions occurring in power electronic circuits. Recently published methods in this field are also discussed. The objectives are to provide generalization and to increase the precision level of numerical methods used for the computation of transients due to switching events in Electromagnetic Transients Program (EMTP) type applications.     

Optimization of large change tolerances of linear integrated circuits

Optimization of element tolerances is a very important but also time consuming part of integrated circuit design. In this paper an algorithm is presented for the worst case optimal assignment of large change tolerances, in which a significant simplification of the problem is obtained for a class of linear circuits. This is due to taking advantage of the bilinear dependence of the network functions on element values and to some simplifications assumed. The minimal cost of the circuit is the objective function.