A hybrid time-domain technique for simulation of high-density integrated optical circuits

This paper presents a new simulation method for modeling and simulation of high-density integrated optical circuits based on high index contrast (HIC) waveguides with complex topology. The method combines the time-domain reflective beam propagation method (TD-RBPM) and the slow-wave finite-difference time-domain method and is hence referred to as the time-domain hybrid BPM (TD-HBPM). It is capable of handling arbitrary optical integrated circuits with perpendicularly located input and output ports. The application to the two HIC optical circuits shows the accuracy and efficiency of this method.     

Applications of PSPICE simulation software to the study ofoptoelectronic integrated circuits and devices

Software models for Si and GaAs pin photodetectors are described, for use in the simulation of optoelectronic integrated circuits (OEICs). These preliminary models, which include the effects of dark current and lumped internal impedance, are completely integrable with PSPICE software, and may be used to study the operating characteristics of independent devices and cascaded components in complex OEICs. Parametric device dependence on applied bias, doping density, and wavelength of incident light are also established. The simulation of more advanced OEICs can be implemented with the subsequent modeling of other passive and active components, including waveguide modulators and light emitting sources. The use of PSPICE simulation software in the study of optoelectronic devices and circuits described should find wide application in upper division core or elective optical electronic courses and laboratories     

Large-scale photonic integrated circuits

100-Gb/s dense wavelength division multiplexed (DWDM) transmitter and receiver photonic integrated circuits (PICs) are demonstrated. The transmitter is realized through the integration of over 50 discrete functions onto a single monolithic InP chip. The resultant DWDM PICs are capable of simultaneously transmitting and receiving ten wavelengths at 10 Gb/s on a DWDM wavelength grid. Optical system performance results across a representative DWDM long-haul link are presented for a next-generation optical transport system using these large-scale PICs. The large-scale PIC enables significant reductions in cost, packaging complexity, size, fiber coupling, and power consumption.     

Thermal issues in next-generation integrated circuits

The drive for higher performance has led to greater integration and higher clock frequency of microprocessor chips. This translates into higher heat dissipation and, therefore, effective cooling of electronic chips is becoming increasingly important for their reliable performance. We systematically explore the limits for heat removal from a model chip in various configurations. First, the heat removal from a bare chip by pure heat conduction and convection is studied to establish the theoretical limit of heat removal from a bare die bound by an infinite medium. This is followed by an analysis of heat removal from a packaged chip by evaluating the thermal resistance due to individual packaging elements. The analysis results allow us to identify the bottlenecks in the thermal performance of current generation packages, and to motivate lowering of thermal resistance through the board-side for efficient heat removal to meet ever increasing reliability and performance requirements.     

Development of an electrothermal simulation tool for integrated circuits: Application to a two-transistor circuit

In this paper a methodology for performing electrothermal analyses on integrated circuits is introduced. Using the relaxation method, standard electrical and thermal simulators, which are often used in the design process, are coupled through an efficient interface program. The simulator is capable of performing steady-state and transient analysis at device and chip levels. A variable-time-step technique has been implemented to reduce the computational time for a given set of computational resources. The simulator has been validated on different structures such as the bipolar junction transistor to predict the temperature distribution and the device performance in an amplifier circuit and an integrated current-mirror circuit. The simulation results are compared to experimental results to verify the performance of the electrothermal simulator and the accuracy of the thermal model. Simulation results demonstrate that the approach is suitable to model the thermal effects of integrated circuits in a more time-efficient, accurate and user-friendly fashion.     

Circuit-level modeling of soft errors in integrated circuits

This paper describes the steps necessary to develop a soft-error methodology that can be used at the circuit-simulation level for accurate nominal soft-error prediction. It addresses the role of device simulations, statistical simulation, analytical soft-error rate (SER) model development, and SER-model calibration. The resulting approach is easily automated and generic enough to be applied to any type of circuit for estimation of the nominal SER.     

Photonic integrated circuits fabricated using ion implantation

Intermixing the wells and barriers of quantum-well (QW) laser heterostructures generally results in an increase in the bandgap energy and is accompanied by changes in the refractive index. A technique, based on ion implantation-induced QW intermixing, has been developed to enhance the quantum-well intermixing (QWI) rate in selected areas of a wafer. Such processes offer the prospect of a powerful and simple fabrication route for the integration of discrete optoelectronic devices and for forming photonic integrated circuits     

用于大规模集成电路的多级布局规划设计

本文提出了一种适用于处理大规模集成电路设计的布图规划问题的V型多级不可分割固定边框布图规划算法。该算法以追求电路设计在短耗时前提下的最短布线为目的,同时满足电路原本的面积边框限制。通过计算机仿真,实验结果体现了所提出多级布局规划算法的有效性。     

Optoelectronic-VLSI: photonics integrated with VLSI circuits

Optoelectronic-VLSI (OE-VLSI) technology represents the intimate integration of photonic devices with silicon VLSI electronics. We review the motivations and status of emerging OE-VLSI technologies and examine the performance of OE-VLSI technology versus conventional wire-bonded OE packaging. The results suggest that OE-VLSI integration offers substantial power and speed improvements even when relatively small numbers of photonic devices are driven with commodity complementary metal-oxide-semiconductor logic technologies     

Hybrid integration of VCSEL's to CMOS integrated circuits

Three hybrid integration techniques for bonding vertical-cavity surface-emitting lasers (VCSELs) to CMOS integrated circuit chips have been developed and compared in order to determine the optimum method of fabricating VCSEL based smart pixels for optical interconnects and free-space optical processing. Each of the three bonding techniques used different ways of attaching the VCSEL to the integrated circuit and making electrical contacts to the n- and p-mirrors. All three techniques remove the substrate from the VCSEL wafer leaving an array of individual VCSELs bonded to individual pixels. The 4×4 and/or 8×8 arrays of bonded VCSELs produced electrical and optical characteristics typical of unbonded VCSELs. Threshold voltages down to 1.5 V and dynamic resistance as low as 30 Ω were measured, indicating good electrical contact was obtained. Optical power as high as ~10 mW for a VCSEL with a 20-μm aperture and 0.7 mW with a 6-μm aperture were observed. The VCSELs were operated at 200 Mb/s (our equipment limit) with the rise and fall times of the optical output <1 nS     

A quantum-well-intermixing process for wavelength-agile photonic integrated circuits

Wavelength-agile photonic integrated circuits are fabricated using a one-step ion implantation quantum-well intermixing process. In this paper, we discuss, the issues in processing optimized widely tunable multisection lasers using this technique and present the results achieved using this process. This quantum-well intermixing process is general in its application and can be used to monolithically integrate a wide variety of optoelectronic components with widely tunable lasers.     

Reduction of electromagnetic field coupling to microwave microstrip circuits

The signals induced by an external electromagnetic field along a microstrip line on a multilayered dielectric substrate were studied. The main target of the work is not to introduce a new technique of study but to search for suitable combinations of the structural and geometrical characteristics of the printed geometry whereby the electromagnetic interference of the external field to the circuit would be reduced. This reduction is desirable in all modern applications. The results derived prove that this object can be achieved at high frequencies and when the substrate is multilayered.     

Propagation of picosecond pulses in superconducting microstrip interconnections on integrated circuits

Studies on the propagation of picosecond pulses in coupled microstrip line interconnections on silicon integrated circuit substrates are presented. The effects of conductor and dielectric losses in the transmission line on the distortion, delay and attenuation of picosecond pulses are studied in detail. A direct comparison is made with the propagation characteristics of interconnects using ordinary metals and high-temperature superconductors such as YBa₂Cu₃O₇. The results generally show the advantages of using high-temperature superconductor tracks on low-loss integrated circuit substrates such as GaAs. However, even in this case, geometrical dispersion can cause distortion on the pulses and it is therefore an important factor to be considered.     

数字电路封装的串扰测试方法研究

梳理了数字电路封装串扰测试方法的发展历史,总结了串扰的影响因素。基于对业界串扰测试方法的分析,比较了各种方法间的区别和优缺点,分析了美军标MIL-STD-883K中串扰测试方法很少修订却长期存在的原因。明确了美军标及其他串扰测试方法的适用范围,提出了我国相应标准制修订方向的建议。测试结果表明,标准中的现有方法在评估串扰对整体电路影响方面手段有欠缺,需要结合电磁仿真对串扰影响做出整体评估,并利用实际测试对仿真结果进行校准,从而提高模拟的准确度,此方法可以在我国相应标准的制修订中加以采用。