CAN总线位定时和同步的研究与设计

在CAN规范中,位定时和同步机制是既重要又难于理解的环节之一,它不仅关系到对规范其他相关内容的理解,甚至能对节点开发的成功与否产生直接的影响.因此介绍了位时间(周期)的组成与结构,总结并归纳位定时的作用;在此基础上,给出硬同步和重同步的定义,重点分析硬同步和重同步的机理,并给出它们相应的图解,形象而又清晰地表明其本质;以独立CAN控制器为例,详细说明在一般开发和工程实际中,位定时参数设置和计算的一般方法及步骤.     

CAN总线位定时和同步机制的分析

合理的设置CAN总线位定时能够有效保证位流的同步,提高CAN总线的通讯性能.本文详细分析了CAN总线的位定时和同步机制,并给出了重同步时重同步跳转宽度与相位差补偿的关系.     

MIMO-OFDM系统空间分集定时同步算法

根据MIMO-OFDM系统无线传输信道的特性,提出了基于单个前导子符号的MIMO-OFDM系统空间分集定时同步算法,以克服高速无线多径信道中深衰落对MIMO-OFDM系统定时同步性能的影响,应用概率论推导出MIMO-OFDM系统空间分集算法的定时错误概率分布和概率密度数学表达式,并给出了MIMO-OFDM系统在无线多径信道中帧定时同步的仿真结果.     

一种适合OFDM系统的定时同步方案

文章通过对传统定时同步算法的分析,重新设计了一种前导字结构,并在此基础上改进了定时同步算法.最后,在信道环境下进行仿真,结果表明,改进的前导字具有良好的自相关性,同时文章给出的定时同步算法具有良好的同步性能.     

PCMA系统中位定时误差对干扰抵消性能的影响

首先介绍了PCMA技术的基本概念 ,并建立了PCMA系统基带传输模型 ;在此基础上研究了PCMA系统中位同步误差对干扰抵消性能的影响 ,并给出了相应的仿真结果。根据系统对干扰抑制比的要求 ,仿真结果可以为位定时估计算法的设计提供可靠的依据     

通信系统中同步技术的研究

同步是进行信息传输的关键前提,其工作质量直接决定通信的质量,几乎在所有的通信系统中都要先解决同步问题,稳定、可靠、准确的同步对通信至关重要.为了从整体上理解同步技术,本文系统阐述了载波同步、位同步、群同步和网同步的基本原理,并分析对比了各自的实现方法,最后给出各同步技术的性能指标及对通信系统性能的影响.     

OFDM中的同步

本文简单介绍了正交频分复用(OFDM)技术中同步的问题。本文共分三个部分,第一部分介绍了OFDM的载波同步,给出实现载波同步的方法;第二部分介绍OFDM接收机的样值同步,给出样值同步示意图;第三部分介绍OFDM的符号同步,给出采用最大似然准则估计符号定时同步和载波同步的框图。     

CAN FD总线位定时模块的设计与验证

随着汽车电子设备的发展,传统CAN总线难以满足传输速度快且传送容量大的要求,而CAN FD总线能在兼容CAN的同时提供更快速的通信。CAN FD总线位定时模块在保障CAN FD总线的正常收发过程中发挥重要作用,同时也是CAN FD控制器的重要组成部分和设计难点之一。本文依据ISO11898-1:2015标准研究CAN FD位定时机制,提出一种CAN FD位定时模块设计思路。此模块使用Verilog硬件描述语言实现,采用QuartusⅡ和Modelsim联合仿真来对位速率产生、位速率切换和同步操作功能进行验证。验证结果表明此设计符合ISO11898-1标准规定,能完成FD帧的位时间产生和切换,证明设计思路的正确性和可行性。     

WiMAXOFDMA下行同步原理与仿真

介绍了同步的种类,以及同步的基本方法,给出了WiMAXOFDMA系统的整套同步方案。并利用前导的时域三段伪重复性和共轭对称性结合前人的研究成果,对粗定时、小数倍频偏估计和精定时做了改进,并给出了新方案的仿真图像。     

点对多点通信系统的同步方式

结合笔者研制的一种时分多址(TDMA)一点对多点通信系统,讨论了时分多址系统的位同步、帧同步、复帧同步和网同步。位同步实质是系统主时钟的提取,它通过在帧结构中设置前置码及后续信息扰码,由硬件完成;帧同步是在软件配合下,由硬件对未经扰码的独特码进行正确检测所得示位脉冲完成的;复帧同步是通过在下行帧中设置计数器,在软、硬件配合下实现的;网同步的过程就是系统定时和延时调整过程,它在软、硬件的配合下以用户站接收定时为基准,延迟发送时刻,使各用户站与中心站之间具有相同的等效半径,以期与中心站发送定时同步。时延调整是经人工粗调和自动细调两步完成的。     

CAN总线通信原理分析

介绍了控制器局域网总线(CAN总线)的应用特性以及将其应用于具体的工程项目时CAN总线系统的分层结构及各层的主要功能。基于CAN总线系统结构构成,通过工程实践的具体应用以及对CAN控制器及收发器硬件结构的深入理解,并从通信的角度出发着重深入分析了CAN总线通信的节点同步机制、总线地址机制、总线仲裁机制(即总线的冲突解决机制)以及总线鲁棒性的实现原理。     

积分位同步原理及其HDL实现

位同步是数字通信中必不可少的环节,位同步的功能的好坏直接关系到一个数字接收系统的性能。位同步有外同步与自同步之分,自同步主要有微分同步与积分同步2种。简要介绍了2种同步方法的工作原理及各自的优缺点,并主要介绍了这2种同步方式的鉴相器的区别。HDL是设计数字逻辑电路必不可少的通用工具,该文给出了位同步性能较好的积分型自同步的一个HDL实现。     

Performance evaluation of zero-crossing-based bit synchronizers

Bit synchronization algorithms based on signal zero-crossing analysis are investigated. Their performance is compared to conventional maximum-likelihood-type techniques for symbol timing recovery. The zero-crossing bit synchronizers are shown to be superior for bandlimited pulses such as raised cosine and double-jump frequency rolloff, except for very low signal-to-noise ratios     

Carrier Synchronization Techniques for Unbalanced QPSK Signals-Part II

This paper develops the theory for assessing the tracking performance and designing carrier synchronization loops which are to be matched to an unbalanced QPSK signal design. It is assumed that the power split and theIandQchannel data rates are arbitrary. Bit synchronization is assumed unavailable for both carrier reconstruction techniques which have been suggested via MAP estimation theory. Numerical results are presented along with their comparison with results given in Part I where bit timing was assumed known.     

自噪声抑制Gardner算法及位同步环路设计

位同步技术是空间激光通信和测控一体化的关键技术之一,位同步的精确与否直接影响整个系统的性能。针对空间激光通信位同步技术中基于Gardner定时误差估计算法易受系统自噪声干扰,提出了一种自噪声抑制Gardner算法,同时基于此算法提出一种位同步环路。通过对算法理论分析与环路建模仿真结果表明,在Eb/N0大于9 dB情况下,提出自噪声抑制Gardner算法与位同步环路能够有效地降低同步过程中由于系统自噪声引起的定时抖动,并且拥有更快的位同步建立的时间。     

Bit Synchronization in the Presence of Asymmetric Channel Noise

Bit synchronization in the presence of asymmetric channel noise has not appeared in the open literature. It is the purpose of this paper to study the tracking performance (clock jitter and cycle slip rate) of a popular digital clock synchronizer, the digital data transition tracking loop (DTTL), in the presence of asymmetric noise. Related parameters of interest, the transition density and data asymmetry, are also included. Acquisition performance (frequency acquisition time) is discussed in the absence of noise. A comparison of the DTTL and crossspectrum synchronization loop (CSSL) is also provided. Numerical results are Presented for the design of a bit synchronizer in this environment.     

Digital burst mode clock recovery technique for fiber-optic systems

We present a clock recovery technique for burst mode systems that performs the functions of clock phase recovery, burst synchronization (to determine the first data bit in the burst), and timing alarm generation (to maintain bursts within their designated time slots). The method is based on the use of a correlation algorithm in which the incoming preamble containing a `0 1 0' bit sequence is sampled with multiple clock phases and correlated with stored, time delayed versions of the same sequence. The method was implemented in a 0.7 μm CMOS Application Specific Integrated Circuit (ASIC). Measurements of the phase tracking characteristics over the frequency range of 38 to 90 MHz are presented. Bit error rate measurements made using the device in a burst mode fiber-optic receiver operating at 51.84 Mb/s were also performed, where it was found that the device performed well and was able to perform clock extraction with a penalty of approximately 2 dB with respect to an ideal clock extraction system     

一种新的基于前导序列的MSK位定时同步方法

数字通信系统中,位定时同步是实现正常数字通信的必要条件.本文基于1bit差分解调算法,提出了一种基于前导序列的位定时同步方法.基于前导序列的自相关性,该方法首先将差分解调数据划分为若干并行支路,然后利用并行滑动相关法搜索各支路前导序列的自相关峰,最后根据大数判决方法完成位定时同步.通过Matlab仿真表明,该方法性能接近Monte Ca]or仿真.     

新一代宽带通信卫星系统网络同步方案

网络同步是卫星通信系统的关键技术。针对基于MF-TDMA／TDM体制的新一代宽带多媒体通信卫星系统,提出了网络同步的总体方案;在此基础上,分别设计了上下行链路的帧同步结构和信号流程,并对捕获、失同步后的快速恢复和定时控制方案等关键问题进行了探讨。     

Novel signals for optimized timing synchronization in direct‐sequence spread‐spectrum communication systems

The paper presents design techniques for novel signaling waveforms to optimize timing synchronization in direct‐sequence spread‐spectrum communication systems. Both coarse code timing acquisition and fine delay‐locked loop tracking systems are considered, and their performance metrics are analyzed in terms of initial acquisition detection probability and residual tracking jitter, showing a strong dependency on signal waveform spectral characteristics. Bit error performance under imperfect synchronization is also assessed. A design methodology is formulated with a low complexity parametric optimization approach based on prolate spheroidal waveform expansions for the generation of signals that minimize the probability of acquisition miss and tracking error jitter subject to additional constraints on signal energy and phase transitions. Novel optimized waveforms are synthesized with different levels of effective root mean square bandwidth occupancy and compared with conventional pulses to illustrate their advantages. Performance trade‐offs are demonstrated between the acquisition and tracking systems, whereby signals with low effective bandwidth are found to have better acquisition capability at the expense of poorer tracking jitter, while the converse holds for signals with higher effective bandwidth. It is found that an effective root mean square bandwidth occupancy in the range of 40% to 50% of the chip rate can achieve a good compromise between the requirements of the 2 code timing synchronization phases. Numerical results are presented to quantify the relative merits of representative waveforms with respect to the different performance measures in terms of acquisition capability, tracking jitter, and bit error probability.