Random Yield Prediction Based on a Stochastic Layout Sensitivity Model

Yield loss caused by random defects is an important manufacturability concern. Random yield of modern integrated circuits is associated with layout sensitivity to defects defined as the ratio of critical area to the overall layout area. This paper proposes a methodology to predict random yield with high fidelity based on a stochastic layout sensitivity model that uses very basic layout information. The model has very important applications including pre-layout yield prediction and yield forecasting for future process technologies.      

Layout-synthesis techniques for yield enhancement

Several yield-enhancement techniques are proposed for the last two stages of VLSI design, i.e., topological/symbolic and physical layout synthesis. Our approach is based on modifications of the symbolic/physical layout to reduce the sensitivity of the design to random point defects without increasing the area, rather than fault tolerance techniques. A layout compaction algorithm is presented and the yield improvement results of some industrial layout examples are shown. This algorithm has been implemented in a commercial CAD framework. Some routing techniques for wire length and via minimization are presented, and the results of wire length reduction in benchmark routing examples are shown. We demonstrate through topological optimization for PLA-based designs that yield enhancement can be applied even at a higher level of design abstraction. Experimental results show that it is possible to achieve significant yield improvements without increasing the layout area by applying the proposed techniques during layout synthesis     

A new sensitivity model with blank space for layout optimization

As the technology scales advancing into the nanometer region, the concept of yield has become an increasingly important design metric. To reduce the yield loss caused by local defects, layout optimization can play a critical role. In this paper, we propose a new open sensitivity-based model with consideration of the blank space around the net, and study the corresponding net optimization. The proposed new model not only has a high practicability in the selection of nets to be optimized but also solves the issue of the increase in short critical area brought during the open optimization,which means to reduce the open critical area with no new short critical area produced, and thereby this model can ensure the decrease of total critical area and finally achieves an integrative optimization. Compared with the models available, the experimental results show that our sensitivity model not only consumes less time with concise algorithm but also can deal with irregular layout, which is out of the scope of other models. At the end of this paper, the effectiveness of the new model is verified by the experiment on the randomly selected five metal layers from the synthesized OpenSparc circuit layout.     

基于物理版图信息的低功耗扫描测试方法

芯片测试模式下功耗过高的情形会极大地降低芯片良率,已经成为越来越严重的问题。针对此问题,本文提出了一种降低测试功耗的设计方法。该方法采用贪婪算法来改变扫描链顺序,同时考虑芯片物理版图中寄存器单元的具体位置,能够实现在不影响测试覆盖率和绕线的前提下,快速有效地降低测试功耗。与已有的多种方法相比,该方法更快速更合理,可以应用于多种芯片的扫描链设计。该方法通过一款实际的电力线载波通信芯片验证,分别将平均功耗和瞬态功耗降至77%和83%。     

Integrated circuit yield management and yield analysis: developmentand implementation

Integrated circuit manufacturing yields are not necessarily a function of chip area. Accurate yield analysis shows how the yield depends on circuit design and layout. By determining the probabilities of failure and critical areas for different defect types, it is possible to control and manage the yield of integrated circuits. This includes the manufacture of DRAM's, SRAM's, CMOS logic, ASIC's, and CMOS and biCMOS microprocessors. Examples explain the method of meeting yield objectives by setting targets for yield components. In addition, the yield management approach allows for a systematic allocation of resources. Required defect-density learning determines the contamination levels for clean rooms and process equipment     

Automated evaluation of critical features in VLSI layouts based onphotolithographic simulations

In this paper, we address the problem of identifying and evaluating “critical features” in an integrated circuit (IC) layout. The “critical features” (e.g., nested elbows and open ends) are areas in the layout that are more prone to defects during photolithography. As feature sizes become smaller (sub-micron range) and as the chip area becomes larger, new process techniques (such as, using phase shifted masks for photolithography), are being used. Under these conditions, the only means to design compact circuits with good yield capabilities is to bring the design and process phases of IC manufacturing closer. This can be accomplished by integrating photolithography simulators with layout editors. However, evaluation of a large layout using a photolithography simulator is time consuming and often unnecessary. A much faster and efficient method would be to have a means of automatically identifying “critical features” in a layout and then evaluate the “critical features” using a photolithography simulator. Our technique has potential for use either to evaluate the limits of any new and nonconventional process technique in an early process definition phase or in a mask house, as a postprocessor to improve the printing capability of a given mask. This paper presents a CAD tool (an Integrated CAD Framework) which is built upon the layout editor, Magic, and the process simulator, Depict 3.0, that automatically identifies and evaluates “critical features”     

Critical area and critical levels calculation in IC yield modeling

A method is described for calculating critical coefficients to be included in an IC yield model for each masking step. The yield model is a function of the chip surface, the defect density, and a mathematical law. The method relies on partitioning total mask area at each level into area subcomponents sensitive to a minimal defect size using a design rule checker program. Defect density with respect to size has been experimentally determined, and the selected mathematical law corresponded to the data. Yield per level Y_i was determined by applying the model to critical areas with their corresponding defect densities. The calculation of α_i has been carried out using the equation Y_i=1/(1+A_Tλ^α i) where Y_i is the i-level yield, A_T the total chip area, and λ the average value of defect density per level. It has been found that the resultant α_i values are stable in a given environment whatever the technology, the average defect density value, and the design rules     

Critical area extraction for soft fault estimation

Algorithms are presented for extracting the critical area associated with extra and missing material soft faults of an integrated circuit from the mask layout. These algorithms have been implemented within the Edinburgh Yield Estimator (EYE) tool which permits efficient extraction of the critical area from an arbitrary mask layout. Accurate estimates of device critical area of even the largest devices can be obtained in a reasonable time using the sampling version of the tool. The application of these algorithms to defect related reliability is explored and results reported that compare the susceptibility to soft faults before and after layout modifications intended to enhance manufacturing yield. These results suggest that yield enhancement techniques can have a significant impact on defect-related device reliability     

Accurate estimation of defect-related yield loss in reconfigurableVLSI circuits

A general methodology for accurate estimation of defect-related yield loss in reconfigurable VLSI circuits is presented. Yield for replicated cells in the reconfigurable circuitry is estimated based upon a calculation of layout sensitivity to manufacturing defects of varying sizes. The important concept addressed is the need for separate estimation of reconfigurable and nonreconfigurable components of a replicated cell's critical area (CA) for accurate yield estimation. Two examples-a 256 kb SRAM and reconfigurable 32×32 port 32 b crossbar switch-are presented to illustrate the essential characteristics of the proposed yield estimation method     

A layout-driven yield predictor and fault generator for VLSI

The authors present an efficient approach to probability-graded fault list generation, and critical area calculation for IC yield production. The approach is also efficient to program because it is built on top of existing design rule checking routines. The accuracy of the tool is enhanced by including in the critical area calculations adjustments for defects occurring at the end of a feature and validating shorts before including the associated critical area in the sum. It would be possible to make the approach more efficient by going to an entirely graph-based approach, thus avoiding the physical tile generation step     

A New Flexible Algorithm for Random Yield Improvement

This paper presents a new and improved solution for random yield improvement at the post-routing stage. The proposed solution is better suited for current processes, where a clustering effect has been observed resulting in differing particle densities in the metal and empty regions of the chip. To account for this clustering effect, we introduce the concept of weighted critical area to serve as a proxy for random yield loss. A new algorithm for weighted critical area minimization is also introduced. The proposed optimization solution derives a weighted critical area based on the user-specified particle densities. It then uses this weighted critical area information to dynamically select the appropriate critical area reduction technique in each local region to guarantee a reduction of the weighted critical area in both the local region and the whole layer. This makes the algorithm flexible and readily applicable to different process lines. It consistently improves the random yield irrespective of the particle densities in the metal and empty regions of the chip.     

A post-package bit-repair scheme using static latches withbipolar-voltage programmable antifuse circuit for high-densityDRAMs

A bipolar-voltage programmable antifuse circuit scheme and bit-repair scheme are newly proposed for post package repair. For fail-bit repair, the antifuses in the proposed scheme are programmed by bipolar voltages of V_CC and -V_CC, alleviating high-voltage problems such as permanent device breakdown and achieving a smaller layout area for the antifuse circuit than the previous scheme. In addition, an efficient bit-repair scheme is used instead of the conventional line-repair scheme, reducing the layout area for the redundancy bits. Also, using static latches instead of dynamic memory cells for the redundancy bits eliminates possible defects in the redundancy area, making this bit-repair scheme robust and avoiding burn-in stress issues. Through manufacturing commercial DRAM products, the yield improvement by the one-bit post-package repair reaches as much as 2.4% for 0.16-μm triple-well 256-M SDRAM     

Yield modeling based on in-line scanner defect sizing and acircuit's critical area

Wafers containing a large number of defects on any layer should be discarded in order to avoid the cost associated with processing wafers that are unlikely to yield. Normally decisions about scrapping wafers are based on defect counts. However, including the size of defects can improve the accuracy of such dispositions. If the size of defects is taken into account, critical area provides an estimate of the kill ratio associated with defects of a given size, where the critical area of a layer of a circuit is computed from a circuit's layout. In this paper, the accuracy of the sizing of defects by in-line scanners is analyzed. Then, the impact of defect sizing inaccuracy on estimates of layer yield is discussed, and a methodology to more accurately compute layer yield and kill ratios is presented, which calibrates for inaccuracy in defect sizing by in-line scanners     

A Discrete Fourier-Cosine Transform Chip

An 8-point Fourier-cosine transform chip designed for a data rate of 100 Mbits/s is described. The top-down design is presented step by step, including algorithm modification for VLSI suitability, architectural choices, testing overhead, internal precision assignments, mask generation, and finally, verification of the layout. A high-level language (C) design tool was developed concurrently with the layout. This tool allows mimicking exactly the different representations of the algorithm: software, mask, and chip. This provides an automatic cross-checking at all design stages. The VLSI environment created by this tool, as well as existing powerful CAD tools, made a fast design-time possible.     

Fast compensative design approach for the approximate squaringfunction

In this paper, a systematic compensation approach is presented to efficiently design the approximate squaring function with a simple combinational logic circuit. Also, a set of recursive Boolean equations for general outputs is derived such that the logic circuit can be rapidly designed and reused for various bit-width inputs. In logic implementation, our design approach possesses less circuit cost and lower critical delay. Moreover, in error analysis, the maximum relative error (MRE) and average relative error (ARE) of squaring approximation are significantly improved by at least 26.95% and 61.59%, respectively, as compared with the existing approaches. Finally, a 7-bit approximate squaring function chip is accomplished to verify the circuit performance based on 0.6-μm CMOS technology. The chip layout occupies 127×135 μm² and the total number of transistors is 186     

基于红外热图序列的板级芯片故障诊断研究

提出一种基于红外热图序列的板级芯片开/短路缺陷检测方法。首先记录芯片关键区域在上电程序响应过程的温度均值序列,运用Savitzky Golay卷积平滑法对其平滑滤波后提取时域特征参量,利用主成分分析法优选关键特征;然后构建支持向量机分类模型,利用粒子群算法优化支持向量机模型参数,使其能有效区分不同的电路板故障类型。为验证提出的方法在芯片开/短路缺陷检测中的有效性,在开发板上的主控芯片上进行了多种焊球开/短路模拟实验。结果表明,优化后的分类模型在测试集的交叉验证分类准确率为96.90%,证明了该方法诊断芯片开/短路缺陷的有效性。     

Targeted layout modifications for semiconductor yield/reliability enhancement

A new layout modification tool for the automation of layout modifications to improve the yield and reliability of semiconductor IC layout is reported. The Peye tool combines a polygon library with the practical extraction and reporting language (Perl). This new tool permits complex layout modification operations to be defined using the powerful language features of Perl. The Peye tool has been interfaced with a sampling-based yield prediction system to enable the measurement of the layout modifications and yield predictions based on these modifications. This enables the usefulness of a modification to a particular design to be assessed by sampling before use. Both the sampled measurement and the final modifications to the whole chip database can be farmed out to a number of networked computers, enabling the system to assess and apply layout modifications to large industrial ICs in a reasonable time. The results of layout modifications are presented.     

Product Yield Prediction System and Critical Area Database

Pre-silicon yield estimators for ASIC products have the potential for improved accuracy based on retrospective critical area and yield analysis of completed designs. A prototype closed-loop system, in which a database of observed yield and computed critical areas is continuously compiled and updated, is described in this paper. The database allows a yield model based on circuit content, which is available at the time of quote, but before the physical layout, to be optimized to more accurately reflect a technology's random defect sensitivities. Confining one's observations to the mature 130-nm technology minimizes the inclusion of systematic defects in the observed yield and allows for a more complete view of the random defect component of yield loss.      

A unified yield model incorporating both defect and parametriceffects

A new approach to modeling yield is presented, which inherently includes both the effects of the conventional defect contributors and the parametric yield loss contributors often treated separately in existing yield models. These parametric yield losses are particularly important during the startup yield-improvement phase of new technology introduction, in many performance-sensitive products such as analog devices and high-speed digital devices, and in analyses of bin-split yields. By assuming a distribution in the size of defects, from point defects up to defects as large as or larger than a wafer, the parametric yield contributors can be viewed as simply rather large, design-dependent defects, which will render IC's unacceptable if any portion of the large defect overlaps the defect-sensitive area of a chip. In this way, the conventional Poisson model, or various extensions of the well-known Murphy model, can be augmented in a straightforward and general way to include parametric yield loss. It is shown that parametric yield losses introduce an additional die size dependence for yield that can help to account for the observed dependence of yield on die area. The model is compared to other models and to experimental yield data to illustrate both its utility in separating yield contributors and its close agreement with experimental yield data     

Yield analysis and process modeling of low cost, high throughputflip chip assembly based on no-flow underfill materials

As a concept to achieve low-cost, high-throughput flip chip on board (FCOB) assembly, a new process has been developed implementing next generation flip chip processing based no-flow fluxing underfill materials. The low-cost, high throughput flip chip process implements large area underfill printing, integrated chip placement and underfill flow and simultaneous solder interconnect reflow and underfill cure. The goals of this study are to demonstrate feasibility of no flow underfill materials and the high throughput flip chip process over a range of flip chip configurations, identify the critical process variables affecting yield, analyze the yield of the high throughput flip chip process, and determine the impact of no-flow underfill materials on key process elements. Reported in this work is the assembly of a series of test vehicles to assess process yield and process defects. The test vehicles are assembled by depositing a controlled mass of underfill material on the chip site, aligning chip to the substrate pads, and placing the chip inducing a compression type underfill flow. The assemblies are reflowed in a commercial reflow furnace in an air atmosphere to simultaneously form the solder interconnects and cure the underfill. A series of designed experiments identify the critical process variables including underfill mass, reflow profile, placement velocity, placement force, and underfill material system. Of particular interest is the fact that the no-flow underfill materials studied exhibit an affinity for unique reflow profiles to minimize process defects