融合宏块平坦度和时空相关性的预测模式选择算法

H.264/AVC以巨大编码复杂度为代价,在获得更高压缩率的同时,编码实时性也随之降低。针对视频编码中重要且耗时的帧间预测技术,分析了宏块平坦度和时空相关性,提出了一种快速的预测模式选择算法。仿真实验结果表明,本文提出算法与H.264/AVC(JM12.2)标准算法相比,在保持重建视频图像质量和输出码流结构的前提下,平均节省约70%的编码时间,并继承了H.264/AVC低码率的编码优势。     

Fast Interframe mode decision algorithm based on mode mapping and MB activity for MPEG-2 to H.264/AVC transcoding

Recently the latest video coding standard H.264/AVC is widely used for the mobile and low bitrate video codec in the various multimedia terminals. On the other hand, the MPEG-2 MP@HL codec has become the center of digital video contents since it is the standard codec for the Digital TV (DTV). To provide the bridge between the contents in MPEG-2 and mobile terminals, the transcoding of MPEG-2 contents into H.264/AVC format is an inevitable technology in the digital video market. The main bottleneck in the process lies in the computational complexity. In H.264/AVC, the variable block size (VBS) mode decision (MD) is used in the Interframe for the improved performance in the motion compensated prediction. For the macroblock (MB) which cannot be accurately predicted with one motion vector (MV), it is partitioned into smaller blocks and predicted with different MVs. In addition, SKIP and Intra modes are also permitted in the Interframe MD of H.264/AVC to further ameliorate the encoding performance. With the VBS MD technology, the Inter prediction accuracy can be improved significantly. However, the incidental side-effect is the high computational complexity. In this paper, we propose a fast Interframe MD algorithm for MPEG-2 to H.264/AVC transcoding. The relationships between SKIP and Intra modes are detected at first to map these two kinds of modes directly from MPEG-2 to H.264/AVC. And then the MB activity will be scaled by the residual DCT energy obtained from the MPEG-2 decoding process to estimate the block sizes of the MB mode for H.264/AVC Interframe MD. In our proposed method, the original redundant candidate modes can be eliminated effectively, resulting in the reduction of the computational complexity. It can reduce about 85% Rate-to-Distortion Cost (RDCost) computing and 45% entire processing time compared with the well-known cascaded transcoder while maintaining the video quality.     

Efficient error resilient algorithm for H.264/AVC: mobility management in wireless video streaming

The H.264/AVC standard introduces enhanced error robustness capabilities enabling resilient and reliable transmission of compressed video signals over wireless lossy packet networks. Those robustness capabilities are achieved by integrating some new error resilience tools that are essential for a proper delivery of real-time video services. Those tools include the Intra Refreshing (IR), Arbitrary Slice Ordering (ASO), Sequence Picture Parameter Sets (PPS), Redundant Slices (RS) tools and Flexible Macroblock Ordering (FMO). This paper presents an error resilient algorithm in wireless H.264/AVC streaming. The proposed method merges Reference Frame Selection (RFS), Intra Redundancy Slice and Adaptive Intra Refreshment techniques in order to prevent temporal error propagation in error-phone wireless video streaming. The coding standards only specify the decoding process and the bitstream syntax to allow considerable flexibility for the designers to optimize the encoder for coding performance improvement and complexity reduction. Performance evaluations demonstrate that the proposed encoding algorithm outperforms the conventional H.264/AVC standard. Both subjective and objective visual quality comparative study has been also carried out in order to validate the proposed approach. The proposed method can be used and integrated into H264/AVC without violating the standard.     

Adaptive slice-level parallelism for H.264/AVC encoding using pre macroblock mode selection

In order to achieve high computational performance and low power consumption, many modern microprocessors are equipped with special multimedia instructions and multi-core processing capabilities. The number of cores on a single chip increases double every three years. Therefore, besides complexity reduction by smart algorithms such as fast macroblock mode selection, an effective algorithm for parallelizing H.264/AVC is also very crucial in implementing a real-time encoder on a multi-core system. This algorithm serves to uniformly distribute workloads for H.264/AVC encoding over several slower and simpler processor cores on a single chip. In this paper, we propose a new adaptive slice-size selection technique for efficient slice-level parallelism of H.264/AVC encoding on a multi-core processor using fast macroblock mode selection as a pre-processing step. For this we propose an estimation method for the computational complexity of each macroblock using pre macroblock mode selection. Simulation results, with a number of test video sequences, show that, without any noticeable degradation, the proposed fast macroblock mode selection reduces the total encoding time by about 57.30%. The proposed adaptive slice-level parallelism has good parallel performance compared to conventional fixed slice-size parallelism. The proposed method can be applied to many multi-core systems for real-time H.264 video encoding.     

Encoder adaptable difference detection for low power video compression in surveillance system

As a state-of-the-art video compression technique, H.264/AVC has been deployed in many surveillance cameras to improve the compression efficiency. However, it induces very high coding complexity, and thus high power consumption. In this paper, a difference detection algorithm is proposed to reduce the computational complexity and power consumption in surveillance video compression by automatically distributing the video data to different modules of the video encoder according to their content similarity features. Without any requirement in changing the encoder hardware, the proposed algorithm provides high adaptability to be integrated into the existing H.264 video encoders. An average of over 82% of overall encoding complexity can be reduced regardless of whether or not the H.264 encoder itself has employed fast algorithms. No loss is observed in both subjective and objective video quality.     

A high performance and low complexity sampling-based intra coding method for H.264/AVC

The H.264/AVC video coding standard can achieves higher compression performance than previous video coding standards, such as MPEG-2, MPEG-4, and H.263. Especially, in order to obtain the high coding performance in intra pictures, the H.264/AVC encoder employs various directional spatial prediction modes and the rate-distortion (RD) optimization technique inducing high computational complexity. For further improvement in the coding performance with the low computational complexity, we introduce a sampling-based intra coding method. The proposed method generates two sub-images, which are defined as a sampled sub-image and a prediction error sub-image in this paper, from an original image through horizontal or vertical sampling and prediction processes, and then each sub-image is encoded with different intra prediction modes, quantization parameters, and scanning patterns. Experimental results demonstrate that the proposed method significantly improves the intra coding performance and reduces the encoding complexity with the smaller number of the RD cost calculation process.     

Low-Cost H.264/AVC Inter Frame Mode Decision Algorithm for Mobile Communication Systems

One of the important issues of green mobile networking is the low energy consumption for either mobile devices or transmissions. To adapt this, a low-cost Inter frame mode decision (MD) algorithm is proposed for H.264/AVC encoder to reduce the computational complexity of the original encoding procedure in this paper. The information extracted from macroblock (MB), such as energy, temporal domain mode similarity and so on, which can be used to pre-estimate the optimal mode of the MB is investigated and utilized to eliminate the redundant mode candidates. The performance evaluations including quantitative analysis and PC simulations show that the proposed algorithm is an energy-efficient source coding because it can reduce around 85% Inter frame encoding time with little quality loss. It can be widely implemented in green mobile networking systems with H.264/AVC standard to realize the real-time video signal coding.     

A Fast Intra Skip Detection Algorithm for H.264/AVC Video Encoding

A fast intra skip detection algorithm based on the rate‐distortion (RD) cost for an inter frame (P‐slices) is proposed for H.264/AVC video encoding. In the H.264/AVC coding standard, a robust rate‐distortion optimization technique is used to select the best coding mode and reference frame for each macroblock (MB). There are three types of intra predictions according to profiles. These are 16×16 and 4×4 intra predictions for luminance and an 8×8 intra prediction for chroma. For the high profile, an 8×8 intra prediction has been added for luminance. The 4×4 prediction mode has 9 prediction directions with 4 directions for 16×16 and 8×8 luma, and 8×8 chrominance. In addition to the inter mode search procedure, an intra mode search causes a significant increase in the complexity and computational load for an inter frame. To reduce the computational load of the intra mode search at the inter frame, the RD costs of the neighborhood MBs for the current MB are used and we propose an adaptive thresholding scheme for the intra skip extraction. We verified the performance of the proposed scheme through comparative analysis of experimental results using joint model reference software. The overall encoding time was reduced up to 32% for the IPPP sequence type and 35% for the IBBPBBP sequence type.     

A Very High Throughput Deblocking Filter for H.264/AVC

This paper presents a novel hardware architecture for the real-time high-throughput implementation of the adaptive deblocking filtering process specified by the H.264/AVC video coding standard. A parallel filtering order of six units is proposed according to the H.264/AVC standard. With a parallel filtering order (fully compliant with H.264/AVC) and a dedicated data arrangement in local memory banks, the proposed architecture can process filtering operations for one macroblock with less filtering cycles than previously proposed approaches. Whereas, filtering efficiency is improved due to a novel computation scheduling and a dedicated architecture composed of six filtering cores. It can be used either into the decoder or the encoder as a hardware accelerator for the processor or can be embedded into a full-hardware codec. This developed Intellectual Property block-based on the proposed architecture supports multiple and high definition processing flows in real time. While working at clock frequency of 150 MHz, synthesized under 65 nm low power and low voltage CMOS standard cell technology, it easily meets the throughput requirements for 4 k video at 30 fps of all the levels in H.264/AVC video coding standard and consumes 25.08 Kgates.     

Fast block mode decision algorithm in H.264/AVC video coding

The recent video coding standard H.264/AVC show extremely higher coding efficiency compare to any other previous standards. H.264/AVC can achieve over 50% of bit rate saving with same quality using the rate–distortion process, but it brings high computational complexity. In this paper, we propose an algorithm that can reduce the complexity of the codec by reducing the block mode decision process adaptively. Block mode decision process in H.264/AVC consists of inter mode decision process and intra mode decision process. We deal with reduction method for inter and intra mode decision. In this paper an efficient method is proposed to reduce the inter mode decision complexity using the direct prediction methods based on block correlation and adaptive rate distortion cost threshold for early stopping. The fast intra mode reduction algorithm based on inter mode information is also proposed to reduce the computational complexity. The experimental results show that the proposed algorithm can achieve up to 63.34–77.39% speed up ratio with a little PSNR loss. Increment in bit requirement is also not much noticeable.     

A 212 MPixels/s 4096 $times$ 2160p Multiview Video Encoder Chip for 3D/Quad Full HDTV Applications

Multiview video coding (MVC) plays an important role in a 3-D video system. In addition, the resolution of HDTV is increasing to present more vivid perception for users. To realize real-time processing of dozens of TOPS, VLSI solution is necessary. However, ultra high computational complexity, a large amount of external memory bandwidth and on-chip SRAM size, and complex MVC prediction structures are three main design challenges of implementation of MVC hardware architecture. In this paper, an MVC single-chip encoder is proposed for H.264/AVC Multiview High Profile and High Profile for 3-D and quad full high definition (QFHD) TV applications, respectively. The 4096 × 2160 p multiview video encoder chip is implemented on a 11.46 mm² die with 90 nm CMOS technology. An eight-stage macroblock pipelined architecture with proposed system scheduling and cache-based prediction core supports real-time processing from one-view 4096 × 2160 p to seven-view 720 p videos. The 212 Mpixels/s throughput is 3.4 to 7.7 times higher than previous work. The 407 Mpixels/W power efficiency is achieved, and 94% on-chip SRAM size and 79% external memory bandwidth are saved by the proposed techniques.     

Computation-aware fast motion estimation for H.264/AVC using image indexing

The key to designing a real-time video coding system is efficient motion estimation, which reduces temporal redundancies. The motion estimation of the H.264/AVC coding standard can use multiple references and multiple block sizes to improve rate-distortion performance. The computational complexity of H.264 is linearly dependent on the number of allowed reference frames and block sizes using a full exhaustive search. Many fast block-matching algorithms reduce the computational complexity of motion estimation by carefully designing search patterns with different shapes or sizes, which have a significant impact on the search speed and distortion performance. However, the search speed and the distortion performance often conflict with each other in these methods, and their high computational complexity incurs a large amount of memory access. This paper presents a novel block-matching scheme with image indexing, which sets a proper priority list of search points, to encode a H.264 video sequence. This study also proposes a computation-aware motion estimation method for the H.264/AVC. Experimental results show that the proposed method achieves good performance and offers a new way to design a cost-effective real-time video coding system.     

H.264 motion estimation algorithm based on video sequences activity

Motion estimation is an important part of H.264/AVC encoding progress, with high computational complexity. Therefore, it is quite necessary to find a fast motion estimation algorithm for real-time applications. The algorithm proposed in this letter adjudges the macroblocks activity degree first; then classifies different video sequences, and applies different search strategies according to the result. Experiments show that this method obtains almost the same video quality with the Full Search （FS） algorithm but with reduced more than 95% computation cost.     

Adaptive video coding control for real-time H.264/AVC encoder

In this paper, we present a new adaptive video coding control for real-time H.264/AVC encoding system. The main techniques include: (1) the initial quantization parameter (QP) decision scheme is based on Laplacian of Gaussian (LoG) operators; (2) the MB-level QP calculation is based on the spatio-temporal correlation, in which the computation is less than the quadratic model used by H.264/AVC; (3) the adaptive GOP structure is proposed, in which the I-frame is adaptively replaced by an enhancement P-frame to improve the coding efficiency; (4) the scene change is detected with the complexity of adjacent inter-frames and the appropriate QP is re-calculated for the scene-change frame. The proposed algorithm is not only to save the computational complexity but also to improve coding quality. Compared to the JM12.4 reference under various sequences testing, the proposed algorithm can decrease coding time by 64.5% and improve PSNR by 1.52 dB while keeping the same bit-rate.     

嵌入式平台下的安全媒体传输系统

Security video communication is a challenging task, especially for wireless video applications. An efficient security multimedia system on embedded platform is designed. By analyzing the hardware architecture and resource, the efficient DSP-based H.264/AVC coding is studied by efficient video coding techniques and system optimizing implementation.To protect the confidentiality and integrity of media information, a novel security mechanism is presented, which includes user identify authentication and a perceptual video encryption algorithm based on exploiting the special feature of entropy coding in H.264. Experimental results show that the proposed hardware framework has high performance and achieves a better balance between security and efficiency. The proposed security mechanism can achieve high security and low complexity cost, and has a little effect on the compression ratio and transmission bandwidth. What’s more, encoding and encryption at the same time, the performance of data process can meet real-time application.     

Hierarchical B-picture mode decision in H.264/SVC

To enable robust video transmission over heterogeneous networks, the hierarchical B-picture prediction structure is employed in the state-of-the-art video coding standard H.264/SVC, aiming to produce scalable bitstreams with various frame rates. However, the exhaustive mode decision process with the hierarchical B-picture structure increases the computational complexity of H.264/SVC encoding dramatically. In this paper, a fast mode decision algorithm is proposed to speed up H.264/SVC encoding with the hierarchical B-picture structure, which is achieved by utilizing macroblock (MB) features, correlation of temporal–spatial neighboring MBs, and the discrepant characteristics of hierarchical layers. Extensive experimental results demonstrate that the proposed algorithm is able to reduce the encoding time of H.264/SVC significantly for video sequences with a wide range of resolutions, and meanwhile the video quality and compression ratio are well preserved.     

A 0.7-V 1.8-mW H.264/AVC 720p Video Decoder

The H.264/AVC video coding standard can deliver high compression efficiency at a cost of increased complexity and power. The increasing popularity of video capture and playback on portable devices requires that the power of the video codec be kept to a minimum. This work implements several architecture optimizations such as increased parallelism, pipelining with FIFOs, multiple voltage/frequency domains, and custom voltage-scalable SRAMs that enable low voltage operation to reduce the power of a high-definition decoder. Dynamic voltage and frequency scaling can efficiently adapt to the varying workloads by leveraging the low voltage capabilities and domain partitioning of the decoder. An H.264/AVC Baseline Level 3.2 decoder ASIC was fabricated in 65-nm CMOS and verified. For high definition 720p video decoding at 30 frames per second (fps), it operates down to 0.7$~$ V with a measured power of 1.8 mW, which is significantly lower than previously published results. The highly scalable decoder is capable of operating down to 0.5 V for decoding QCIF at 15 fps with a measured power of 29 $mu$W.      

Fast Algorithm and Efficient Architecture for Integer and Fractional Motion Estimation

Motion estimation in H.264/AVC, is done in two parts – integer motion estimation, and fractional motion estimation. Hardware reuse for both parts is inefficient due to the differences between them. In this paper we address the hardware reuse problem by proposing a, fast motion estimation algorithm as well as a pipelined FPGA-based, field programmable system-on-chip (FPSoC), for integer and fractional motion estimation. Our results show that the rate-distortion loss of our algorithm is insignificant when compared to full search in H.264/AVC. Its average Y-PSNR loss is 0.065 dB, its average percentage bit rate increase is 5 %, and its power consumption is 76 mW. Our FPSoC is hardware-efficient, even out-performing some state-of-the-art ASIC implementations. It can support up to high definition 1280?×?720p video at 24Hz. Thus, our proposed algorithm and architecture is suitable for delivery of high quality video on low power devices and low bit rate applications which typically use H.264/AVC baseline profile@levels 1–3.1.     

基于H.264编码的多屏共享系统研究

H.264/AVC是一种由ITU-T视频编码专家组合ISO/IEC JTC1动态图像专家组联合提出的高度压缩视频编码器标准。然而H.264/AVC编码器较高的运算复杂度提高了多屏共享系统的延迟时间。H.264/AVC由多种开源的实现,其中X264因简单高效而得到广泛的应用。在此对多频共享系统的关键技术进行实现,分析X264编码器提供的运动估计算法并且提出一种优化的算法。实验表明,新的算法提高了编码的速度、减少了系统延迟时间,同时视频质量几乎没有产生损失。     

Reference frame modification techniques for temporal and spatial scalability

Compressed video is usually transmitted over channels which are not necessarily error free. Channel errors can result in a mismatch between the encoder and the decoder, and because of the predictive structures used in video coding, the errors will propagate both temporally and spatially. Consequently, the quality of the received video at the decoder may degrade significantly. In order to improve the quality of the received video, several error resilient methods have been proposed. In this paper, the introduced mismatch is reduced by modifying the prediction structure and forming a more robust reference frame. The proposed technique combines error robustness of previous Intra coded blocks, better prediction achieved using the previous reference frame, and exponential decay of error propagation caused by the leaky prediction. This technique was examined with the scalable extension of H.264/AVC. Furthermore, the technique was also used in combination with random Intra refresh and error resilience mode decision techniques to achieve better robustness. Simulation results show the effectiveness of our scheme, especially for medium and high motion sequences.