Low complexity output generalized memory polynomial model for digital predistortion of RF power amplifiers

A novel output generalized memory polynomial (OGMP) behavioral model was proposed in this article, which is based on the previous output signal for digital predistortion (DPD) of power amplifiers (PA). Traditional MP or GMP model use polynomials of the previous input signal to characterize memory effect. Although the OGMP model use polynomials of the previous output signal to characterize memory effect. Using the previous output signal to characterize polynomials of the previous input signal, the number of coefficients will decrease. Measurement results show that the proposed OGMP model can achieve the similar effect with less coefficients. In detail, the complexity of OGMP model reduced by about 50% comparing with MP model. Compared with GMP model, the complexity of OGMP model reduced by about 60% with the similar effect.     

基于分段线性函数的功放模型及数字预失真应用

为了克服通信系统中功率放大器的非线性和记忆效应,数字预失真技术成为研究的热点。提出一种基于分段线性函数的多项式模型,与广义记忆多项式模型相比,我们把多项式中的高阶项转换为分段求和项,消除了高阶相乘带来的不稳定性,同时由于分段阈值的存在,该模型的适用性和稳定性均有所提高。把功放模型应用于数字预失真结构中的实验结果表明:与广义记忆多项式模型相比,分段线性函数模型所需系数要少40%,邻信道功率比提高约1dB,归一化均方误差提高约8dB,因此该模型在数字预失真方面具有较好的效果。     

Dynamic deviation reduction‐based concurrent dual‐band digital predistortion

This article introduces the concurrent dual‐band digital predistortion (DPD) architecture with only one upconvertion unit, which is suitable for the linearization of wideband power amplifiers (PAs) excited by concurrent dual‐band signals. By extending the conventional dynamic deviation reduction (DDR) model to the concurrent dual‐band mode, we propose two DDR‐based concurrent dual‐band models, the dual‐band DDR (DB‐DDR) model and the simplified dual‐band DDR (SDB‐DDR) model. The performance of these two models is experimentally assessed with two types of wideband PAs (a GaN Class F PA and a GaN Doherty PA) driven by the concurrent dual‐band signal, and compared with the prior two‐dimensional digital predistortion (2D‐DPD) model and the two‐dimensional modified memory polynomial (2D‐MMP) model. The results prove the good DPD performance and low computational complexity of the proposed models. © 2013 Wiley Periodicals, Inc. Int J RF and Microwave CAE 24:401–411, 2014.     

One‐bit in‐phase observation for direct learning‐based digital predistortion with modified frequency‐domain delay estimation and alignment

This article proposes a novel digital predistortion (DPD) implementation method for RF power amplifiers. The new approach adopts only one 1‐bit comparator in the feedback path to observe the in‐phase (I) or the quadrature (Q) component of the error signal between the input and the output signals. To this end, the theoretical derivation of the in‐phase observation based on direct learning architecture (DLA) DPD is first given in this article, by combining the existing 1‐bit method and the low‐cost in‐phase observation. To facilitate the delay estimation and alignment, a modified iterative frequency‐domain delay estimation is presented, which only acquires either I or Q components of the output signal to achieve satisfied delay estimation. Experimental results show that the proposed DPD method decreased the normalized mean square error (NMSE) and the adjacent channel power ratio (ACPR) to less than ?42 and ?51 dB, respectively, which indicates that the proposed DPD system can achieve comparable performance as the existing DPD identification techniques with lower implementation complexity.     

基于双核NiosⅡ系统的数字预失真器设计

设计了一种基于双核Nios Ⅱ系统的数字预失真器(DPD)。在FPGA中构建多查找表结构,实现了基于记忆多项式模型的DPD;采用双核处理器完成并行RLS算法处理,保证了DPD模型参数提取过程的执行效率。实验结果证明,该系统能够对功放的非线性进行较好补偿。     

硅压阻式压力传感器误差修正算法的FPGA实现

针对现场可编程门阵列(FPGA)的输入输出(L/O)资源丰富、并行执行特点对设计大规模硅压阻式压力传感器补偿系统以及提高其补偿效率有一定的意义,提出了一种FPGA补偿系统设计方案并对传感器输入输出存在的非线性误差,设计了32位单精度浮点运算单元实现曲线拟合法中的多项式拟合算法,使用Verilog语言在Xilinx ISE中实现FPGA的逻辑设计、仿真和综合.结果证明:设计的可在FPGA中综合实现的多项式拟合算法效果显著,可以对非线性系统进行校正,有较高的应用价值.     

一种低功耗DCT硬件结构的设计

提出一种基于CSD编码的向量内积分布式计算结构CDA,将其应用于二维离散余弦变换(DCT)硬件设计,利用DCT变换矩阵的编码特点减少设计中加法器的数量及移位累加树的带宽。该结构在Chartered 0.13 μm工艺库上进行设计和综合,共用了31 528个晶体管和1 024 bit存储器,具有低功耗与高性能的特点,适用于图像视频等要求低功耗、实时处理的领域。     

Orthonormal basis functions for memory predistorter in oversampled systems

Volterra model or memory polynomial model are commonly used to describe the nonlinearity with memory effects for power amplifier (PA) modeling as well as digital predistorter designs. Different monomial terms of the Volterra model or memory polynomial model are highly correlated, which become a challenge during the fixed‐point implementation of the coefficients estimation as the data matrix is ill‐conditioned. Previous works derived orthogonal basis functions to eliminate the correlation among different monomial terms. Conversely, models of the PAs or the digital predistorters work in the oversampled domain to capture the adjacent band and/or out of band emissions. The correlation among data samples, which was neglected in previous works, can also be a major issue to the numerical instability in the coefficients estimation. In this article, we propose a set of new orthonormal basis functions to eliminate the correlation among different monomial terms as well as the correlation among data samples. As the proposed orthonormal basis functions can be predetermined and implemented with look up tables, the fixed‐point implementation is feasible and online computational complexity is greatly reduced. Simulation and experimental results show that the proposed orthonormal basis functions outperform the conventional ones in terms of condition number reduction as well as spectral regrowth suppression. © 2014 Wiley Periodicals, Inc. Int J RF and Microwave CAE 25:202–212, 2015.     

Efficient dynamic priority based soft error mitigation techniques for configuration memory of FPGA hardware

Radiation-induced single bit upsets (SBUs) and multi-bit upsets (MBUs) are more prominent in Field Programmable Gate Arrays (FPGAs) due to the presence of a large number of latches in the configuration memory (CM) of FPGAs. At the same time, SBUs and MBUs in the CM can permanently or temporarily affect the hardware circuit implemented on FPGA. Hence, error mitigation and recovery techniques are necessary to protect the FPGA hardware from permanent faults arising due to such SBUs and MBUs. Different existing techniques used to mitigate the effect of soft errors in FPGA have high overhead and their implementations are also quite complex. In this paper, we have proposed efficient single bit as well as multi-bit error correcting methods to correct errors in the CM of FPGAs using simple parity equations and Erasure code. These codes are easy to implement, and the needed decoding circuits are also simple. Use of Dynamic Partial Reconfiguration (DPR) along with a simple hardware scheduling algorithm based download manager helps to perform the error correction in the CM without suspending the operations of the other hardware blocks. We propose a first of its kind methodology for novel transient fault correction using efficient error correcting codes with hardware scheduling for FPGAs. To validate the design we have tested the proposed methodology with Kintex FPGA. We have also measured different parameters like fault recovery time, power consumption, resource overhead and error correction efficiency to estimate the performance of our proposed methods.     

基于直接学习法的一种新预失真器

为了克服宽带信号经过记忆放大器的非线性失真,针对有记忆非线性功放的多项式模型,提出了一种新的基于直接学习法的自适应算法.该算法采用无记忆预失真器的级联扩展,具有横向滤波器结构,与记忆多项式有相似的线性化效果.并且针对信号噪声对自适应算法的扰动和收敛速度慢等缺点,采用归一化LMS算法加以改进.在非线性功放的记忆多项式模型下,通过宽带信号验证了基于直接学习法的记忆型预失真器算法的有效性.     

A small‐area and low‐power data driver IC using two‐stage DAC with a capacitor array for active matrix flat‐panel displays

A small‐area and low‐power data driver integrated circuit (IC) using a two‐stage digital‐to‐analog converter (DAC) with a capacitor array is proposed for active matrix flat‐panel displays. The proposed data driver IC employs a capacitor array in the two‐stage DAC so as to reduce the DAC area and eliminate the need for a resistor string, which has high‐power consumption. To verify the proposed two‐stage DAC, a 20‐channel data driver IC with the proposed 10‐bit two‐stage DAC was fabricated using a 0.18‐μm complementary metal–oxide–semiconductor process with 1.8 and 6 V complementary metal–oxide–semiconductor devices. The proposed 10‐bit two‐stage DAC occupies only 43.8% of the area of a conventional 10‐bit two‐stage DAC. The measurement results show that the differential nonlinearity and integral nonlinearity are +0.58/?0.52 least significant bit and +0.62/?0.59 least significant bit, respectively. The measured interchannel deviation of the voltage outputs is 8.8 mV, and the measured power consumption of the 20‐channel data driver IC is reduced to 7.1 mW, which is less than half of the power consumed by the conventional one.     

Gabor-based kernel PCA with fractional power polynomial models for face recognition

This paper presents a novel Gabor-based kernel Principal Component Analysis (PCA) method by integrating the Gabor wavelet representation of face images and the kernel PCA method for face recognition. Gabor wavelets first derive desirable facial features characterized by spatial frequency, spatial locality, and orientation selectivity to cope with the variations due to illumination and facial expression changes. The kernel PCA method is then extended to include fractional power polynomial models for enhanced face recognition performance. A fractional power polynomial, however, does not necessarily define a kernel function, as it might not define a positive semidefinite Gram matrix. Note that the sigmoid kernels, one of the three classes of widely used kernel functions (polynomial kernels, Gaussian kernels, and sigmoid kernels), do not actually define a positive semidefinite Gram matrix either. Nevertheless, the sigmoid kernels have been successfully used in practice, such as in building support vector machines. In order to derive real kernel PCA features, we apply only those kernel PCA eigenvectors that are associated with positive eigenvalues. The feasibility of the Gabor-based kernel PCA method with fractional power polynomial models has been successfully tested on both frontal and pose-angled face recognition, using two data sets from the FERET database and the CMU PIE database, respectively. The FERET data set contains 600 frontal face images of 200 subjects, while the PIE data set consists of 680 images across five poses (left and right profiles, left and right half profiles, and frontal view) with two different facial expressions (neutral and smiling) of 68 subjects. The effectiveness of the Gabor-based kernel PCA method with fractional power polynomial models is shown in terms of both absolute performance indices and comparative performance against the PCA method, the kernel PCA method with polynomial kernels, the kernel PCA method with fractional power polynomial models, the Gabor wavelet-based PCA method, and the Gabor wavelet-based kernel PCA method with polynomial kernels.     

Doherty功放的数字预失真技术研究

通信系统中功率放大器（PA）的效率和线性度影响着整个系统的性能,而Doherty技术是提高效率的一种有效方式,但在提高效率的同时,它的线性度也会变差。数字预失真（DPD）是一种最具有前景的线性化技术,近年来各种模型被不断提出。通过在一种合适阶数、记忆深度的记忆多项式DPD中采用新的RLS与LMS混合算法,实现Doherty功放（DPA）快速、高效的线性化。仿真结果表明所提算法能够快速收敛,对系统的非线性和记忆效应有明显改善。     

Digital time‐modulation pixel memory circuit in LTPS technology

Abstract— A digital time‐modulation pixel memory circuit on glass substrate has been designed and verified for a 3‐μm low‐temperature polysilicon (LTPS) technology. From the experimental results, the proposed circuit can generate 4‐bit digital codes and the corresponding inversion data with a time‐modulation technique. While the liquid‐crystal‐display (LCD) panel operates in the still mode, which means the same image is displayed on the panel, a data driver for an LCD panel is not required to provide the image data of the frame by the proposed pixel memory circuit. This pixel memory circuit can store the frame data and generate its corresponding inversion data to refresh a static image without activating the data driver circuit. Therefore, the power consumption of a data driver can be reduced in the LCD panel.     

Digital techniques to mitigate feedback impairment and noise of look‐up table digital predistortion

In this article, some new effects of feedback impairment and noise on look‐up table (LUT) digital predistortion (DPD) are presented. Several digital techniques are proposed to mitigate these effects. A smoothing filter (SMF) for LUTs is used to eliminate fluctuations of the transfer function of the overall DPD amplification system. By combining SMF method with iterative average (IA) method, the LUTs iterative process becomes stable and well converged. A postcompensator is established according to the proposed two‐box model for feedback impairment. For the demonstration, both simulation and experiments are carried out based on a Hammerstein‐type PA. Simulation results give some preliminary cognition of these new effects and the effectiveness of proposed techniques. Experimental tests are performed on an S‐band amplifier excited with single‐carrier WCDMA signal. The adjacent channel power ratio (ACPR) at 5‐MHz offset is ?48 dBc after DPD with SMF method and postcompensator. A total of 8 dB extra improvement of ACPR is obtained compared with that with neither SMF nor postcompensator. The result clearly shows that the proposed digital techniques are qualified for LUT DPD system, especially when it suffers significant feedback impairment and noise. © 2011 Wiley Periodicals, Inc. Int J RF and Microwave CAE, 2011.     

压缩感知框架下宽带功放预失真模型

射频功放的非线性特性是一个重要的研究方向,针对预失真系统采样率过高的问题,提出一种新的宽带功放预失真模型,即在反馈回路采用基于正弦调频(SFM)信号的调制宽带解调(MWC)对信号进行采样,再用变步长广义自适应匹配追踪(VS-GSAMP)算法对信号进行重构,降低反馈回路采样速率,提升线性化效果。实验结果表明,在提高信号重构精度的同时,NSME(normalized mean squared error)显示较MP、GMP模型提升了2~3 d B,ACPR(adjacent channel power radio)约改善了21 d B,该方法能够使系统在较低的采样率下获得良好的线性性能。     

Hybrid weighted bit flipping low density parity check decoding

Low density parity check codes (LDPC) exhibit near capacity performance in terms of error correction. Large hardware costs, limited flexibility in terms of code length/code rate and considerable power consumption limit the use of belief-propagation algorithm based LDPC decoders in area and energy sensitive mobile environment. Serial bit flipping algorithms offer a trade-off between resource utilization and error correction performance at the expense of increased number of decoding iterations required for convergence. Parallel weighted bit flipping decoding and its variants aim at reducing the decoding iteration and time by flipping the potential erroneous bits in parallel. However, in most of the existing parallel decoding methods, the flipping threshold requires complex computations.In this paper, Hybrid Weighted Bit Flipping (HWBF) decoding is proposed to allow multiple bit flipping in each decoding iteration. To compute the number of bits that can be flipped in parallel, a criterion for determining the relationship between the erroneous bits in received code word is proposed. Using the proposed relation the proposed scheme can detect and correct a maximum of 3 erreneous hard decision bits in an iteration. The simulation results show that as compared to existing serial bit flipping decoding methods, the number of iterations required for convergence is reduced by 45% and the decoding time is reduced by 40%, by the use of proposed HWBF decoding. As compared to existing parallel bit flipping decoding methods, the proposed HWBF decoding can achieve similar bit error rate (BER) with same number of iterations and lesser computational complexity. Due to reduced number of decoding iterations, less computational complexity and reduced decoding time, the proposed HWBF decoding can be useful in energy sensitive mobile platforms.     

稀疏的归一化功放模型及预失真应用*

针对射频功放的非线性特性进行了研究,提出一种新的稀疏化的Volterra级数模型。该模型基于压缩感知算法,将稀疏系统的辨识等效为信号的重构问题,利用正则正交匹配（ROMP）算法对核系数进行稀疏化并选择出活跃的核系数。将提出的模型与记忆多项式（MP）模型、通用记忆多项式（GMP）模型进行比较,较MP模型的建模精度提升10.7dB,模型系数减少25%,较GMP模型的建模精度提升3.9dB,但模型系数减少84.58%。仿真结果表明：提出的方法实现良好的预失真线性化性能,极大地降低模型系数,优于传统的功放行为模型。由此验证对功放的线性化技术发展具有参考价值。     

Behavioral modeling for concurrent dual‐band power amplifiers using 2D hammerstein/wiener models

Behavioral modeling for the concurrent dual‐band power amplifier (PA) is a critical problem in practical applications. The nonlinear distortion in the concurrent dual‐band PA is quite different from that in the conventional single‐band PA. This article analyzes the nonlinearities in the concurrent dual‐band PA and reveals that both input signals in the dual bands are important for the behavioral modeling. The 2D Hammerstein model and 2D Wiener model are proposed for the first time for the concurrent dual‐band PA. They are extended versions of conventional Hammerstein and Wiener structures used in the single‐band PA by including the cross‐band intermodulation in the static nonlinearity block. The proposed 2D models require much less coefficients than the original work of the 2D‐DPD model. Experiments were carried out for an 880 MHz/1960 MHz concurrent dual‐band Doherty PA to demonstrate the effectiveness of the proposed models. The results clearly show that less than ?40 dB normalized mean square errors (NMSEs) are obtained in the dual bands in the behavioral modeling. © 2012 Wiley Periodicals, Inc. Int J RF and Microwave CAE 23: 646–654, 2013.     

Consecutive multiline addressing: A scheme for addressing PMOLEDs

Abstract— Consecutive multiline addressing (CMLA) has been developed to increase a PMOLED display's lifetime, resolution, and power efficiency. Mathematically, it decomposes an image matrix into a set of multiline matrices and a residual single‐line matrix. The decomposition is lossless and implemented by a combinatorial algorithm allowing small chip size for the logic and high processing speed, e.g., for video applications. The additional memory needed for CMLA is just a fraction of the graphic data memory (GDRAM). The printed‐circuit‐board (PCB) prototype with a field programmable gate array (FPGA) proves that the CMLA produces images of the same visual quality as the conventional single‐line addressing (SLA), while the power efficiency is substantially higher.