Design of a 10 W high‐efficiency balanced power amplifier using a combination of load‐pull and load‐line methods for ISM band

In this article, a 10 W power amplifier has been designed and constructed at 2.4 GHz. The source and load‐pull impedance data published by the manufacturer at a nearby frequency of 2.5 GHz have been adopted to power match the transistor at the intended design frequency. For this purpose, the linear model of the GaN transistor has been derived from the S‐parameter data. The load‐line at the dependent current source plane and the impedance at the intrinsic gate‐source capacitance have been simulated in the presence of the source and load‐pull impedances at 2.5 GHz. The extracted impedances have been retained in the design of the power amplifier at 2.4 GHz. In a novel approach, the input and output matching circuits interacted with the linear model of the transistor to provide the same load‐line conditions at the virtual drain plane and the intrinsic gate‐source capacitance plane. In contrast to conventional load‐pull methods that give no information about the harmonic terminations, harmonic terminations can be easily controlled in this method. The insight into the transistor linear model allows the harmonic terminations at the virtual drain plane to be set to low values for proper class‐B operation.     

An improved empirical large‐signal model for the GaAs‐ and GaN‐based HEMTs

A complete empirical large‐signal model for the GaAs‐ and GaN‐based HEMTs is presented. Three generalized drain current I–V models characterized by the multi‐bias Pulsed I–V measurements are presented along with their dependence on temperature and quiescent bias state. The new I–V equations dedicated for different modeling cases are kept accurate enough to the higher‐order derivatives of drain‐current. Besides, an improved charge‐conservative gate charge Q–V formulation is proposed to extract and model the nonlinear gate capacitances. The composite nonlinear model is shown to accurately predict the S‐parameters, large‐signal power performances as well as the two‐tone intermodulation distortion products for various types of GaAs and GaN HEMTs. © 2011 Wiley Periodicals, Inc. Int J RF and Microwave CAE , 2011.     

The AB‐C Doherty power amplifier. Part II: Validation

In part I, the complete theoretical (and nonlinear) analysis of a Doherty amplifier employing a Class AB bias condition for the Main Amplifier and a Class C one for the Auxiliary device has been presented. In this article, the experimental validation of the proposed theory is presented, describing the step‐by‐step procedure to be adopted when designing an AB‐C Doherty. The amplifier was realized at 2.14 GHz in hybrid form using two (0.5 μm, 1 mm gate periphery) GaN HEMTs. © 2008 Wiley Periodicals, Inc. Int J RF and Microwave CAE, 2009.     

The AB‐C Doherty power amplifier. Part I: Theory

In this article, the complete theoretical analysis of a Doherty amplifier employing a Class AB bias condition for the Main and a Class C one for the Auxiliary devices, respectively, is presented. Starting from the simplified model of an active device, the analysis of the AB‐C Doherty behavior is carried out as a function of the input signal. In particular, the proposed approach is based on the analysis of the output drain current waveforms generated by the two active devices, while assuming a Tuned Load configuration (i.e., short circuit condition) for higher harmonic terminations. A closed form formulation is derived in order to directly design an AB‐C Doherty amplifier, while fully understanding the basis of its physical behavior. Finally, which Doherty parameters can be chosen by the designer or have to be implicitly fixed are discussed and clarified. © 2008 Wiley Periodicals, Inc. Int J RF and Microwave CAE, 2009.     

Modeling power and intermodulation behavior of microwave transistors with unified small‐signal/large‐signal neural network models

This article presents a detailed procedure to learn a nonlinear model and its derivatives to as many orders as desired with multilayer perceptron (MLP) neural networks. A modular neural network modeling a nonlinear function and its derivatives is introduced. The method has been used for the extraction of the large‐signal model of a power MESFET device, modeling the nonlinear relationship of drain‐source current I_ds as well as gate and drain charge Q_g and Q_d with respect to intrinsic voltages V_gs and V_ds over the whole operational bias region. The neural models have been implemented into a user‐defined nonlinear model of a commercial microwave simulator to predict output power performance as well as intermodulation distortion. The accuracy of the device model is verified by harmonic load‐pull measurements. This neural network approach has demonstrated to predict nonlinear behavior with enough accuracy even if based only on first‐order derivative information. © 2003 Wiley Periodicals, Inc. Int J RF and Microwave CAE 13: 276–284, 2003.     

Genetic algorithm‐based neural‐network modeling approach applied to AlGaN/GaN devices

An accurate equivalent circuit large‐signal model (ECLSM) for AlGaN‐GaN high electron mobility transistor (HEMT) is presented. The model is derived from a distributed small‐signal model that efficiently describes the physics of the device. A genetic neural‐network‐based model for the gate and drain currents and charges is presented along with its parameters extraction procedure. This model is embedded in the ECLSM, which is then implemented in CAD software and validated by pulsed and continuous large‐signal measurements of on‐wafer 8 × 125‐μm GaN on SiC substrate HEMT. Pulsed IV simulations show that the model can efficiently describe the bias dependency of trapping and self‐heating effects. Single‐ and two‐tone simulation results show that the model can accurately predict the output power and its harmonics and the associated intermodulation distortion (IMD) under different input‐power and bias conditions. © 2012 Wiley Periodicals, Inc. Int J RF and Microwave CAE, 2013.     

Memory effects of all‐solution‐processed oxide thin‐film transistors using ZnO nanoparticles

Abstract— Non‐volatile memory effects of an all‐solution‐processed oxide thin‐film transistor (TFT) with ZnO nanoparticles (NPs) as the charge‐trapping layer are reported. The device was fabricated by using a soluble MgInZnO active channel on a ZrHfO^x gate dielectric. ZnO NPs were used as the charge‐trapping site at the gate‐insulator—channel interface, and Al was used for source and drain electrodes. Transfer characteristics of the device showed a large clockwise hysteresis, which can be used to demonstrate its memory function due to electron trapping in the ZnO NP charge‐trapping layer. This memory effect has the potential to be utilized as a memory application on displays and disposable electronics.     

Letter: Mechanisms for on/off currents in dual‐gate a‐Si:H thin‐film transistors using indium‐tin‐oxide top‐gate electrodes

Abstract— Two types of dual‐gate a‐Si:H TFTs were made with transparent indium‐tin‐oxide (ITO) top‐gate electrodes of different lengths to investigate the static characteristics of these devices. By changing the length of the ITO top gate, we found that the variations in the on‐currents of these dual‐gate TFTs with dual‐gate driving are due to the high resistance of the parasitic intrinsic a‐Si:H regions between the back electron channel and the source/drain contact. In the off‐state of the dual‐gate‐driven TFTs, the Poole‐Frenkel effect is also enhanced due to back‐channel hole accumulation in the vicinity of the source/drain contact. Furthermore, we observed for the first time that under illumination the dual‐gate‐driven a‐Si:H TFTs exhibit extremely low photo‐leakage currents, much lower than that of single‐gate‐driven TFTs in a certain range (reverse subthreshold region) of negative gate voltages. The high on/off current ratio under backside illumination makes dual‐gate TFTs suitable devices for use as switching elements in liquid‐crystal displays (LCDs) or for other applications.     

Energy awareness and uncertainty in microarchitecture-level design

The authors present microarchitecture-level statistical models for characterizing process and system parameter variability, concentrating on gate length and on-chip temperature variations. To assess the effect of microarchitecture decisions on these variations, and vice versa, they propose a joint performance, power, and variability metric that distinguishes among various design choices.     

2–6 GHz GaN distributed power amplifier MMIC with tapered gate‐series/drain‐shunt capacitors

In this article, using a 0.25 μm GaN HEMT process, we present a 2–6 GHz GaN two‐stage distributed power amplifier MMIC that utilizes tapered gate series capacitors and nonuniform drain transmission lines with tapered shunt capacitors to simultaneously obtain a linear gain enhancement and optimum load line for each transistor. By using well‐derived equations to provide each transistor with the optimum load impedance and to tune the phase delay between the input and output transmission lines, the nonuniform distributed power amplifier is designed for second‐stage amplification, and satisfactory performance is demonstrated. The phase balance and tapering of the gate series capacitors have a role in improving the linear gain of the two‐stage amplifier. The measured data show a linear gain of 22 ± 1 dB, an input/output return loss of more than 15 dB, saturated output power of 41.2–43.1 dBm under a continuous‐wave mode, and a power‐added efficiency of 18–22% from 2 to 6 GHz which are very competitive values compared with previous works. © 2016 Wiley Periodicals, Inc. Int J RF and Microwave CAE 26:456–465, 2016.     

High‐efficiency transmission‐line inverse Class F power amplifiers for 2‐GHz WCDMA systems

In this article, a novel load‐network solution to implement the transmission‐line inverse Class F power amplifiers for base station WCDMA applications is presented. The theoretical analysis is based on an analytical derivation of the optimum load‐network parameters to control the second and third harmonics at the device output, including the device output parasitic shunt capacitance and series inductance. The transmission‐line inverse Class F LDMOSFET and GaN HEMT power amplifiers using NXP BLF6G22LS‐75 and CREE CGH27060F devices, respectively, were designed and measured. The high‐performance results with the drain efficiency of 70.2% and power gain of 18.0 dB for a 60‐W LDMOSFET power amplifier and with the drain efficiency of 82.3% and power gain of 14.3 dB for a 50‐W GaN HEMT power amplifier were achieved at an operating frequency of 2.14 GHz. © 2011 Wiley Periodicals, Inc. Int J RF and Microwave CAE, 2011.     

Efficiency enhancement by employing the transistor nonlinear capacitors effects in a 6W hybrid X‐band Class‐J power amplifier

This article presents the design and fabrication of a 6 W X‐band hybrid Class‐J power amplifier (PA) based on a bare die GaN on SiC HEMT by accurate implementing the transistor nonlinear capacitor effects. The transistor input capacitor is precisely modelled and its nonlinearity effects on Class‐J performance is studied for the first time. It is shown that the harmonic generation property of the nonlinear input capacitor, especially at the second harmonic, can be of benefit to shape the transistor gate voltage as a quasi‐half wave sinusoidal waveform and consequently, it can improve the power added efficiency (PAE). A complete 3D thermal model of the power transistor is developed using ANSYS software and it is calibrated based on the thermal measured data. The PA achieves 13 dB average power gain over the frequency range of 8.8‐9.6 GHz. The drain efficiency and PAE are about 67% and 58% at 9.2 GHz, respectively.     

Modeling of threshold‐voltage‐shift dependency on drain bias in amorphous‐silicon thin‐film transistors in active‐matrix organic light‐emitting‐diode displays

Abstract— A theoretical model to interpret appearances of the threshold voltage shift in hydrogenated amorphous‐silicon (a‐Si:H) thin‐film transistors (TFTs) is developed to better understand the instability of a‐Si:H TFTs for the driving transistors in active‐matrix organic light‐emitting‐diode (AMOLED) displays. This model assumes that the defect creation at channel in a‐Si:H is proportional to the carrier concentration, leading to the defect density varying along the channel depending on the bias conditions. The model interprets a threshold‐voltage‐shift dependency on the drain‐stress bias. The model predicts the threshold voltage shift stressed under a given gate bias applying the drain saturation voltage is 66% of that with zero drain bias, and it even goes down to 50–60% of that when stressed by applying twice the drain saturation voltage.     

Enhancement of Johnson figure of merit in III‐V HEMT combined with discrete field plate and AlGaN blocking layer

The performance of AlGaN/GaN HEMT is enhanced by using discrete field plate (DFP) and AlGaN blocking layer. The AlGaN blocking layer provides an excellent confinement of electrons toward the GaN channel, resulting very low subthreshold drain current of 10^?8 A/mm. It reveals very high off state breakdown voltage (BV) of 342 V for 250 nm gate technology HEMT. The breakdown voltage achieved for the proposed HEMT is 23% higher when compared to the breakdown voltage of conventional field plate HEMT device. In addition, the DFP reduces the gate capacitance (C_G) from 12.04 × 10^?13 to 10.48 × 10^?13 F/mm. Furthermore, the drain current and transconductance (g_m) reported for the proposed HEMT device are 0.82 A/mm and 314 mS/mm, respectively. Besides, the cut‐off frequency (f_T) exhibited for the proposed HEMT is 28 GHz. Moreover, the proposed HEMT records the highest Johnson figure of merit (JFOM) of 9.57 THz‐V for 250 nm gate technology without incorporating T‐gate.     

Yield sensitivity study of A1GaAs/GaAs high electron mobility transistor

A simple graphical statistical method is presented and is used to study the statistical sensitivity of the AlGaAs/GaAs High Electron Mobility Transistor (HEMT) small-signal performances to physical model parameters, Using an analytical model and applying numerical techniques, the small-signal performances, transconductance, gate-to-source capacitance, current gain cut-off frequency, and the optimum cut-off frequency are calculated for four different HEMTs. These are then used as the device specifications in the Monte Carlo-based sensitivity analysis. Based on the model, a device simulator is developed in which the gate length, the gate width, and the carrier mobility are statistically varied simultaneously about their nominal values. The yield factor histograms for each small-signal parameter and its sensitivity to the process parameter variations are determined. In this work, we report that the current gain cut-off frequency increases as the carrier mobility increases, but it is almost independent of the gate width. We observe that the gate-to-source capacitance is independent of the carrier mobility, but it is strongly dependent on the transistor dimension. All the performance yields analyzed here go down as the gate length increases.     

Effect of source/drain overlap region on device performance in a‐IGZO thin‐film transistors

Abstract— In this paper, the effect of source/drain overlap length on the amorphous indium gallium zinc oxide (a‐IGZO) TFT performance has been investigated. Results of this paper show that as source/drain overlap length decreases to a negative value forming S/D offset, the threshold voltage and S parameters of a‐IGZO TFTs increased and the field‐effect mobility decreased. The V_T variation increases sharply as the channel length decreases because of the large resistance R_offset when it is formed at a‐IGZO source/drain. In the experiment, R_offset of each 1 μm, evaluated from the transfer length method (TLM), shows approximately 54–66 kΩ. This means thatthe source/drain overlap length is a very important control parameter for uniform device characteristics of a‐IGZO TFTs.     

On invariant sets and closed‐loop boundedness of Lure‐type nonlinear systems by LPV‐embedding

We address the problem of achieving trajectory boundedness and computing ultimate bounds and invariant sets for Lure‐type nonlinear systems with a sector‐bounded nonlinearity. Our first contribution is to compare two systematic methods to compute invariant sets for Lure systems. In the first method, a linear‐like bound is considered for the nonlinearity, and this bound is used to compute an invariant set by regarding the nonlinear system as a linear system with a nonlinear perturbation. In the second method, the sector‐bounded nonlinearity is treated as a time‐varying parameterised linear function with bounded parameter variations, and then invariant sets are computed by embedding the nonlinear system into a convex polytopic linear parameter varying (LPV) system. We show that under some conditions on the system matrices, these approaches give identical invariant sets, the LPV‐embedding method being less conservative in the general case. The second contribution of the paper is to characterise a class of Lure systems, for which an appropriately designed linear state feedback achieves bounded trajectories of the closed‐loop nonlinear system and allows for the computation of an invariant set via a simple, closed‐form expression. The third contribution is to show that, for disturbances that are ‘aligned’ with the control input, arbitrarily small ultimate bounds on the system states can be achieved by assigning the eigenvalues of the linear part of the system with ‘large enough’ negative real part. We illustrate the results via examples of a pendulum system, a Josephson junction circuit and the well‐known Chua circuit. Copyright © 2015 John Wiley & Sons, Ltd.     

The influence of dependence of HEMT’s model parameters on gate and drain voltages on upper boundary of LNA’s linearity

On the basis of numerical model the parameters of high electron mobility transistors (HEMT’s) as a function of gate and drain voltages are obtained. The simulation of nonlinear properties of low noise amplifier cascade with HEMT for various modes of its operation has shown that the account of its dependence simultaneously on both the voltages allows to approach the results of calculation to experimental data.     

A new procedure for nonlinear statistical model extraction of GaAs FET‐integrated circuits

A new statistical nonlinear model of GaAs FET MMICs which allows the representation of distance‐dependent technological parameter variations by means of equivalent circuit parameters, and an automatic extraction procedure, are presented. The capability to reproduce statistical distribution has been successfully checked on S parameters at different distances in the 1–50 GHz frequency range. © 2003 Wiley Periodicals, Inc. Int J RF and Microwave CAE 13, 348–356, 2003.