Modeling for reduced gate capacitance of nanoscale MOSFETs

As gate oxides become thinner, in conjunction with scaling of MOS technologies, a discrepancy arises between the gate oxide capacitance and the total gate capacitance, due to the increasing importance of the carrier distributions in the polysilicon electrodes. For the first time, based on least-squares curve fit, we quantitatively explore the impact of quantum mechanics effects in polysilicon gate region on gate capacitance. Comparing the theoretical curves with an extensive set of simulation ones has validated this model.     

Analysis of the gate capacitance measurement technique and its application for the evaluation of hot-carrier degradation in submicrometer MOSFETs

The use of gate-to-drain capacitance (C_gd) measurement as a tool to characterize hot-carrier-induced charge centers in submicron n- and p-MOSFET’s has been reviewed and demonstrated. By analyzing the change in C_gd measured at room and cryogenic temperature before and after high gate-to-drain transverse field (high field) and maximum substrate current (I_bmax) stress, it is concluded that the degradation was found to be mostly due to trapping of majority carriers and generation of interface states. These interface states were found to be acceptor states at top half of band gap for n-MOSFETs and donor states at bottom half of band gap for p-MOSFETs. In general, hot electrons are more likely to be trapped in gate oxide as compared to hot holes while the presence of hot holes generates more interface states. Also, we have demonstrated a new method for extracting the spatial distribution of oxide trapped charge, Q_ot, through gate-to-substrate capacitance (C_gb) measurement. This method is simple to implement and does not require additional information from simulation or detailed knowledge of the device’s structure.     

On the gate capacitance limits of nanoscale DG and FD SOI MOSFETs

An analytical total gate capacitance C/sub G/ model for symmetric double-gate (DG) and fully depleted silicon-on-insulator (FD/SOI) MOSFETs of arbitrary Si film is developed and demonstrated. The model accounts for the effects of carrier-energy quantization and inversion-layer screening and is verified via self-consistent numerical solutions of the Poisson and Schro/spl uml/dinger equations. Results provide good physical insight regarding C/sub G/ degradation due to quantization and screening governed by device structure and/or transverse electric field for nanoscale DG and FD/SOI MOSFETs. Two limits of C/sub G/ at ON-state are then derived when the silicon film t/sub Si/ approaches zero and infinity. The effect of inversion-layer screening on C/sub G/, which is significant for ultrathin Si-film DG MOSFETs, is quantitatively defined for the first time. The insightful results show that the two-dimensional screening length for DG MOSFETs is independent of the doping density and much shorter than the bulk Debye length as a result of strong structural confinement.     

Fowler-Nordheim stress degradation in gate oxide: results fromgate-to-drain capacitance and charge pumping current

The buildup of positive oxide charge and interface trap charge, due to Fowler-Nordheim stress, is observed in the gate-drain overlap region of the MOSFET. Results from gate-to-drain capacitance and charge pumping current show a steady increase in positive charge near the anode interface. Interface trap generation becomes significant when injected electron fluence exceeds ~10¹⁴ cm^-2, and dominates net charge creation at higher fluence     

Dose rate dependence of the back gate degradation in thin gate oxide PD-SOI MOSFETs by 2-MeV electron irradiation

The degradation of the electrical properties of thin gate oxide PD-SOI n-MOSFETs by 2-MeV electrons at different dose rates is presented. The degradation of the back channel and its dependence on dose rate are clarified. The characteristics of the PD-SOI MOSFETs are degraded, and the degradation becomes higher for a low dose rate. The magnitude of the hysteresis characteristics in the drain current becomes smaller after irradiation, and the degradation for a low dose rate is higher than for a high dose rate. It is found that the degradation of the front characteristics is related to the back gate degradation by the coupling effect.     

Modeling the Well-Edge Proximity Effect in Highly Scaled MOSFETs

The well-edge proximity effect caused by ion scattering during implantation in highly scaled CMOS technology is explored from a physics and process perspective. Technology computer-aided design (TCAD) simulations together with silicon wafer experiments have been conducted to investigate the impact of this effect. The ion scattering model and TCAD simulations provided a physical understanding of how the internal changes of the MOSFETs are formed. A new compact model for SPICE is proposed using physics-based understanding and has been calibrated using experimental silicon test sets     

Scaled silicon MOSFET's: universal mobility behavior

We use a fully quantum-mechanical model to study the inversion layer mobility in a silicon MOS structure. The importance of depletion charge and surface-roughness scattering on the effective electron mobility is examined. The magnitude of the mobility is found to be considerably reduced by both depletion charge and interface-roughness scattering. The appropriate weighting coefficients a and b for the inversion and depletion charge densities in the definition of the effective electric field, which eliminate the doping dependence of the effective electron mobility, are also calculated. These are found to differ from the commonly used values of 0.5 and 1. In addition, the weighting coefficient for the depletion charge density is found to be significantly influenced by the actual shape of the doping profile and can be either >1 or <1     

Characterization of P-channel power trench MOSFETs with polycrystalline silicon germanium gate electrode for faster switching

Electrical switching characteristics using polycrystalline silicon–germanium (poly-Si_l?xGe_x) gate for P-channel power trench MOSFETs was investigated. Switching time reduction of over 22% was observed when the boron-doped poly-Si gate was replaced with a similarly boron-doped poly-SiGe gate on the P-channel power MOSFETs. The fall time (T_f) on MOSFETs with poly-SiGe gate, was found to be ～11 ns lesser than the poly-Si gate MOSFET which is ～60% improvement in switching performance. However, all the switching improvement was observed during the fall times (T_f). The reason could be the higher series resistance in the switching test circuit masking any reduction in the rise times (T_r). Faster switching is achieved due to a lower gate resistance (R_g) offered by the poly-SiGe gate electrode as compared to poly-silicon (pSi) material. The pSi gate resistance was found to be 6.25 Ω compared to 3.75 Ω on the poly-SiGe gate measured on the same device. Lower gate resistance (R_g) also means less power is lost during switching thereby less heat is generated in the device. A very uniform boron doping profile was achieved with-in the pSiGe gate electrode, which is critical for uniform die turn on and better thermal response for the power trench MOSFET. pSiGe thin film optimization, properties and device characteristics are discussed in details in the following sections.     

Characterization of double gate MOSFETs fabricated by a simple method on a recrystallized silicon film

A simple process to fabricate double gate SOI MOSFET is proposed. The new device structure utilizes the bulk diffusion layer as the bottom gate. The active silicon film is formed by recrystallized amorphous silicon film using metal-induced-lateral-crystallization (MILC). While the active silicon film is not truly single crystal, the material and device characteristics show that the film is equivalent to single crystal SOI film with high defect density, like SOI wafers produced in early days. The fabricated double gate MOSFETs are characterized, which demonstrate excellent device characteristics with higher current drive and stronger immunity to short channel effects compared to the single gate devices.     

Metal gate work function engineering on gate leakage of MOSFETs

We present a systematic study of tunneling leakage current in metal gate MOSFETs and how it is affected by the work function of the metal gate electrodes. Physical models used for simulations were corroborated by experimental results from SiO/sub 2/ and HfO/sub 2/ gate dielectrics with TaN electrodes. In bulk CMOS results show that, at the same capacitance equivalent oxide thickness (CET) at inversion, replacing a poly-Si gate by metal reduces the gate leakage appreciably by one to two orders of magnitude due to the elimination of polysilicon gate depletion. It is also found that the work function /spl Phi//sub B/ of a metal gate affects tunneling characteristics in MOSFETs. It is particularly significant when the transistor is biased at accumulation. Specifically, the increase of /spl Phi//sub B/ reduces the gate-to-channel tunneling in off-biased n-FET and the use of a metal gate with midgap /spl Phi//sub B/ results in a significant reduction of gate to source/drain extension (SDE) tunneling in both n- and p-FETs. Compared to bulk FET, double gate (DG) FET has much lower off-state leakage due to the smaller gate to SDE tunneling. This reduction in off-state leakage can be as much as three orders of magnitude when high-/spl kappa/ gate dielectric is used. Finally, the benefits of employing metal gate DG structure in future CMOS scaling are discussed.     

Electrical method of measuring physical thickness and nitrogen concentration of silicon oxynitride gate dielectric for MOSFETs

This paper proposes an electrical method of measuring the physical thickness T_ox and the nitrogen concentration α_N of the silicon oxynitride (SiON) gate dielectric for MOSFETs. The proposed method uses the facts that the gate dielectric breakdown field strength E_BD depends on α_N for a given T_ox and the direct tunneling (DT) current depends strongly on T_ox. Gate current I_g versus gate voltage V_g (I_g-V_g) curves at a given α_N were calculated for different T_oxs using the DT model, and measurements were compared to the curves to obtain T_ox. The α_N was obtained by comparing the measured E_BD at a given T_ox with the theoretical E_BD for a SiON gate dielectric. These two steps were iterated until the convergence error of α_N was less than 1%. The I_g-V_g curves calculated using the extracted T_oxs and α_Ns agreed very well with measurements when V_g was less than the gate breakdown voltage. The difference between the equivalent oxide thickness (EOT) measured using the C-V method and the EOT calculated using the extracted T_ox and α_N was less than 7%, demonstrating that the proposed method can accurately determine T_ox and α_N of an ultra-thin SiON gate dielectric from only the measured I_g-V_g curve of the MOSFET.     

Increase of gate capacitance in DMOST

The gate capacitance of an n-channel DMOST at nonzero drain current biasing exceeds that of a similar conventional MOST and may even exceed the gate oxide capacitance. This effect is due to the behavior of mobile electrons in the device. The fundamental operation of the DMOST is understood through the use of a two-dimensional computer analysis. Based on this insight, the increase of the gate capacitance is clarified in terms of the electron velocity between the source and the drain. Gate capacitance measurements are carried out on experimental DMOST's, which are made on a p^-background as well as on an n^-epitaxial layer. The measuredC-Vcurves qualitatively confirm the theory on the increase of the gate capacitance in its dependence on the background of the DMOST and the applied dc voltages.     

Nanoscale silicon MOSFETs: A theoretical study

We have carried out extensive numerical modeling of double-gate, nanoscale silicon n-metal oxide semiconductor field effect transistors (MOSFETs) with ultrathin, intrinsic channels connecting bulk, highly doped electrodes. Our model takes into account two most important factors limiting the device performance as the gate length is reduced, namely the gate field screening by source and drain, and quantum mechanical tunneling from source to drain. The results show that the devices with small but plausible values of gate oxide thickness t/sub ox/ and channel thickness t (both of the order of 2 nm) may retain high ON current, good saturation and acceptable subthreshold slope even if the gate length L is as small as /spl sim/5 nm, with voltage gain above unity all the way down to L/spl ap/2 nm (channel length L/sub c/=L+2t/sub ox//spl ap/5 nm). However, as soon as L is decreased below /spl sim/10 nm, specific power (per unit channel width) starts to grow rapidly. Even more importantly, threshold voltage becomes an extremely sensitive function of L,t, and t/sub ox/, creating serious problems for reproducible device fabrication.     

Modeling the gate more accurately for power MOSFETs

In recent years, power MOSFET devices have replaced the bipolar transistor. However, the power MOSFET is a fairly new device and current modeling techniques have not produced an accurate simulation of the gate to source. The method presented here generates a more accurate model of the transient behavior and gate to source characteristics of the power MOSFET. The results provide a better correlation between the MOSFET model and the actual device     

A method to extract mobility degradation and total seriesresistance of fully-depleted SOI MOSFETs

Free-carrier mobility degradation in the channel and drain/source series resistance are two important parameters limiting the performance of MOS devices. In this paper, we present a method to extract these parameters from the drain current versus gate voltage characteristics of fully-depleted (FD) SOI MOSFETs operating in the saturation region. This method is developed based on an integration function which reduces errors associated with the extraction procedure and on the DC characteristics of MOS devices having several different channel lengths. Simulation results and measured data of FD SOI MOSFETs are used to test and verify the method developed     

Analysis of gate shot noise in MOSFETs with ultrathin gate oxides

The impact of gate shot noise associated with gate leakage current in MOSFETs is studied by means of analytical models and numerical device simulation. The effects of shot noise on the main two-port noise parameters (minimum noise figure, equivalent noise resistance, and optimum source admittance) and their dependence on oxide thickness and on the level of tunneling leakage current are analyzed.     

Induced gate noise in MOSFETs revisited: The submicron case

At high frequencies the gate admittance of the MOSFET contains a conductive component because of the capacitive coupling of the gate electrode to the channel. The thermal noise fluctuations, originating in the channel, induce a gate current outwards from the gate electrode. Based on a proved two-region model for the drain current noise of a sub-micron MOSFET, it is shown that the calculated gate-noise current increases significantly, compared to that predicted by a classical model, valid for long channel devices.     

Memory characteristics of MOSFETs with densely stacked silicon nanocrystal Layers in the gate oxide synthesized by low-energy ion beam

Densely stacked silicon nanocrystal layers embedded in the gate oxide of MOSFETs are synthesized with Si ion implantation into an SiO/sub 2/ layer at an implantation energy of 2 keV. In this letter, the memory characteristics of MOSFETs with 7-nm tunnel oxide and 20-nm control oxide at various temperatures have been investigated. A threshold voltage window of /spl sim/ 0.5 V is achieved under write/erase (W/E) voltages of +12 V/-12 V for 1 ms. The devices exhibit good endurance up to 10/sup 5/ W/E cycles even at a high operation temperature of 150/spl deg/C. They also have good retention characteristics with an extrapolated ten-year memory window of /spl sim/ 0.3 V at 100/spl deg/C.     

Hot-electron degradation of n-channel polysilicon MOSFETs

The stability of the hydrogen passivation in hydrogenated n-channel polysilicon MOSFETs has been studied under thermal stress and hot-electron stress at elevated temperatures. Although the hydrogen passivation is stable at 150°C, channel hot-electron stress at high temperatures appears to create additional grain boundary traps, presumably by breaking the Si-H bonds at the grain boundaries. This mechanism is in addition to the creation of acceptor-type fast interface states that occur in bulk MOSFETs