纠错码在容错存储器设计中的应用

本文分析了存储器产生错误的原因，提出了提高其可靠性的途径，给出了一套常用数字系统中存储器容错的纠错方案，最终通过验证电路说明其可靠性。     

下一代网络核心业务平台的可靠性分析

基于随机Petri网,提出了一种计算NGN核心业务平台可靠性的方法。对双机热备份容错系统和N 1互备份容错系统的硬件环境分别进行了可靠性建模与分析。提出了软件模块容错方法,并得到了该方法的软件模块可靠性表示方法;然后从软件模块的角度,对业务软件的可靠性进行了建模与分析。最后给出了一个实例,分析了NGN核心业务平台的硬件系统和业务软件是如何协作满足业务可靠性要求。     

嵌入式存储器容错方案可靠性评估

随着工艺节点的不断降低,存储器的软错误率呈指数趋势上升,容错技术已成为存储器设计中的重要环节。依据美国NASA Rosetta实验数据,对错误检纠错码(EDAC: Error Detection and Correction)和不同的在线刷新模式组成的多种容错方案进行可靠性建模与量化评估,提出了不同工艺节点下嵌入式存储器容错技术选择的判据方法。在地面单粒子模拟实验中进行验证,结果表明,该方法预测的失效率评估结果与实验测试结果的平均偏差约为10.3%。     

一种基于FPGA的高可用容错计算机的研究

针对传统容错嵌入式计算机故障检测方式较少,故障检测实时性不高,并且多余度结构中单个计算节点自身的可靠性较低的问题,给出了一种基于FPGA的高可用容错计算机设计思路。该计算机采用Lock Step技术作为处理器和存储器的故障检测方式,并应用TMR技术和局部重加载技术来提高接口电路FPGA设计的可靠性,具有丰富的故障监测方式,在多层级上增加了故障检测的覆盖率和实时性,显著提高了多余度结构中单个计算节点自身的可靠性,而且具备智能故障管理和故障自恢复能力。     

双机容错方案设计

介绍了双机容错的两种基本构架模式，双机互备援模式和双机热备份模式，利用马尔科夫模型对两者的可靠性进行了分析、比较；针对不同的用户给出了相应的双机容错设计方案，并对两种方案的优缺点进行了分析。     

一种具备故障自恢复能力的容错计算机架构设计

针对当前工程应用中容错嵌入式计算机较低的故障检测实时性,缺乏故障检测方式,且单个余度节点的可靠性较低的问题,设计出一种具备故障自恢复能力的容错计算机架构思路。该计算机架构应用局部重加载技术和TMR技术提高接口电路FPGA设计的可靠性,通过使用LockStep技术进行处理器和存储器的故障检测,在多层级上提高了故障检测的实时性和覆盖率,使故障监测方式更加丰富,具备故障自恢复能力和智能故障管理,较大程度提升了多余度结构中单个计算节点的可靠性。     

实时信号处理用VLSI的容错设计

随着微电子技术的发展,集成电路的芯片面积、集成度愈来愈大。芯片面积及集成度的增大带来了两个问题:一是成品率问题,二是可靠性问题。本文阐述了容错设计在实时信号处理用VLSI中的必要性、意义和研究内容;讨论了二维脉动阵列的容错并给出了算法;讨论了VLSI单元的完全自检查问题,并给出了实现电路;给出了VLSI的成品率与可靠性分析模型;最后分析了模拟结果并给出了结论。     

一种有效的电路容错结构及其成品率分析

本文提出了一种有效的电路容错结构,给出了一种重组算法.按照这种重组算法,对该结构的成品率进行了分析,并给出了其成品率的表达式.最后,通过电路设计和分析说明了该容错结构的有效性.     

自组织容错系统的设计及其可靠性分析

以生物神经系统的容错机理为基础,借鉴传统的人工神经网络的构建方式,结合电子电路的构造特点,提出了一种自组织神经网络模型,构建了自组织容错系统,并对构建的容错系统建立可靠性模型.通过可靠性分析发现,对于同功能不同拓扑的承载电路,当其占用神经元越少、在各层上分布越均匀时,其可靠性越高.     

光纤通道拓扑结构冗余方法研究

对于采用光纤通道(FC)互连的航空电子系统,在FC3种基本拓扑结构的基础上,分别给出了FC组合拓扑结构和由多个FC交换机组成的FC交换式网络的通信模型。针对航空电子系统的分布式网络模型,给出了基于任务的可靠性分析方法。根据航空电子系统容错功能和提高可靠性的需要,提出了FC的3种基本冗余结构:双环结构、双交换机结构和交换机仲裁环冗余结构,专门针对FC交换式网络提出了两种冗余结构:基本路径冗余和全网络冗余,专门针对FC组合拓扑结构提出了桥端口冗余结构;通过基于任务的可靠性分析,对各种容错拓扑结构进行了比较。对FC各种冗余拓扑结构的研究对于航空电子系统设计阶段的容错设计和冗余结构设计都将起到一定作用。     

一种神经网络控制器的容错设计与可靠性评估方法

本文以应用于电力控制系统中的人工神经网络快速汽门非线性适应控制器为例,详细论述了一种神经网络控制器的容错设计与可靠性评估方法,文中首先提出网络可靠性研究的重要性,以及本文所提出和容错设计与可靠性评估方法的通用性,然后详细介绍了一种神经网络快速汽门非线性适应控制器的设计结构和容错设计原理,最后根据设计的结果,得出了可靠性评估公式及其推广。     

A Hybrid Fault-Tolerant Architecture for Highly Reliable Processing Cores

Increasing vulnerability of transistors and interconnects due to scaling is continuously challenging the reliability of future microprocessors. Lifetime reliability is gaining attention over performance as a design factor even for lower-end commodity applications. In this work we present a low-power hybrid fault tolerant architecture for reliability improvement of pipelined microprocessors by protecting their combinational logic parts. The architecture can handle a broad spectrum of faults with little impact on performance by combining different types of redundancies. Moreover, it addresses the problem of error propagation in nonlinear pipelines and error detection in pipeline stages with memory interfaces. Our case-study implementation of a fault tolerant MIPS microprocessor highlights four main advantages of the proposed solution. It offers (i) 11.6 % power saving, (ii) improved transient error detection capability, (iii) lifetime reliability improvement, and (iv) more effective fault accumulation effect handling, in comparison with TMR architectures. We also present a gate-level fault-injection framework that offers high fidelity to model physical defects and transient faults.     

Maintainability Considerations in a Fault Tolerant/Faultproof Systems Design

The maintainability, reliability, and availability of a computer system are closely bonded to insure continuing service of a system. The ability of a system to tolerate failures or faults while operating is a principal requirement of a fault tolerant system. A fault tolerant system's design must incorporate considerations for maintenance and reliability in order to provide its ultimate requirement-available operation. These factors are considered in the design philosophy presented in this paper, identified as FAULTPROOF. FAULTPROOF design incorporates redundancy, reliability, maintainability, and adaptability to augment normally accepted fault tolerant design. The design approach described utilizes a hierarchical interconnection mechanism, Intelligent Networked Partitioning, to isolate faulted components.     

Fault‐tolerant spanners for ad hoc networks

Spanners for ad hoc networks provide several benefits such as low communication cost and resource consumption. These spanners need to be fault tolerant in resource‐constrained ad hoc networks. In this paper, we have proposed three spanners, called fault‐tolerant local Delaunay triangulation (FTLDel), fault‐tolerant relative neighborhood graph (FTRNG), and fault‐tolerant Gabriel graph (FTGG). The fault‐tolerant spanners provide reliability to the network by avoiding heavy packet loss and retaining useful geometric properties. The performance of fault‐tolerant spanners FTLDel, FTRNG, and FTGG are evaluated using the network simulator ns2.28. Copyright © 2011 John Wiley & Sons, Ltd.     

A Low-Cost Reliability vs. Cost Trade-Off Methodology to Selectively Harden Logic Circuits

Selecting the ideal trade-off between reliability and cost associated with a fault tolerant architecture generally involves an extensive design space exploration. Employing state-of-the-art reliability estimation methods makes this exploration un-scalable with the design complexity. In this paper we introduce a low-cost reliability analysis methodology that helps taking this key decision with less computational effort and orders of magnitude faster. Based on this methodology we also propose a selective hardening technique using a hybrid fault tolerant architecture that allows meeting the soft-error rate constraints within a given design cost-budget and vice versa. Our experimental validation shows that the methodology offers huge gain (1200 ×) in terms of computational effort in comparison with fault injection-based reliability estimation method and produces results within acceptable error limits.     

阵列结构矩阵乘法器的容错模块方法

<正> 一、引言 二维阵列结构是一种用途广泛的易于在VLSI中实现的结构。由于这种结构适合于开发并行运算,所以矩阵相乘、傅里叶变换、卷积等信号处理运算均可采用二维阵列结构。但这 种结构的弱点是,一旦阵列中的某一个单元出现故障,它将影响整个阵列的正常运行。为了提高二维阵列的可靠性,在这种结构中引入容错是必要的。 对于二维阵列的容错设计,目前有两类方法:一是结构冗余法,即提供冗余硬件;二是时间冗余法,即通过加倍处理时间实现容错。     

一种容错的空间计算机体系结构

当今空间计算机必须具有强实时下的高速处理能力和自主工作方式下的高可靠性，而对长寿命卫星而言，其可靠性要求使得任何一种模式的单机结构都难以胜任，于是各种各样的冗余方案溶进了星载计算机设计中，而有目的地识别和选择一种结构使其在有限资源的条件下最大限度地实现容错，同时又能达到所要求的性能，这正是本文所追求的目标，这里阐明的是一种模块化的容错结构，它使用简易的冗余内总线．将不同功能的冗余模块紧密地耦合在一起，从而使系统级的性能可以很方便的进行扩展，功能上可以灵活地实现集中或分布，从而达到了既适应空间计算和控制要求，又满足容错的性能要求的目标。     

Algorithm transformation methods to reduce the overhead of software-based fault tolerance techniques

This paper introduces a framework that tackles the costs in area and energy consumed by methodologies like spatial or temporal redundancy with a different approach: given an algorithm, we find a transformation in which part of the computation involved is transformed into memory accesses. The precomputed data stored in memory can be protected then by applying traditional and well established ECC algorithms to provide fault tolerant hardware designs. At the same time, the transformation increases the performance of the system by reducing its execution time, which is then used by customized software-based fault tolerant techniques to protect the system without any degradation when compared to its original form. Application of this technique to key algorithms in a MP3 player, combined with a fault injection campaign, show that this approach increases fault tolerance up to 92%, without any performance degradation.     

Simulated Fault Injection Using Simulator Modification Technique

In the current very deep submicron technology era, fault tolerant mechanisms perform an essential function to cope with the effects of soft errors. To evaluate the effectiveness of the fault tolerant mechanism, reliability engineers use simulated fault injections using either saboteur modules or mutants in the simulation model. However, the two methods suffer from both inefficiency in the simulation mechanism and difficulties with the experimental setups. To overcome these inefficiencies, we propose the Verilog‐based simulated fault injection (VFI) technique. VFI has the following advantages. First, modification of the design model is unnecessary. Second, the fault injection simulation procedure is simple and efficient. Third, various types of fault injection experiments can be performed. To evaluate the effectiveness of the proposed methodology, we developed a VFI environment using the ICARUS Verilog Simulator. From the experimental results, we were able to qualitatively evaluate the reliability of the target simulation models and to assess the effectiveness of the employed fault‐tolerance mechanisms.