A model relating wearout to breakdown in thin oxides

A model has been developed relating wearout to breakdown in thin oxides. Wearout has been described in terms of trap generation inside of the oxide during high voltage stressing prior to breakdown. Breakdown occurred locally when the local density of traps exceeded a critical value and the product of the electric field and the higher leakage currents through the traps exceeded a critical energy density. The measurement techniques needed for determining the density of high-voltage stress generated traps have been described along with the method for coupling the wearout measurements to breakdown distributions. The average trap density immediately prior to breakdown was measured to be of the order of low-10¹⁹/cm³ in 10 nm thick oxides fabricated on p-type substrates stressed with negative gate voltages. The model has been used to describe several effects observed during measurements of time-dependent-dielectric-breakdown distributions. The area dependence of breakdown distributions, the differences in the breakdown distributions during constant current and constant voltage stressing, and the multi-modal distributions often observed were simulated using the model. The model contained the provision for incorporation of weak spots in the oxide     

Metal-insulator-semiconductor structures of InSb/SiO2with very low interface trap density

MIS structures fabricated using InSb and silicon dioxide with an interface trap density as low as 4×10¹⁰ cm^-2 eV^-1 have been achieved. This is about one order of magnitude less than any other reported figure for the InSb MIS system. Both capacitance/voltage and conductance techniques have been employed to study the interface properties of InSb/SiO₂. A low state density of <10¹⁰ cm^-2 was observed and the dielectric breakdown field of the oxide was greater than 4 mV cm^-1      

Dependence of Fermi level positions at gate and substrate on thereliability of ultrathin MOS gate oxides

In this work, we demonstrate that the reliability of ultrathin (<10 nm) gate oxide in MOS devices depends on the Fermi level position at the gate, and not on its position at the substrate for constant current gate injection (υ_g^-). The oxide breakdown strength (Q_bd) is less for p⁺ poly-Si gate than for n⁺ poly-Si gate, but, it is independent of the substrate doping type. The degradation of an oxide is closely related to the electric field across it, which is influenced by the cathode Fermi level for constant current injection. P⁺ poly-Si gate has higher barrier height for tunneled electrons, therefore, the cathode electric field is higher to give the same injection current density. A higher electric field gives more high-energy electrons at the anode, and therefore the damage is more at the substrate interface. We have also shown that oxide degradation is independent of the testing methodology, i.e., constant current or constant voltage stress. It depends mainly on the electric field in the oxide     

4H-SiC TSOB结势垒肖特基二极管静态特性

为增强器件的反向耐压能力,降低器件的漏电功耗,采用Silvaco TCAD对沟槽底部具有SiO₂间隔的结势垒肖特基二极管(TSOB)的器件特性进行了仿真研究。通过优化参数来改善导通压降(V_F)-反向漏电流(I_R)和击穿电压的折衷关系。室温下,沟槽深度为2.2 μm时,器件的击穿电压达到1 610 V。正向导通压降为2.1 V,在V_F=3 V时正向电流密度为199 A/cm²。为进一步改善器件的反向阻断特性,在P型多晶硅掺杂的有源区生成一层SiO₂来优化漂移区电场分布,此时改善的器件结构在维持正向导通压降2.1 V的前提下,击穿电压达到1 821 V,增加了13%。在1 000 V反向偏置电压下,反向漏电流密度比普通结构降低了87%,有效降低了器件的漏电功耗。普通器件结构的开/关电流比为2.6×10³(1 V/-500 V),而改善的结构为1.3×10⁴(1 V/-500 V)。     

Hole injection SiO2 breakdown model for very low voltagelifetime extrapolation

In this paper, we present a model for silicon dioxide breakdown characterization, valid for a thickness range between 25 Å and 130 Å, which provides a method for predicting dielectric lifetime for reduced power supply voltages and aggressively scaled oxide thicknesses. This model, based on hole injection from the anode, accurately predicts Q_BD and t_BD behavior including a fluence in excess of 10⁷ C/cm² at an oxide voltage of 2.4 V for a 25 Å oxide. Moreover, this model is a refinement of and fully complementary with the well known 1/E model, while offering the ability to predict oxide reliability for low voltages     

Electrical conduction and dielectric breakdown in aluminum oxideinsulators on silicon

Leakage currents and dielectric breakdown were studied in MIS capacitors of metal-aluminum oxide-silicon. The aluminum oxide was produced by thermally oxidizing AlN at 800-1160°C under dry O₂ conditions. The AlN films were deposited by RF magnetron sputtering on p-type Si (100) substrates. Thermal oxidation produced Al ₂O₃ with a thickness and structure that depended on the process time and temperature. The MIS capacitors exhibited the charge regimes of accumulation, depletion, and inversion on the Si semiconductor surface. The best electrical properties were obtained when all of the AlN was fully oxidized to Al₂O₃ with no residual AlN. The MIS flatband voltage was near 0 V, the net oxide trapped charge density, Q_0x, was less than 10¹¹ cm ^-2, and the interface trap density, D_it, was less than 10¹¹ cm^-2 eV^-1, At an oxide electric field of 0.3 MV/cm, the leakage current density was less than 10^-7 A cm^-2, with a resistivity greater than 10 ¹² Ω-cm. The critical field for dielectric breakdown ranged from 4 to 5 MV/cm. The temperature dependence of the current versus electric field indicated that the conduction mechanism was Frenkel-Poole emission, which has the property that higher temperatures reduce the current. This may be important for the reliability of circuits operating under extreme conditions. The dielectric constant ranged from 3 to 9. The excellent electronic quality of aluminum oxide may be attractive for field effect transistor applications     

Thin oxide grown on heavily channel-implanted substrate by using a low temperature wafer loading and N2 pre-annealing process

In this paper, we present high integrity thin oxides grown on the channel implanted substrate (3 × 10¹⁷ cm⁻³) and heavily doped substrate (1 × 10²⁰ cm⁻³) by using a low-temperature wafer loading and N₂ pre-annealing process. The presented thin oxide grown on the channel implanted substrate exhibits a very low interface state density (1 × 10¹⁰ cm⁻² eV⁻¹) and a very high intrinsic dielectric breakdown field (15 MV/cm). It also shows a lower charge trapping rate and interface state generation rate than the conventional thermal oxide. For the thin oxide grown on the heavily-doped substrate by using the proposed recipe, the implantation-induced damage close to the silicon surface can be almost annealed out. The presented heavily-doped oxide shows much better dielectric characteristics, such as the dielectric breakdown field and the charge-to-breakdown, as compared to the conventional heavily-doped oxide.     

Stress voltage polarity dependence of thermally grown thin gateoxide wearout

Gate oxide wearout for thermally grown 57-190-A SiO₂ films in a polycrystalline silicon-SiO₂-Si structure prepared on n-type and p-type wafers was studied by examining time-dependent dielectric breakdown (TDDB) under 1-mA/cm² constant current with positive and negative voltages at 250°C. TDDB lifetimes for positive voltage stress are more than one order longer than those for negative voltage stress. TDDB lifetimes depend on oxide thickness, that is, they increase for positive voltage stress and decreases for negative voltage stress with decreasing oxide thickness. They also depend on whether the oxide films are prepared on n-type or p-type wafers. After the positive voltage TDDB stress, negative charges are predominantly produced in the oxide layer, and the electric field at the cathode in the oxide film slightly decreases. On the contrary, after the negative voltage TDDB stress, positive charges are predominantly produced at the cathode in the oxide layer and the electric field at the cathode is built up, resulting in an increase in Fowler-Nordheim tunnel current flowing though the oxide film     

Improved high-voltage lateral RESURF MOSFETs in 4H-SiC

High-voltage lateral RESURF metal oxide semiconductor field effect transistors (MOSFETs) in 4H-SiC have been experimentally demonstrated, that block 900 V with a specific on-resistance of 0.5 Ω-cm² . The RESURF dose in 4H-SiC to maximize the avalanche breakdown voltage is almost an order of magnitude higher than that of silicon; however this high RESURF dose leads to oxide breakdown and reliability concerns in thin (100-200 nm) gate oxide devices due to high electric field (>3-4 MV/cm) in the oxide. Lighter RESURF doses and/or thicker gate oxides are required in SiC lateral MOSFETs to achieve highest breakdown voltage capability     

Planar, ion implanted, high voltage 6H-SiC P-N junction diodes

Planar, high voltage (800 V) P-N junction diodes have been fabricated for the first time on N-type 6H-SiC by room temperature boron implantation through a pad oxide deposited within windows etched in an LPCVD field oxide. All the diodes showed excellent rectification with leakage currents of less than 10 nA (~5×10^-5 A/cm² ) until avalanche breakdown. It was found that the breakdown voltage increases with junction depth. The reverse recovery time (t_rr) was measured to be 50 ns for the 800 V diode from which an effective minority carrier life time of 12.5 ns was extracted     

High current bulk GaN Schottky rectifiers

GaN Schottky rectifiers employing guard-ring and SiO₂ edge termination show almost ideal forward current characteristics, with ideality factor 1.08 and specific on-state resistance as low as 2.6×10⁻³ Ω cm². A maximum forward current of 1.72 A at 6.28 V was achieved under pulsed (10% duty cycle) conditions. The reverse breakdown voltage was inversely dependent on rectifier area. The presence of defects in the GaN still dominates the reverse leakage, with both field emission and thermionic field emission contributions present. The parallel-plane breakdown voltage is never reached, even with the use of multiple edge termination methods, but the results show the promise of GaN rectifiers for power conditioning and electric utility applications.     

An 1800 V triple implanted vertical 6H-SiC MOSFET

6H silicon carbide vertical power MOSFETs with a blocking voltage of 1800 V have been fabricated. Applying a novel processing scheme, n ⁺ source regions, p-base regions and p-wells have been fabricated by three different ion implantation steps. Our SiC triple ion implanted MOSFETs have a lateral channel and a planar polysilicon gate electrode. The 1800 V blocking voltage of the devices is due to the avalanche breakdown of the reverse diode. The reverse current density is well below 200 μA/cm² for drain source voltages up to 90% of the breakdown voltage. The MOSFETs are normally off showing a threshold voltage of 2.7 V. The active area of 0.48 mm² delivers a forward drain current of 0.3 A at Y_GS=10 V and V _DS=8 V. The specific on resistance was determined to 82 mΩdcm² at 50 mV drain source voltage and at V_GS =10 V which corresponds to an uppermost acceptable oxide field strength of about 2.7 MV/cm. This specific on resistance is an order of magnitude lower than silicon DMOSFET's of the same blocking capability could offer     

Interfacial and breakdown characteristics of MOS devices with rapidly grown ultrathin SiO2gate insulators

Metal-oxide-semiconductor (MOS) devices fabricated with composite gates and subhundred-angstrom SiO2gate insulators grown by rapid thermal oxidation were characterized by various electrical measurements. The as-fabricated devices with unannealed rapidly grown oxides exhibited breakdown characteristics superior to furnace-grown oxides as evidenced by their excellent breakdown uniformity, an average breakdown field of 15 MV/cm, and an average breakdown charge density of over 50 C/cm²at a stress current density of 1 A/cm². The preoxidation surface cleaning procedure was observed to affect the charge-to-breakdown and the densities of fixed oxide charges and surface states in these MOS structures.     

Characterization of thermally oxidized n+polycrystalline silicon

The properties of thermally grown silicon dioxide films on n⁺polysilicon are studied using cross-sectional TEM, and electrical measurements to evaluate conduction, electron trapping, destructive breakdown and wearout mechanisms. All of the above electrical parameters are found to be degraded by any increase in the degree of surface roughness at the oxide-polysilicon interface. Our results suggest that a significant improvement in the insulating properties of the SiO2films can be achieved if the polysilicon is initially deposited in the amorphous phase at 560°C rather than the polycrystalline phase at 620°C. For example, for dry-oxidized diffusion-doped films, there is an increase in oxide breakdown field from 3.0 MV . cm^-1to 6.2 MV . cm^-1, and a reduction in leakage (Fowler-Nordheim) current of two orders of magnitude. Furthermore, it is shown that the long-term reliability of n⁺polysilicon/SiO2/n⁺polysilicon structures is directly related to the degree of interface texture; i.e., a smoother interface will result in a significant reduction in electrical wearout and an increase in time to failure.     

Deep-depletion breakdown voltage of silicon-dioxide/silicon MOS capacitors

The deep-depletion breakdown voltage of silicon-dioxide/ silicon MOS capacitors is determined by the ionization-integral method, with potential distributions computed by two-dimensional relaxation techniques. Calculations cover the range of substrate doping between 10¹⁴and 10¹⁸cm^-3and oxide thickness between 0.01 and 5.00 µm, providing plots of breakdown voltage versus substrate impurity concentration with oxide thickness as parameter. A universal and normalized criterion is derived for field uniformity in terms of the ratio of oxide thickness to the maximum (breakdown) width of the silicon depletion region: this ratio should be larger than 0.3 in order not to have field concentration around the edges of the metal plate.     

A GaAs MOSFET with a liquid phase oxidized gate

Low leakage current density (as low as 10^-8 A/cm² at an applied voltage of 5 V) and high breakdown electrical field (larger than 4.5 MV/cm) of the liquid phase chemical-enhanced oxidized GaAs insulating layer enable application to the GaAs MOSFET. The oxide layer is found to be a composite of Ga₂O₃, As, and As₂O₃. The n-channel depletion mode GaAs MOSFET's are demonstrated and the I-V curves with complete pinch-off and saturation characteristics can be seen. A transconductance larger than 30 mS/mm can be achieved which is even better than that of MESFET's fabricated on the same wafer structure     

Electrical properties of N2O/NH3 plasma grownoxynitride on strained-Si

Growth of ultrathin (<100 Å) oxynitride on strained-Si using microwave N₂O and NH₃ plasma is reported. X-ray photoelectron spectroscopy (XPS) results indicate a nitrogen-rich layer at the strained-Si/SiO₂ interface. The electrical properties of oxynitrides have been characterized using a metal-insulator-semiconductor (MIS) structure. A moderately low value of insulator charge density (6.1×10¹⁰ cm^-2) has been obtained for NH₃ plasma treated N₂O oxide sample. Nitrided oxide shows a larger breakdown voltage and an improved charge trapping properties under Fowler-Nordheim (F-N) constant current stress     

Analytical solutions for the breakdown voltages of punched-through diodes having curved junction boundaries at the edges

Analytical expressions are derived for the breakdown voltages of punched-through diodes having a plane structure terminated with cylindrical and spherical curved boundaries at the edges, through the use of suitable approximations for the electric field in the depletion layer. The expressions derived include both p⁺-i-n⁺and p⁺-p-n⁺(or p⁺-n-n⁺) types and are given in terms of the middle-region (i-layer or p-layer) width, the radius of curvature of the junction edge, the punch-through voltage, and the plane parallel breakdown voltage of p⁺-i-n⁺diodes. The results obtained include a correlation between the middle-region (p-layer) width and the width of the depletion layer in the curved portions of the junction when the applied reverse bias across the diode is just sufficient so that punchthrough takes in the portions where the junction is plane parallel. These results are made use of in the breakdown voltage calculations.     

Improvement of P-channel SOI LDMOS transistor by adapting a newtapered oxide technique

On-resistance of P-channel REduced SURface Field (RESURF) lateral double-diffused MOS (LDMOS) transistors has been improved by using a new tapered TEOS field oxide on the drift region of the devices. The new tapered oxidation technique provides better uniformity, less than 3%, and reproducibility. With the similar breakdown voltage (V_B), at V_gs=-5.0 V, the specific on-resistance (R_sp) of the LDMOS with the tapered field oxide is about 31.5 mΩ·cm ², while that of the LDMOS with the conventional field oxide is about R_sp=57 mΩ·cm². The uniformities of R_sp and V_B are less than 5 and 3%, respectively     

Effect of Hydrogen implantation on polysilicon p-n junctions

The effect of hydrogen implantation on theI(V)characteristics of lateral polysilicon p-n junctions is reported. After implantation with hydrogen and annealing at 400°C, a moderate decrease in the forward current and a large decrease in the reverse current is observed. In addition, the reverse breakdown voltage is increased. Best results were obtained for hydrogen dose of 10¹⁶cm^-2. The measurements are explained by considering both electric field enhancement of emission and capture rates and the generation of new trap levels by ion implantation.