All-digital TX frequency synthesizer and discrete-time receiver for Bluetooth radio in 130-nm CMOS

We present a single-chip fully compliant Bluetooth radio fabricated in a digital 130-nm CMOS process. The transceiver is architectured from the ground up to be compatible with digital deep-submicron CMOS processes and be readily integrated with a digital baseband and application processor. The conventional RF frequency synthesizer architecture, based on the voltage-controlled oscillator and the phase/frequency detector and charge-pump combination, has been replaced with a digitally controlled oscillator and a time-to-digital converter, respectively. The transmitter architecture takes advantage of the wideband frequency modulation capability of the all-digital phase-locked loop with built-in automatic compensation to ensure modulation accuracy. The receiver employs a discrete-time architecture in which the RF signal is directly sampled and processed using analog and digital signal processing techniques. The complete chip also integrates power management functions and a digital baseband processor. Application of the presented ideas has resulted in significant area and power savings while producing structures that are amenable to migration to more advanced deep-submicron processes, as they become available. The entire IC occupies 10 mm/sup 2/ and consumes 28 mA during transmit and 41 mA during receive at 1.5-V supply.     

A single-chip digitally calibrated 5.15-5.825-GHz 0.18-/spl mu/m CMOS transceiver for 802.11a wireless LAN

The drive for cost reduction has led to the use of CMOS technology in the implementation of highly integrated radios. This paper presents a single-chip 5-GHz fully integrated direct conversion transceiver for IEEE 802.11a WLAN systems, manufactured in 0.18-/spl mu/m CMOS. The IC features an innovative system architecture which takes advantage of the computing resources of the digital companion chip in order to eliminate I/Q mismatch and achieve accurately matched baseband filters. The integrated voltage-controlled oscillator and synthesizer achieve an integrated phase noise of less than 0.8/spl deg/ rms. The receiver has an overall noise figure of 5.2 dB and achieves sensitivity of -75 dBm at 54-Mb/s operation, both referred to the IC input. The transmit error vector magnitude is -33 dB at -5-dBm output power from the integrated power-amplifier driver amplifier. The transceiver occupies an area of 18.5 mm/sup 2/.     

Alternatives for on-board digital multicarrier demodulation

In this paper alternatives for digital multicarrier demodulators (MCD) suitable for advanced digital satellite communications systems are presented. The MCD permits the direct on-board interfacing of FDMA and TDM communication links by digital signal processing techniques. Two main functions are implemented by a MCD: demultiplexing (DEMUX) and demodulation (DEMOD). We focus here only on a digital implementation of the MCD, looking at its advantages, flexibility, better performance and VLSI integrability. The DEMUX may be implemented in a number of ways: the analytic signal method, fast Fourier transform with polyphase network technique, or multistage methods. For all the implementation methods considered it is shown that a certain degree of integration of DEMUX and DEMOD functions is possible. To this end, in the proposed MCD schemes the receiver pulse-shaping filter has been integrated in the DEMUX structure, reducing the overall implementation complexity. It is shown that, for the per-channel structure based on the analytic signal method, a highly modular and flexible implementation can also be achieved. Coherent demodulation is used to reduce the signal-to-noise ratio required to achieve a specified bit error rate. The coherent demodulation is carried out by using the maximum likelihood (ML) estimation method. Two different approaches to receiver synchronization have been studied. For the first, the carrier phase and symbol timing estimates are independently derived by suitable techniques. The second approach makes use of the maximum a posteriori probability method to estimate both the carrier phase and symbol timing of the receivied signal. In particular, for this technique it is shown that, by a suitable choice of the architecture of the digital coherent receiver, the ML demodulator can be integrated in the joint carrier and clock recovery circuit, with no increase in the overall system complexity. The digital architecture of the proposed MCD can be adapted to different digital modulation techniques. However, here we consider only the application for QPSK signals, as this modulation scheme is the most promising for digital satellite communications. A theoretical analysis and computer simulation have been used to evaluate the performance degradation of the proposed MCD, including finite-arithmetic implementation effects.     

Performance Evaluation of Bluetooth Systems With LDI, Modified LDI, and NSD Receivers

Bluetooth is a popular short-range low-power radio standard for wireless personal area networks. Bluetooth transmitters employ Gaussian frequency shift keying (GFSK) and simple block codes for error correction. Recently, two new receiver designs for Bluetooth devices, which are the so-called modified limiter-discriminator detector with integrate-and-dump filtering (LDI) and noncoherent sequence detection (NSD), have been proposed in the literature. While the modified LDI receiver is a concatenation of a conventional LDI detector with an improved error-correction decoder, the NSD receiver fully takes into account the memory introduced by the GFSK. Both receivers have been shown to improve the Bluetooth system performance in terms of physical-layer metrics such as bit-error rate and packet-error rate. In this paper, we present a comprehensive performance evaluation considering practically more relevant metrics such as throughput, delay, and delay jitter at the medium-access control layer. To this end, we develop an evaluation framework, which includes the spatial distribution of Bluetooth devices, path loss, fading, realistic data traffic models, scheduling, automatic repeat request, and baseband packet selection. Our numerical and simulation results verify that the newly introduced Bluetooth receivers, especially NSD, offer a significant performance enhancement for Bluetooth systems in terms of practically relevant measures.     

A single-chip tuner for DVB-T

A new architecture is presented for a single-chip tuner for digital terrestrial television, based on existing double conversion and direct conversion topologies. The new design forms part of a mixed-signal Digital Video Broadcasting-Terrestrial (DVB-T) receiver system, employing digital signal processing at baseband to ensure minimal performance requirements for the analog circuitry. To evaluate the potential performance of this new tuner/receiver system, high-level system simulations have been performed, followed by the construction of a prototype DVB-T receiver using a custom-designed analog ASIC which integrates all analog tuner blocks (including channel filtering) on one chip. Measured results from this chip, implemented in a 20-GHz bipolar technology, show an overall third-order input referred intercept point of 116 dB/spl mu/V, a noise figure of 14 dB and an automatic gain control range of 71.4 dB, drawing 250 mA at a 5-V supply.     

A digital DS spread-spectrum receiver with joint channel andDoppler shift estimation

A digital spread-spectrum receiver design is presented for communication over multipath channels with severe Doppler shifts. The characteristics of the underwater channel relevant to spread-spectrum system design are discussed, and a channel model for short-range communications (less than 10 km) is defined. The receiver considered uses a digital coherent RAKE combiner, coupled with an extended Kalman filter (EKF)-based estimator for channel parameters and pseudonoise code delay. Receiver performance is evaluated by computing average bit-error rate (BER) versus iterations of the EKF joint estimator, using both fixed and time-varying channels. It is shown that the BER obtained using the EKF joint estimator closely tracks the optimum BER obtained when the channel, delay, and Doppler parameters are known exactly. Finally, the Cramer-Rao lower bound for time-invariant joint channel, delay, and Doppler estimation is derived, and compared with the ensemble averaged mean-squared error of the EKF estimator     

An 802.11g WLAN SoC

A single-chip IEEE-802.11g-compliant wireless LAN system-on-a-chip (SoC) that implements all RF, analog, digital PHY and MAC functions has been integrated in a 0.18-/spl mu/m CMOS technology. The IC transmits 0-dBm EVM-compliant output power for a 64-QAM OFDM signal. The overall receiver sensitivities are better than -92 and -73 dBm for data rates of 6 and 54Mb/s, respectively.     

一种基于超再生原理的直扩通信系统新型接收机的设计

在短距离窄带无线通信系统中,具有结构简单、低成本、低功耗和灵敏度较高(相对于再生接收机)等优点的超再生接收机已经有几十年的应用历史。这里,根据超再生的基本原理,构建出一种用于对直序列扩频(DS-SS)信号进行非相干检测的扩频接收机的新型结构,并对其在2.4GHz的ISM波段的宽带应用进行分析。     

A 2.4-GHz-band 1.8-V operation single-chip Si-CMOS T/R-MMICfront-end with a low insertion loss switch

This paper describes the design and experimental results of a 1.8-V single-chip CMOS MMIC front-end for 2.4-GHz band short-range wireless communications, such as Bluetooth and wireless LANs. The IC consists of fundamental RF building circuits-a power amplifier (PA), a low-noise amplifier (LNA), and a transmit/receive-antenna switch (SW), including almost all on-chip matching elements. The IC was fabricated using a 0.18-μm standard bulk CMOS technology which has no extra processing steps to enhance the RF performances. Two new circuit-design techniques are introduced in the IC in order to minimize the insertion loss of the SW and realize a higher gain for the PA and LNA despite the utilization of the standard bulk CMOS technology. The first is the derivation of an optimum gate width of the SW to minimize the insertion loss based on small-signal equivalent circuit analysis. The other is the revelation of the advantages of interdigitated capacitors (IDCs) over conventional polysilicon to polysilicon capacitors and the successful use of the IDCs in the LNA and PA. The IC achieves the following sufficient characteristics for practical wireless terminals at 2.1 GHz and 1.8 V: a 5-dBm transmit power at a -1-dB gain compression, a 19-dB gain, an 18-mA current for the PA, a 1.5-dB insertion loss, more than 24-dB isolation, an 11-dBm power handling capability for the SW, a 7.5-dB gain, a 4.5-dB noise figure, and an 8-mA current for the LNA     

Microsensor Integration Into Systems-on-Chip

Sensing systems-on-chip (SSoCs), combining micromachined sensing structures and microelectronic building blocks on a single chip, are reviewed. While single-chip pressure and inertial sensing systems have been commercially available for more than a decade, the recent expansion of SSoC into new application areas, ranging from chemical and biochemical sensing to atomic force microscopy, demonstrates the full potential of this microsensor integration approach. Available fabrication processes for integrated sensing systems are summarized, categorizing them into pre-, intra-, and post-CMOS approaches depending on the way the micromachining module is merged with the integrated circuit (IC) technology. Examples of SSoCs are presented to highlight the different integration options, ranging from cointegration of micromachined sensors with purely analog signal chains to microsystems with cointegrated digital signal processors and digital interfaces.     

A low-power monolithic CMOS transceiver for 802.11b wireless LANs

A single-chip low-power transceiver IC operating in the 2.4 GHz ISM band is presented. Designed in 0.18 μm CMOS, the transceiver system employs direct-conversion architecture for both the receiver and transmitter to realize a fully integrated wireless LAN product. A sigma-delta (∑△) fractional-N frequency synthesizer provides on-chip quadrature local oscillator frequency. Measurement results show that the receiver achieves a maximum gain of 81 dB and a noise figure of 8.2 dB, the transmitter has maximum output power of-3.4 dBm and RMS EVM of 6.8%. Power dissipation of the transceiver is 74 mW in the receiving mode and 81 mW in the transmitting mode under a supply voltage of 1.8 V, including 30 mW consumed by the frequency synthesizer. The total chip area with pads is 2.7×4.2 mm2.     

A Low-Power Multicarrier-CDMA Downlink Baseband Receiver for Future Cellular Communication Systems

In this paper, design and implementation of a baseband receiver integrated circuit (IC) for a downlink multi-carrier code-division multiple access (MC-CDMA) system are presented. This MC-CDMA system aims to provide higher data transmission capacity than the current wide-band CDMA systems in mobile cellular communication environments. The proposed chip provides a robust tracking mechanism for synchronization errors and an accurate channel estimation strategy to overcome the challenge of outdoor fast-fading channels. Besides, low-power and low-complexity architecture design techniques are adopted to satisfy mobile receiver needs. Experimental results of the designed baseband receiver integrated circuit demonstrate its superior system performance and great reduction in power consumption. The chip was fabricated in a 0.18-mum CMOS technology with a core area of 2.6 mm times 2.6 mm. It can support up to 21.7-Mbps uncoded data rate in a 5-MHz bandwidth. When running at 5.76 MHz, its power consumption is as low as 9.9 mW from a supply voltage of 1.1 V.     

A dual-mode 802.11b/bluetooth radio in 0.35-/spl mu/m CMOS

A fully integrated dual-mode CMOS transceiver tuned to 2.4 GHz consumes 65 mA in receive mode and 78 mA in transmit mode from a 3-V supply. The radio includes all the receive and transmit building blocks, such as frequency synthesizer, voltage-controlled oscillator (VCO), and power amplifier, and is intended for use in 802.11b and Bluetooth applications. The Bluetooth receiver uses a low-IF architecture for higher level of integration and lower power consumption, while the 802.11b receiver is direct conversion. The receiver achieves a typical sensitivity of -88 dBm at 11 Mb/s for 802.11b, and -83 dBm for Bluetooth mode. The receiver minimum IIP3 is -8 dBm. Both transmitters use a direct-conversion architecture, and deliver a nominal output power of 0 dBm, with a power range of 20 dB in 2-dB steps.     

A 0.25-/spl mu/m CMOS OPLL transmitter IC for GSM and DCS applications

A single-chip CMOS global system for mobile communications/digital cellular system dual-band offset phase-locked loop (OPLL) transmitter is presented in this paper. This chip includes a quadrature modulator and an OPLL modulation loop. Except for the loop filter and high-power voltage-controlled oscillator (TX VCO), everything is integrated into this chip to form a dual-band transmitter. This transmitter integrated circuit is fabricated in a 0.25-mum CMOS process. The current consumption without the TX VCO is approximately 23 mA under 2.7-V power supply for both bands. The measured rms and peak phase errors for Gaussian minimum shift-keying (GMSK) modulated signals are approximately 1deg and 2.4deg, respectively. The measurements show comparable performance to its BiCMOS counterparts     

A low-power CMOS Bluetooth RF transceiver with a digital offset canceling DLL-based GFSK demodulator

This paper presents a fully integrated 0.18-/spl mu/m CMOS Bluetooth transceiver. The chip consumes 33 mA in receive mode and 25 mA in transmit mode from a 3-V system supply. The receiver uses a low-IF (3-MHz) architecture, and the transmitter uses a direct modulation with ROM-based Gaussian low-pass filter and I/Q direct digital frequency synthesizer for high level of integration and low power consumption. A new frequency shift keying demodulator based on a delay-locked loop with a digital frequency offset canceller is proposed. The demodulator operates without harmonic distortion, handles up to /spl plusmn/160-kHz frequency offset, and consumes only 2 mA from a 1.8-V supply. The receiver dynamic range is from -78 dBm to -16 dBm at 0.1% bit-error rate, and the transmitter delivers a maximum of 0 dBm with 20-dB digital power control capability.     

All-Digital PLL With Ultra Fast Settling

A fully digital frequency synthesizer for RF wireless applications has recently been proposed. At its foundation lies a digitally controlled oscillator with sufficiently fine frequency resolution to avoid analog tuning. The conventional phase/frequency detector, charge pump and RC loop filter are replaced by a time-to-digital converter and a simple digital loop filter. When implemented in highly scaled digital CMOS processes, the proposed architecture is more advantageous over conventional charge-pump-based phase-locked loops (PLLs) since it exploits signal processing capabilities of digital circuits and avoids relying on the fine voltage resolution of analog circuits. In this brief, we present novel techniques used in the all-digital PLL to achieve an ultra-fast frequency acquisition of <50 mus while maintaining excellent phase noise and spurious performance during transmission and reception. This approach has been validated and incorporated in commercial single-chip Bluetooth and Global System for Mobile Communications radios realized in deep-submicrometer CMOS     

Simplified matched filter receiver designs for spread spectrumcommunications applications

The design of receiver architectures for use in direct sequence spread spectrum systems is reviewed. As it is difficult to construct the long matched filters for these systems, the authors propose a programmable receiver architecture which achieves the required high processing gain while, at the same time, simplifying the filter hardware requirements. Results are presented for a prototype receiver, based on digital signal processing (DSP) components, which can be reprogrammed for serial, serial-parallel or fully parallel operation while offering minimal degradation from theoretical performance