一种基于知识模型的CT图像分割方法*

图像自动分割一直是医学图像处理的研究重点。系统由解剖知识模型、图像处理程序和推理机组成。模块之间的通信由黑板控制。该方法提高了医学图像分割的自动化程度和可靠性。由于具有扩展性,该方法为基于知识医学图像的处理提供一个通用的模式。     

基于抽象体系结构模板的多路软硬件划分算法

随着系统芯片技术在嵌入式系统中的应用，软硬件划分从传统的二划分问题转化为多划分问题．文中对此提出了一个由通信通道连接的处理单元网络的抽象模型来描述多处理模块结构，并利用模拟退火算法与启发式的调度算法分别完成多路软硬件划分与系统性能和代价的估算．初步的实验结果表明，该算法能有效地选择合适的体系结构，使系统的性能和代价得到优化．     

边缘增强图像互相关模板匹配的并行架构

基于归一化互相关测度(NCC)的模板匹配已经在图像处理领域得到了广泛的应用。对图像进行边缘检测然后进行模板匹配,可充分利用图像的空间相关性,锐化模板匹配结果的相关峰,提高匹配的准确度,可以获得更高的定位精度。为了有效提高定位精度,考虑到导弹制导系统的算法实时性、体积以及为适应战场不同任务阶段采用不同匹配策略的灵活性要求,基于FPGA,通过结合Sobel边缘检测,进一步改进了提出的图像归一化互相关模板匹配高速并行实现架构。对边缘检测前后图像模板匹配的仿真比较结果表明,边缘检测处理可有效锐化相关峰;基于Altera的FPGA芯片EP2S90和开发软件Quartus Ⅱ 8.0的并行实现架构功能与时序仿真及在实际目标识别系统中的应用表明,这种方案可有效地提高系统的运算速度和定位精度,FPGA实现本身也进一步缩小了系统的体积。     

An analog systolic neural processing architecture

Developed for the VLSI implementation of neural network models, our novel analog architecture adds flexibility and adaptability by incorporating digital processing capabilities. Its systolic-based architecture avoids static storage of analog values by transferring the activation values through the chip's processing units. This proposed combination of analog and digital technologies produces a densely packed, high-speed, scalable architecture, designed to easily accommodate learning capabilities     

模板匹配算法在动车零部件故障检测系统中的应用

针对动车零部件丢失、松动的故障,设计了一套采用自动视频图像识别技术进行故障自动检测的系统;在图像处理这一重要环节中,采用了基于轮廓的模板匹配算法对动车零部件是否松动、是否丢失的故障进行检测。阐述了动车零部件故障检测系统架构、各部分的实现并提出了基于轮廓的模板匹配零部件检测方法,并从对图像进行预处理、确定零部件的特征区域到设置最小分值过程进行了详细阐述。应用过程表明,应用模板匹配算法对动车零部件故障检测能够达到预期的效果。     

基于DSP+FPGA结构图像处理系统设计与实现

为了实现视频图像的实时处理，采用基于DSP FPGA的线性流水阵列结构，用现场可编程门阵列FPGA对采集的视频数字图像做预处理，并结合大规模可编程逻辑阵列CPLD进行逻辑控制，实现了视频图像的采集和目标提取的视频数字图像处理系统。介绍了该视频图像处理系统的硬件组成、工作原理和各种视频跟踪算法的应用。该系统与计算机联结，配以适当的图像处理软件和开发系统，即可形成一个通用的实时图像处理平台。     

Architecture exploration for a reconfigurable architecture template

Coarse-grained architectures (CGRAs) can be tailored and optimized for different application domains. The vast design space of coarse-grained reconfigurable architectures complicates the design of optimized processors. The goal is to design a domain-specific processor that provides just enough-flexibility for that domain while minimizing the energy consumption for a given level of performance. However, a flexible architecture template and a retargetable simulator and compiler enable systematic architecture exploration that can lead to more efficient domain-specific architecture design. This article presents such an environment and an architecture exploration for a novel CGRA template.     

近程作用离散系统大规模并行模拟概念模型

通用大规模并行计算（Ｍａｓｓｉｖｅ Ｐａｒａｌｌｅｌ Ｐｒｏｃｅｓｓｉｎｇ，ＭＰＰ）的主要困难在于有关消息传递和内存在共享的硬件必然随着处理单元的增加而复杂化，而实际上许多ＭＰＰ课题都可抽象为对近程作用离散系统的模拟，它们具有能完全并行的统一的总体算法和纯粹的局部性，若建立其专用ＭＰＰ系统，理论上能无限增加处理器数量而不使系统结构复杂化，而计算速度也将随处理器数目线性增长，从而获得最大的经济性。本     

一种结构自适应的神经网络特征选择方法

特征选择是数据处理的一项重要内容，现有的基于神经网络的特征选择方法没有考虑网络中隐结点数目的变化，使网络结构的特征选择过程中往往变得不合理，这阻碍了特征的进一步删除以及网络泛化性能的提高，针对以上问题提出了一种结构自适应的神经网络特征选择方法，通过交替删除网络中冗余的输入特征和隐结点，使网络结构在特征选择的过程中保持相对良好，实验表明，该方法既能快速有效地删除特征，又提高了网络的泛化性能。     

Synergistic Processing in Cell's Multicore Architecture

Eight synergistic processor units enable the Cell Broadband Engine's breakthrough performance. The SPU architecture implements a novel, pervasively data-parallel architecture combining scalar and SIMD processing on a wide data path. A large number of SPUs per chip provide high thread-level parallelism.     

Parallel, high-speed PC fuzzy control

To overcome the inefficiencies in processing fuzzy rules on sequential digital computers and the inflexibility of purely analog processors, we introduce a parallel architecture using analog processors with a digital interface. Our architecture for fuzzy processing supports ISA-based PC platforms. Single or multiple fuzzy units with analog processing cores can operate as stand-alone MISO or MIMO fuzzy logic controllers supporting a digital interface with a master PC (for setup, monitoring, and/or relational MIMO support). The journal issue contains a concise summary of this article. The complete article is linked to Micro's home page on the World Wide Web (http://www.computer.org/pubs/micro/micro.htm)     

User transparency: a fully sequential programming model for efficient data parallel image processing

Although many image processing applications are ideally suited for parallel implementation, most researchers in imaging do not benefit from high‐performance computing on a daily basis. Essentially, this is due to the fact that no parallelization tools exist that truly match the image processing researcher's frame of reference. As it is unrealistic to expect imaging researchers to become experts in parallel computing, tools must be provided to allow them to develop high‐performance applications in a highly familiar manner. In an attempt to provide such a tool, we have designed a software architecture that allows transparent (i.e. sequential) implementation of data parallel imaging applications for execution on homogeneous distributed memory MIMD‐style multicomputers. This paper presents an extensive overview of the design rationale behind the software architecture, and gives an assessment of the architecture's effectiveness in providing significant performance gains. In particular, we describe the implementation and automatic parallelization of three well‐known example applications that contain many fundamental imaging operations: (1) template matching; (2) multi‐baseline stereo vision; and (3) line detection. Based on experimental results we conclude that our software architecture constitutes a powerful and user‐friendly tool for obtaining high performance in many important image processing research areas. Copyright © 2004 John Wiley & Sons, Ltd.     

Computation in the Context of Transport Triggered Architectures

Processors used in embedded systems have specific requirements which are not always met by off-the-shelf processors. A templated processor architecture, which can easily be tuned towards a certain application (domain) offers a solution. The transport triggered architecture (TTA) template presented in this paper has a number of properties that make it very suitable for embedded system design. Key to its success is to give the compiler more control; it has to schedule all data transports within the processor. This paper highlights two important TTA-related issues. First a new code generation method for TTAs is discussed; it integrates scheduling and register allocation, thereby avoiding the notorious phase ordering problem between these two steps. Secondly, we discuss how to tune the instruction repertoire for an embedded processor. A tool is described which automatically detects frequent patterns of operations. These patterns can then be implemented on special function units.     

一种面向并行工程的设计过程管理体系结构

本文提出了一种基于计算机支持的协同工作面向并行工程的设计过程管理体系结构，它既有有效地支持并行设计，也可支持顺序设计。由于不同类型目标数据的设计过程的管理工作各不相同，为此引入了设计过程模糊板和触发事件的概念，以定义设计过程中不可预料的管理活动。     

The SNAP-1 parallel AI prototype

The Semantic Network Array Processor (SNAP) is a parallel architecture for knowledge representation and reasoning that uses the marker-propagation paradigm. The primary application areas of SNAP are natural language understanding and speech processing. A first-generation SNAP-1 system has been designed and constructed using an array of 144 digital signal processors organized as 32 multiprocessing clusters with dedicated communication units, a tiered synchronization scheme, and multiported memory network. Issues in the design, performance, and scalability of a marker-propagation architecture are addressed     

基于ImageJ的数字图像处理课程实验教学案例

针对计算机科学与技术专业中的数字图像处理实验教学问题,提出一种基于Java语言和ImageJ平台的数字图像处理实验教学方案。数字图像处理课程实验教学的目的是通过给学生布置难易适中的实验,让学生在实验课程中独立完成数字图像处理问题的解决。虽然学生已经学过Java语言,考虑到并不是所有学生都熟悉ImageJ软件,实验任务的起点通常是首先让学生理解并且测试已有的ImageJ插件的代码模板。其次教师要求学生在已有数字图像处理代码的基础上根据实验要求逐步对现有的插件进行扩充。由于ImageJ软件是开源的,并且本身是开放式的插件架构体系,使得这种构造性的实验教学方法成为可能。     

基于动态和静态分析的单体应用FaaS改造方法

作为Serverless架构的一种典型形态,函数即服务（function as a service,FaaS）架构将业务抽象为细粒度的函数,并且提供弹性的自动伸缩等自动化运维功能,能够大幅降低运维成本.当前,许多在线服务系统中的一些高并发、高可用、灵活多变的业务（如支付、红包等）都已经迁移到了FaaS平台上,但是大量传统单体应用还是难以利用FaaS架构的优势.针对这一问题,提出了一种基于动态和静态分析的单体应用FaaS改造方法.该方法针对指定的单体应用API,通过动态分析和静态分析相结合的方式识别并剥离其实现代码和依赖,然后按照函数模板完成代码重构.针对函数在高并发场景下的冷启动问题,该方法利用基于IO多路复用的主从多线程Reactor模型优化了函数模板,提高了单个函数实例的并发处理能力.基于该方法实现了针对Java语言的原型工具Codext,在开源Serverless平台OpenFaaS上,面向4个开源单体系统进行了实验验证.     

基于FPGA图像处理技术在钢板表面缺陷检测系统中的应用

为了解决钢板表面缺陷视觉检测系统中图像处理的瓶颈问题,采用基于FPGA的嵌入式处理系统完成大数据量、实时、在线的处理任务,从而满足高速、宽幅、高分辨率的检测要求.嵌入式系统以Altera公司最新的Stratix FPGA作为核心处理器,在分析FPGA专有的硬件结构基础上,对图像处理中的模板卷积算法进行了优化设计,采用Verilog语言对算法完成建模与实现,并在Quartus Ⅱ平台进行了仿真验证.实验与算法仿真证明嵌入式处理系统的可行性与工程实用性,从而表面缺陷检测系统中的图像信息实时处理这一关键问题得以解决.