The reduction of backgating in GaAs MESFETs by impact ionization

The reduction of drain current due to reverse substrate bias in GaAs MESFETs fabricated on EL2-compensated substrates is recovered with the application of sufficient drain bias. The recovery is shown to be due to the compensation of the negative space charge at the channel-substrate interface by holes generated by impact ionization in the MESFET channel. Illumination raises the value of drain bias needed for current recovery due to the requirement of additional hole flux to offset the effects of optically generated electrons on EL2 occupancy. Simulation results show that the channel current becomes independent of substrate bias when the bias value is sufficient to completely delete the p-type surface layer     

New MBE buffer used to eliminate backgating in GaAs MESFETs

The buffer is grown by molecular beam epitaxy (MBE) at low substrate temperatures (150-300°C) using Ga and As₄ beam fluxes. It is highly resistive, optically inactive, and crystalline, and high-quality GaAs active layers can be grown on top of the buffer. MESFETs fabricated in active layers grown on top of this new buffer show improved output resistance and breakdown voltages; the DC and RF characteristics are otherwise comparable to MESFETs fabricated by alternative means and with other buffer layers     

Shielding of backgating effects in GaAs integrated circuits

Shielding of backgating effects in GaAs IC's by using Schottky metal, ohmic metal, and n⁺-implant has been studied. Contrary to what is expected from the electrostatic principle, positive bias to the shielding bars enhances backgating. Negative bias to the Schottky shielding bars increases the threshold for backgating, effectively reducing the backgating effect. These phenomena are explained in terms of carrier injection controlled by the surface potential. The results indicate that backgating effects can be reduced through proper circuit layout.     

Reduction of backgating in GaAs/AlGaAs MESFETs by optimisation of active-layer/buffer-layer interface

Backgating measurements made on GaAs MESFETs with abrupt, graded alloy and graded superlattice interface AlGaAs buffer layers were compared to measurements made on conventional GaAs buffer-layer MESFETs. Only the superlattice interface structure showed a reduction in the backgating transconductance (by a factor of 24 compared to the GaAs buffer-layer FET). The lack of reduction in the backgating transconductance for the abrupt and graded alloy interface devices is attributed to traps resulting from GaAs growth on an AlGaAs layer.     

Substrate-impurities effects on GaAs MESFETs

The effects of background impurities in LEC and HB-grown, doped and undoped GaAs substrates on electron-concentration profiles and ion-implanted MESFET threshold voltages are modeled. For realizing the most steeply falling channel electron profiles, high concentrations of either deep or shallow acceptors are required. When background acceptor impurities are absent, the electron profiles follow the slowly falling ion-implant profiles, which are strongly influenced by ion channeling. The use of buriedp layers to give steeply falling profiles, and to reduce the dependence of MESFET threshold voltages on fluctuating acceptor impurities in GaAs is proposed.     

Ion implantation effects on GaAs MESFETs

The effects of ion-implantation on the uniformity and the ultimately achievable performance of GaAs MESFETs are calculated. The results of an extensive study of the profiles of Si, Se, and Be ions implanted into GaAs are incorporated into a combined process and device model for GaAs MESFET technology. Taken into account are the scaling of transconductances with implantation energy, effects of implant profiles and impurities on low-gate-bias transconductances, dopant diffusion during annealing, effects of encapsulant thickness and etch depth on threshold-voltage uniformity, and effects of recoil atoms on threshold voltages for implants through Si₃N₄ and SiO₂ caps     

Modeling of backgating effects on GaAs digital integrated circuits

The characteristics of GaAs MESFETs are analyzed and modeled, and the results are used to simulate the performance of GaAs digital integrated circuits in the presence of backgating. The degradation of the output current of a MESFET in a circuit is theoretically calculated by treating the channel-substrate interface as a p-n junction, with the junction bias being linearly proportional to the voltage difference between the source voltage of the MESFET and the negative bias of the integrated circuit. Good agreement is obtained between theoretical calculation and the experimental results. This analysis shows that high-threshold-voltage MESFETs are less sensitive to backgating than low-threshold-voltage devices. The model developed for backgating was incorporated into a SPICE 2 program. SPICE was used to simulate the operation of several ring oscillators with different device characteristics. The computer simulation results agree well with the experimental results. Corrections in circuit design to compensate for the backgating effect have been successfully made, and improvements in the circuit performance have been observed.     

Short-channel effects in sub-100 nm GaAs MESFETs

GaAs MESFETs with gate lengths ranging from 260 nm down to 30 nm have been fabricated using high resolution electron-beam lithography. The DC characteristics including transconductance, output conductance, threshold voltage, and subthreshold current of these devices have been measured. Short-channel effects manifested as a negative shift in threshold voltage and an increase in output conductance have been observed as the gate length decreased. These effects become pronounced as the device aspect ratio (gate-length/channel thickness) falls below 5. Subthreshold current increased with a decrease in gate length and is actually an exponential function of the gate bias for gate dimensions below 100 nm. Also, subthreshold current is an increasingly more sensitive function of the drain-to-source voltage as the gate-length is reduced. The observed effects are attributed to the space charge limited electron injection into the GaAs buffer layer under the channel.<>     

2-D simulation of kink-related sidegating effects in GaAs MESFETs

Sidegating (backgating) effects in a planar structure with sidegate on the same side as MESFET are studied by two-dimensional simulation and the results are compared with those for a structure with a backgate on the back side of the substrate. The kink-related sidegating is reproduced in the planar structure, too. Its mechanism is discussed and is attributed to the change of EL2's role from an electron trap to a recombination center by capturing holes, which are generated by impact ionization and flow into the semi-insulating substrate including EL2 (deep donor). The dependence of shallow acceptor density in the semi-insulating substrate is also studied. It is shown that the kink-related sidegating is less remarkable in the case with lower acceptor density in the substrate. Potential dependence of sidegating effects on the sidegate (backgate) position is also discussed.     

Two-dimensional analysis of surface-state effects on turn-oncharacteristics in GaAs MESFETs

Surface-state effects on gate-lag or slow current transient in GaAs MESFETs are studied by two-dimensional (2-D) simulation. It is shown that the gate-lag becomes remarkable when the deep-acceptor surface state acts as a hole trap. To suppress it, the deep acceptor should be made electron-trap-like, which can be realized by reducing the surface-state density. Device structures expected to have less gate-lag, such as a self-aligned structure with n⁺ source and drain regions and a recessed-gate structure are also analyzed. An analysis of the possible complete elimination of gate-lag in these structures is given     

Two-dimensional analysis of substrate-trap effects on turn-oncharacteristics in GaAs MESFETs

Effects of substrate traps on turn-on characteristics of GaAs MESFETs are studied by two dimensional (2-D) simulation. When the off-state gate voltage is much more negative than the threshold (pinch off) voltage and the surface-state effects are small, abnormal current overshoot and subsequent slow transients are observed for the case with undoped semi-insulating substrate including an electron trap: EL2. Even if the surface-state effects are pronounced to show the large gate-lag, the drain current may show the overshoot-like behavior at relatively early periods. The case of Cr-doped substrate with a hole trap: Cr is also discussed     

Evidence of detrimental surface effects on GaAs power MESFETs

GaAs power FETs submitted to biased life tests show a gradual degradation resulting in an output power loss and changes on DC characteristics such as gate-to-drain breakdown voltage and gate leakage current. It is shown that this degradation is correlated with surface effects.     

Reduction of backgating in GaAs SISFET's with a low-temperaturebuffer

The use of a low-temperature molecular beam epitaxy (MBE)-grown buffer layer to reduce backgating in GaAs/AlGaAs semiconductor-insulator-semiconductor FETs (SISFETs) is discussed. Comparison with a control wafer having no low-temperature buffer (LTB) reveals an improvement in backgating threshold voltage by a factor of 3, improvement in output conductance and short-channel characteristics, and no significant change in threshold voltage, threshold-voltage spread, and microwave characteristics. The FETs with LTB exhibited increased sensitivity, at 80 K, to trapping of hot electrons     

Optically induced backgating transients in GaAs FET's

Long-term current transients have been induced with optical pulses in depletion-mode GaAs field-effect transistors (FET's). The millisecond-to-second duration and the bias dependence of the transients are similar to substrate trapping and backgating events initiated by ionizing radiation. A specific region of a FET-the semiconductor region adjacent to the connecting strip between the gate electrode and the gate bonding pad-is particularly sensitive to optical backgating. In this region low-incident optical energies produce a positive current transient; but when the optical intensity exceeds ∼1 mJ/cm², a transient decrease in current is observed. Optical studies promise to be a simple and convenient means of simulating many of the effects of ionizing radiation.     

Analysis of kink-related backgating effect in GaAs MESFET

Two-dimensional simulation of backgating effect in a GaAs MESFET is made in which impact ionization of carriers and deep donors “EL2” in the substrate are considered. The kink-related backgating is reproduced, which is qualitatively consistent with recent experiments. Based on the simulated results, physical mechanism of kink-related backgating effect is discussed     

An accurate photonic capacitance model for GaAs MESFETs

A new set of pseudoempirical equations is presented in order to simulate the optical and bias dependencies of GaAs MESFET junction capacitances, which is valid for the whole I-V plane. The variations induced in the small-signal equivalent circuit by the optical illumination are extracted from on-wafer scattering parameter measurements. New linear and quasi-logarithmic variations versus the incident optical power are shown for gate-drain and gate-source (Cgd and Cgs) capacitances. Furthermore, experimental results are in very good agreement with the simulated values for a wide range of optical power and bias conditions. Large signal MESFET models show a better fit with measured S-parameters than those previously published, leading to a greater degree of confidence in the design of photonic monolithic microwave integrated circuits     

GaAs MESFET中的背栅效应

随着集成电路集成度的提高 ,器件间距不断减小 ,在 Ga As MESFET中产生了一种被称为背栅效应的有害寄生效应。由于器件间距越来越小 ,某一个器件的电极可能就是另一个器件的背栅 ,背栅效应影响了集成电路集成度的提高 ,因此背栅效应在国内外引起了重视。本文介绍了背栅效应及其可能的起因     

Carrier injection and backgating effect in GaAs MESFET's

The relation between the backgating effects on GaAs MESFET's and current conduction in the semi-insulating substrate is studied. The onset voltage of the backgating effect is found to coincide with the trap-fill-limited voltage for the substrate conduction. This observation implies that carrier injection in the substrate is directly related to the backgating effect.     

Impact ionization in GaAs MESFETs

A method to measure impact ionization current in GaAs MESFETs is presented. The impact ionization current is then used to calculate the maximum electric field in the channel and the impact ionization coefficient. Data for the electron impact ionization coefficient in 〈110〉 GaAs are extended beyond previous studies by five orders of magnitude. Impact ionization is taken into account in a new gate current model     

Inclusion of impact ionization in the backgating of GaAs FETs

It is shown that the familiar threshold behavior of the backgate current of GaAs MESFETs has hysteresis. This is associated with an S-type negative differential conductivity (S-NDC) of the semi-insulating substrate. It is difficult to account for this hysteresis using conventional trap-fill-limited (TFL) theory, and it is attributed to the impact ionization of traps in the substrate. A simple model of this ionization, involving two trap levels, is used to incorporate its effect into an existing analytical model of GaAs FETs. The result is a qualitative interpretation of the backgating characteristics of GaAs MESFETs. The calculations show that a simple combination of two ohmic elements to represent parasitic resistances, and a nonohmic one to represent impact ionization in the substrate, can imitate the observed backgating behavior