Correlations between CMOS latch-up characteristics and substrate structure parameters

A structure-oriented model based on a simplified two-dimensional numerical analysis has been developed to calculate the substrate spreading resistance of a parasitic SCR latch-up path in a CMOS circuit. This model establishes the correlation between the major latch-up characteristics parameters (holding voltage, holding current and triggering current) and the structure parameters in the substrate. The correlations thus obtained have been used to predict the effects of layout and structural changes in the substrate on the latch-up characteristics through the application of this model. It has been verified that the calculated results are in good agreement with both the experimental results of the fabricated devices and the simulation results based on the exact two-dimensional numerical analysis.     

A discussion on the temperature dependence of latch-up triggercurrent in CMOS/BiCMOS structures

The measured temperature dependence of latch-up trigger currents in CMOS/BiCMOS structures from 10 to 125 °C is quantitatively discussed based on a simple lumped element equivalent model. Temperature coefficients of the p-well and n-well trigger currents for three different well structures are around -1.0%/°C and -0.6%/°C, respectively. The latch-up trigger currents calculated using temperature dependent parasitic parameter values such as the current gains of parasitic bipolar transistors, the forward emitter-base voltage, and parasitic well shunting resistances are in good agreement with the measured ones. In addition, the role each parameter plays in reducing latch-up trigger currents at higher temperature is clarified     

Latchup model for the parasitic p-n-p-n path in bulk CMOS

The inherent parasitic bipolar transistors and p-n-p-n paths in monolithic CMOS circuits can be undesirably triggered into the low resistance and high current state, i.e., latchup. To ensure the safe operation for the future scaled CMOS circuits, an accurate latchup model is required for design optimization. A modified lumped resistance model has been developed which is shown to accurately predict the latchup characteristics provided the device parameters are accurately measured and reflect those at the latchup state. The model includes the spreading resistance effect in the substrate by a resistor network and it is shown to be critical in the latch-up characterization. Experimental data that supports this model is presented. The reversed layouts in CMOS circuits have been shown to greatly improve the latchup holding current. The dynamic characterization of latchup, caused by voltage overshoot at the input terminals, has also been characterized. It is shown that a minimum turn-on time for the latchup triggering exists and is governed by the base transit time in the lateral transistor with an enhanced diffusion coefficient from the high injection effect.     

The effects of phosphorus diffusion cooling rate on I2L gain

It has been found that the current gain of an I²L cell can be seriously degraded if the deep collector (phosphorus) diffusion is not slow cooled. A correlation between improper cooling rate and the generation of a severe edge dislocation network is established. This network is shown to result in leaky emitter-base and collector-base junctions in an I²L cell but not in a conventional n-p-n transistor. These leaky junctions correlate with the observed low gain. A model is proposed to explain the cooling rate dependence of the dislocation networks in terms of vacancy clustering.     

Cell geometry effect on IGT latch-up

The effect of the emitter cell geometry on insulated gate transistor (IGT) performance has been investigated. The three-dimensional well resistances (emitter shunting resistance) of the square, circular, stripe, and multiple surface short (MSS) have been calculated. The MSS cell geometry has the lowest emitter shunting resistance. As a result, MSS cell has the highest latch-up current capability. It has been experimentally proven that the stripe cell has extremely high latch-up current, and the MSS cell design is current limited. The IGT's with circular and square cell have the lowest latch-up current capability.     

The impact of trench isolation on latch-up immunity in bulknonepitaxial CMOS

Numerical simulations have been used to show that two-dimensional effects can improve the latch-up immunity of deep trench-isolated, bulk, nonepitaxial CMOS. It is observed that the holding voltage is strongly influenced by trench dimensions and layout, which affect the two-dimensional spreading resistance of the conductivity-modulated well and substrate regions, which also changes the parasitic bipolar current gain. To increase the holding voltage, design parameters that are unique to deep trench isolation have been identified. The theoretical understanding that has been obtained can be exploited to design latch-up-free submicrometer CMOS at high packing densities without using expensive epitaxial substrates     

Numerical analysis on abnormal thyristor forward voltage increase due to heavy doping in gated p-base layer

An abnormal forward voltage increase was observed for a p-base gated double diffused n⁺pn^?p⁺ high power thyristor with high impurity concentration at the n⁺-p emitter-base junction. Accurate numerical analysis shows that heavy doping effects are the most responsible mechanism for the abnormality and that depletion layer formation at the center junction accompanies it.It will be shown that appropriate control of the impurity concentration at the emitter-base junction is necessary to avoid this abnormality by realizing the common base transistor current gain of greater than 0.73 for n⁺n^?-portion.     

An efficient two-dimensional model for CMOS latchup analysis

A general structure-oriented model has been specially designed to estimate the substrate spreading resistance of a parasitic SCR latchup path in a CMOS structure, which can handle CMOS structures with normal and reverse layouts in the substrate, with top and back substrate contacts, and with an epitaxial layer in the substrate. The simplified 2D numerical analysis based on solving the Laplace equation has been carried out and used to quantitatively evaluate the substrate spreading resistance of a parasitic SCR latchup path. Based on the calculated substrate spreading and well resistances, the holding voltage and holding current as well as the triggering current have been calculated and compared with the experimental measurements. Moreover, the predicted holding voltage value is shown to be nearly identical to that obtained using the full 2D numerical analysis for a specified CMOS latchup path. In addition, the developed model has been thoroughly applied to evaluate a variety of the CMOS structures and close correlations between the predicted results and the reported latchup experiments are quite encouraging. Furthermore, a latchup-free CMOS structure predicted by the developed model has been shown to be consistent with some experimentally verified latchup-free structures published in the literature.     

Numerical CML switching analyses for heterojunction GaAs/(GaAl)As bipolar transistors

The switching performance of GaAs/Ga_0.7Al_0.3As n-p-n heterojunction bipolar transistors (HBTs) has been investigated for current-mode-logic circuit operation using a hybrid device model composed of numerical one-dimensional transistor and diode models interconnected through resistances corresponding to the real device structure.Switching time is discussed in conjunction with parasitic effects, external circuit conditions and doping profiles.Ultra-high-speed switching of less than 10 ps has been shown to be attainable by scaling the device pattern dimensions down to 1 μm order of magnitude.     

An isolated Al-poly Si-(p)Si-(n+)Si switching device

A new MISS switching device structure was designed and fabricated, which consists of Al/poly Si/p/n⁺/p-Si layers and is isolated by diffusing n-well to the buried n⁺ layer.The switching voltage increases with increasing junction area of the poly-Si junction and the n⁺p junction, due to surface recombination current in the emitter-base junction, respectively. The holding voltage is kept nearly constant of 0.9 V for the 886 Å poly Si devices.     

A simplified computer analysis for n-well guard ring efficiency in CMOS circuits

Based on solving the 2-D continuity and current transport equations for electrons injected into the substrate of a n-well CMOS, a quantitative evaluation of n-well guard ring efficiency in terms of the escape electron current is presented. Simulation results show that in the worst-case condition Auger recombination inherent in the heavily-doped substrate of epi-CMOS is responsible for the enhancement of n-well guard ring efficiency. Also, our simulations show that the substrate doping should be as high as possible and the epi-layer thickness should be as thin as possible. Thus a narrow well-type guard ring can be used in order to make efficient use of epi-CMOS for suppressing the escape electron current to a low level so as to preclude latch-up.     

Temperature dependence of latch-up phenomena in scaled CMOS structures

In this paper the temperature dependence of latch-up in a VLSI CMOS technology is studied. Both steady-state and pulse-induced dynamic trigger characteristics are presented showing a marked increase in latch-up resistance with decreasing temperature; in particular, a latch-up free condition is met for several structures at temperatures ranging between 100 and 200 K. The results of measurements of parasitic bipolar parameters and shunting resistances at different temperatures are reported, and their values are related to latch-up characteristics.     

高温CMOS集成电路闩锁效应分析

本文详细地分析了LDD结构高温CMOS集成电路闩锁效应.文中提出了亚微米和深亚微米CMOS集成电路闩锁效应的模型.在该模型中,针对器件的尺寸和在芯片上分布情况,我们认为CMOS IC闩锁效应的维持电流有两种模式:大尺寸MOST的寄生双极晶体管是长基区,基区输运因子起主要作用;VLSI和ULSI中MOST的寄生双极晶体管是短基区,发射效率起主要作用.但是他们的维持电流都与温度是负指数幂关系.文章给出了这两种模式下的维持电流与温度关系,公式在25℃至300℃之间能与实验结果符合.     

Two-dimensional effects in the bipolar polysilicon self-aligned transistor

There has been a great deal of interest recently in the performance enhancements afforded by self-aligned silicon transistors. Concomitantly, it has been observed that the current gain and collector drive capability of these devices sometimes exhibit a strong dependence an the geometrical size and shape of the emitter, In this study, it has been shown that this two-dimensional effect is explicable in terms of a parasitic p-n diode in parallel with the emitter-base junction. An accurate model has been developed to predict the geometry-dependent current gain under low to moderate bias. It is further shown how the model can be extended to the high-bias regime. Lastly, it is shown, by means of an emitter-base debiasing model, that the geometry of the emitter contact has a more significant effect on the emitter-base debiasing than does the intrinsic base sheet resistance itself.     

A model for the breakdown characteristics of p-channel MOS transistor protection devices

Gate controlled diodes, MOS transistors with grounded gate, source and substrate and gate controlled pnn + structures are compared when used as a protective input device on p-channel MOS integrated circuits. For this purpose two pulse techniques are developed which allow an accurate determination of the dynamic resistance by minimizing the walk-out of the breakdown voltage during the measurement. While the breakdown voltage does not differ much for the different types of devices, the dynamic resistance however is found to be considerably lower for the MOS transistor than for both other devices. For these low values the series resistance of the drain and source diffusion is shown to constitute already an important contribution. The lower dynamic resistance of MOST's can be ascribed to parasitic bipolar transistor operation during breakdown. The identification of this mechanism leads to a simple model for the MOS transistor in breakdown which has been experimentally verified and confirmed. Guidelines for the definition of the source diffusion for an optimal protective functioning can be obtained from this model.     

Latch-up and image crosstalk suppression by internal gettering

Internal gettering can be used to reduce crosstalk in imagers and latch-up susceptibility in CMOS circuits. The internal gettering process forms defects in the bulk of the silicon wafers that are effective recombination sites for minority carriers in the substrate. Experimental and theoretical results are presented for the crosstalk reduction obtained in an area imager. Also, the current gain β of the parasitic lateral n-p-n transistors formed in the substrate in CMOS circuits was considerably lower for the internally gettered wafers. The trigger current needed to initiate latch-up in the n-p-n-p structures increased as 1/β, in accordance with the theory. A Monte Carlo method was developed to calculate the expected lateral transistor current gain. The calculated β's are in excellent agreement with the measured values.     

A computer-aided simulation model for the I–V characteristic of M-n-p silicon Schottky-barrier diodes produced by use of low-energy arsenic-ion implantation

Current-transport properties of Al-n-p silicon Schottky-barrier diodes have been studied both experimentally and theoretically. An analytical model for the I-V characteristic of a metal-n-p Schottky barrier diode has been developed by using an interfacial layer-thermionic-diffusion model. Assuming a Gaussian distribution for the implanted profile, the barrier-height enhancement and ideality factor have been derived analytically. Using low energy (25 KeV) arsenic implantation with the dose ranged form 8 × 10¹⁰/cm² to 10¹²/cm², Al-n-p silicon Schottky barrier diodes have been fabricated and characterized. Comparisons between the experimental measurements and the results of computer simulations have been performed and satisfactory agreements between these comparisons have been obtained. The reverse I–V characteristics of the fabricated Al-n-p silicon Schottky barrier diodes can also be well simulated by the developed model.     

A distributed model of the junction transistor and its application in the prediction of the emitter-base diode characteristic, base impedance, and pulse response of the device

A distributed model for a junction transistor has been analyzed to include both dc and ac biasing effects in the active base region, with particular emphasis on a small-geometry diffused base planar transistor. For such devices with extremely narrow base width, dc biasing effects cannot be neglected. At high frequencies, the response of these devices is greatly modified by ac biasing effects which are accentuated by the significant dc biasing at large emitter current levels. Two-dimensional current flow under these biasing conditions was studied with a distributed model of the active base region. From such a model, the expressions for emitter-base diode characteristic, small-signal and large-signal base resistance, and complex base impedance valid for high frequencies have been deduced in terms of physical parameters of the devices like the geometry, base resistivity, etc. This equivalent base impedance and an ideal diode with its diffusion and emitter-base transition capacitance constitute the lumped model of the emitter-base region. For any particular frequency, the base impedance can be represented exactly by a parallel RC network. The distributed model can also predict the pulse response of the device more accurately than a lumped model and show the sensitivity of the transient response to the physical parameters mentioned above. Experimental verifications of the theoretical expressions are found to be satisfactory, and limitations of the earlier works are pointed out in regard to present devices.     

Substrate potential shift due to parasitic minority carrier injection in smart-power ICs: measurements and full-chip 3D device simulation

Substrate current injection effects are one of the major risks for smart-power IC functionality, often leading to redesigns. Smart-power ICs for motor control consist of four power transistors in H-bridge configuration and the controlling circuitry on a single chip. During switching of the power stages driving an inductive load (e.g. a motor), parasitic bipolar transistors turn on and inject electrons and holes into the substrate. This leads to a substrate potential shift with the risk of disturbing the functionality of the controlling circuitry or even triggering a latch-up. The substrate potential shift due to minority carrier injection by the lateral parasitic NPN transistor has been measured on a test chip and analyzed by 3D device simulation. The previously calibrated 3D device simulation and the measurements are in good agreement. The influence of protecting measures (substrate contacts) and the backside contact has been investigated experimentally. For the first time, the potential shift due to the parasitic substrate NPN transistor has been measured and simulated in 3D on an entire chip.     

Noise associated with recombination in the emitter space charge region of transistors

We have measured the noise associated with the recombination current I_R in the emitter space charge region of a p-n-p transistor at 100°K and find I_EQ = ζI_R, where ξ lies above 0.75 and increases with increasing emitter current. Lauritzen's theory predicts ζ = 0.75; the reasons for this relatively small discrepancy are discussed.