Elixir: High-Throughput Cost-Effective Dual-Field Processors and the Design Framework for Elliptic Curve Cryptography

We present a design framework that consists of a high-throughput, parallel, and scalable elliptic curve cryptographic (ECC) processor, and its cost-effectiveness methodology for the design exploration. A two-phase scheduling methodology is proposed to optimize the ECC arithmetic over both ${rm GF}(p)$ and ${rm GF}(2^m)$. Based on the methodology, a parallel and scalable ECC architecture is also proposed. Our dual-field ECC architecture supports arbitrary elliptic curves and arbitrary finite fields with different field sizes. The optimization to a variety of applications with different area/throughput requirements can be achieved rapidly and efficiently. Using 0.13-$mu$m CMOS technology, a 160-bit ECC processor core is implemented, which can perform elliptic-curve scalar multiplication in 340 $mu$s over ${rm GF}(p)$ and 155 $mu$s over ${rm GF}(2^m)$, respectively. The comparison of speed and area overhead among different ECC designs justifies the cost-effectiveness of the proposed ECC architecture with its design methodology.      

$S$ - and $C$ -Band Ultra-Compact Phase Shifters Based on All-Pass Networks

Ultra-compact phase shifters are presented. The proposed phase-shifting circuits utilize the lumped element all-pass networks. The transition frequency of the all-pass network, which determines the size of the circuit, is set to be much higher than the operating frequency. This results in a significantly small chip size of the phase shifter. To verify this methodology, 5-bit phase shifters have been fabricated in the $S$ - and $C$ -band. The $S$ -band phase shifter, with a chip size of 1.87 mm $,times,$0.87 mm (1.63 mm $^{2}$), has achieved an insertion loss of ${hbox{6.1 dB}} pm {hbox{0.6 dB}}$ and rms phase-shift error of less than 2.8$^{circ}$ in 10% bandwidth. The $C$ -band phase shifter, with a chip size of 1.72 mm $,times,$0.81 mm (1.37 mm $^{2}$), has demonstrated an insertion loss of 5.7 dB $pm$ 0.8 dB and rms phase-shift error of less than 2.3 $^{circ}$ in 10% bandwidth.      

Analysis and Design of a CMOS UWB LNA With Dual- -Branch Wideband Input Matching Network

A wideband low-noise amplifier (LNA) based on the current-reused cascade configuration is proposed. The wideband input-impedance matching was achieved by taking advantage of the resistive shunt–shunt feedback in conjunction with a parallel LC load to make the input network equivalent to two parallel $RLC$-branches, i.e., a second-order wideband bandpass filter. Besides, both the inductive series- and shunt-peaking techniques are used for bandwidth extension. Theoretical analysis shows that both the frequency response of input matching and noise figure (NF) can be described by second-order functions with quality factors as parameters. The CMOS ultra-wideband LNA dissipates 10.34-mW power and achieves ${ S}_{11}$ below $-$8.6 dB, ${ S}_{22}$ below $-$10 dB, ${ S}_{12}$ below $-$26 dB, flat ${ S}_{21}$ of 12.26 $pm$ 0.63 dB, and flat NF of 4.24 $ pm$ 0.5 dB over the 3.1–10.6-GHz band of interest. Besides, good phase linearity property (group-delay variation is only $pm$22 ps across the whole band) is also achieved. The analytical, simulated, and measured results agree well with one another.      

A Noise-Coupled Time-Interleaved Delta-Sigma ADC With 4.2 MHz Bandwidth, ${-}$ 98 dB THD, and 79 dB SNDR

This paper describes a wideband high-linearity $Delta Sigma $ ADC. It uses noise coupling combined with time interleaving. Two versions of a two-channel time-interleaved noise-coupled $Delta Sigma $ ADC were realized in a 0.18- $mu{hbox {m}}$ CMOS technology. Noise coupling between the channels increases the effective order of the noise-shaping loops, provides dithering, and prevents tone generation in all loops. Time interleaving enhances the effects of noise coupling. Using a 1.5 V supply, the device achieved excellent linearity (${rm SFDR} > {hbox {100~dB}}$, ${rm THD}= -{hbox {98~dB}}$) and an SNDR of 79 dB in a 4.2 MHz signal band.      

Q-Band pHEMT and mHEMT Subharmonic Gilbert Upconversion Mixers

This letter makes a comparison between Q-band 0.15 $mu{rm m}$ pseudomorphic high electron mobility transistor (pHEMT) and metamorphic high electron mobility transistor (mHEMT) stacked-LO subharmonic upconversion mixers in terms of gain, isolation and linearity. In general, a 0.15 $mu{rm m}$ mHEMT device has a higher transconductance and cutoff frequency than a 0.15 $mu{rm m}$ pHEMT does. Thus, the conversion gain of the mHEMT is higher than that of the pHEMT in the active Gilbert mixer design. The Q-band stacked-LO subharmonic upconversion mixers using the pHEMT and mHEMT technologies have conversion gain of $-$7.1 dB and $-$0.2 dB, respectively. The pHEMT upconversion mixer has an ${rm OIP}_{3}$ of $-$12 dBm and an ${rm OP}_{1 {rm dB}}$ of $-$24 dBm, while the mHEMT one shows a 4 dB improvement on linearity for the difference between the ${rm OIP}_{3}$ and ${rm OP}_{1 {rm dB}}$. Both the chip sizes are the same at 1.3 mm $times$ 0.9 mm.      

Design of a Beam Switching/Steering Butler Matrix for Phased Array System

A compact broadband 8-way Butler matrix integrated with tunable phase shifters is proposed to provide full beam switching/steering capability. The newly designed multilayer stripline Butler matrix exhibits an average insertion loss of 1.1 dB with amplitude variation less than $pm$2.2 dB and an average phase imbalance of less than 20.7$^{circ}$ from 1.6 GHz to 2.8 GHz. The circuit size is only $160times 100 {rm mm}^{2}$, which corresponds to an 85% size reduction compared with a comparable conventional microstrip 8-way Butler matrix. The stripline tunable phase shifter is designed based on the asymmetric reflection-type configuration, where a Chebyshev matching network is utilized to convert the port impedance from 50 $Omega$ to 25 $Omega$ so that a phase tuning range in excess of 120$^{circ}$ can be obtained from 1.6 GHz to 2.8 GHz. To demonstrate the beam switching/steering functionality, the proposed tunable Butler matrix is applied to a 1 $times$ 8 antenna array system. The measured radiation patterns show that the beam can be fully steered within a spatial range of 108 $^{circ}$.      

Linear Systems, Sparse Solutions, and Sudoku

In this paper, we show that Sudoku puzzles can be formulated and solved as a sparse linear system of equations. We begin by showing that the Sudoku ruleset can be expressed as an underdetermined linear system: ${mmb{Ax}}={mmb b}$, where ${mmb A}$ is of size $mtimes n$ and $n>m$. We then prove that the Sudoku solution is the sparsest solution of ${mmb{Ax}}={mmb b}$, which can be obtained by $l_{0}$ norm minimization, i.e. $minlimits_{mmb x}Vert{mmb x}Vert_{0}$ s.t. ${mmb{Ax}}={mmb b}$. Instead of this minimization problem, inspired by the sparse representation literature, we solve the much simpler linear programming problem of minimizing the $l_{1}$ norm of ${mmb x}$, i.e. $minlimits_{mmb x}Vert{mmb x}Vert_{1}$ s.t. ${mmb{Ax}}={mmb b}$, and show numerically that this approach solves representative Sudoku puzzles.      

Design Principles for Higher (Prime) Order Composite Directional Couplers

The theoretical construction of ideal (lossless) 3 $,times,$3, 4 $,times,$4, and 5 $,times,$5 dimensional directional couplers from 2$,times,$ 2 directional couplers is demonstrated. Such devices could be fabricated as planar waveguide circuit elements.      

An Analytical Method to Extract the Physical Parameters of a Solar Cell From Four Points on the Illuminated $J{-}V$ Curve

For a variety of solar cells, it is shown that the single exponential $J{-}V$ model parameters, namely—ideality factor $eta$ , parasitic series resistance $R_{s}$, parasitic shunt resistance $R_{rm sh}$, dark current $J_{0}$, and photogenerated current $J_{rm ph}$ can be extracted simultaneously from just four simple measurements of the bias points corresponding to $V_{rm oc}$, $sim!hbox{0.6}V_{rm oc}$, $J_{rm sc}$, and $sim! hbox{0.6}J_{rm sc}$ on the illuminated $J{-}V$ curve, using closed-form expressions. The extraction method avoids the measurements of the peak power point and any $dJ/dV$ (i.e., slope). The method is based on the power law $J{-}V$ model proposed recently by us.      

17 GHz RF Front-Ends for Low-Power Wireless Sensor Networks

A 17 GHz low-power radio transceiver front-end implemented in a 0.25 $mu{hbox {m}}$ SiGe:C BiCMOS technology is described. Operating at data rates up to 10 Mbit/s with a reduced transceiver turn-on time of 2 $mu{hbox {s}}$, gives an overall energy consumption of 1.75 nJ/bit for the receiver and 1.6 nJ/bit for the transmitter. The measured conversion gain of the receiver chain is 25–30 dB into a 50 $Omega$ load at 10 MHz IF, and noise figure is 12 $pm$0.5 dB across the band from 10 to 200 MHz. The 1-dB compression point at the receiver input is $-$37 dBm and ${hbox{IIP}}_{3}$ is $-$25 dBm. The maximum saturated output power from the on-chip transmit amplifier is $-$1.4 dBm. Power consumption is 17.5 mW in receiver mode, and 16 mW in transmit mode, both operating from a 2.5 V supply. In standby, the transceiver supply current is less than 1 $mu{hbox {A}}$.      

Separated Unicast/Multicast Splitter-and-Delivery Switch and Its Use in Multicasting-Capable Optical Cross-Connect

We propose a novel separated unicast/multicast splitter-and-delivery (SUM-SaD) switch for mixed unicast and multicast traffic. Only multicast connections undergo extra splitting loss but are compensated by incorporated optical amplifiers. A typical multicasting-capable optical cross-connect is constructed by using the proposed SUM-SaDs. Theoretically, we prove that it is strictly nonblocking for both unicast and multicast connections if $d=N/2$, where $N$ and $d$ are the dimension of SUM-SaD and the number of SaD input ports, respectively. Therefore, $d$ means the maximum accommodated trees in the SUM-SaD. To save cost, $d$ can be less than $N/2$ , and the throughput performance is investigated by simulation. The results show that the throughput is improved when $d$ increases. In the experiment, we construct a 4 $times$ 4 SUM-SaD prototype and measure the bit-error rate (BER) of unicast connection, multicast connection with or without optical amplifier. There is no clear BER difference between them for the small dimensional SUM-SaD switch.      

Improved Microwave Noise Performance by SiN Passivation in AlGaN/GaN HEMTs on Si

Effects of silicon nitride (SiN) surface passivation by plasma enhanced chemical vapor deposition (PECVD) on microwave noise characteristics of AlGaN/GaN HEMTs on high-resistivity silicon (HR-Si) substrate have been investigated. About 25% improvement in the minimum noise figure $(NF_{min})$ (0.52 dB, from 2.03 dB to 1.51 dB) and 10% in the associate gain $(G_{rm a})$ (1.0 dB, from 10.3 dB to 11.3 dB) were observed after passivation. The equivalent circuit parameters and noise source parameters (including channel noise coefficient $(P)$, gate noise coefficient $(R)$, and their correlation coefficient $(C)$ ) were extracted. $P$ , $R$ and $C$ all increased after passivation and the increase of C contributes to the decrease of the noise figure. It was found that the improved microwave small signal and noise performance is mainly due to the increase of the intrinsic transconductance $(g_{{rm m}0})$ and the decrease of the extrinsic source resistance $(R_{rm s})$.      

Sensor Selection via Convex Optimization

We consider the problem of choosing a set of $k$ sensor measurements, from a set of $m$ possible or potential sensor measurements, that minimizes the error in estimating some parameters. Solving this problem by evaluating the performance for each of the $m choose k$ possible choices of sensor measurements is not practical unless $m$ and $k$ are small. In this paper, we describe a heuristic, based on convex optimization, for approximately solving this problem. Our heuristic gives a subset selection as well as a bound on the best performance that can be achieved by any selection of $k$ sensor measurements. There is no guarantee that the gap between the performance of the chosen subset and the performance bound is always small; but numerical experiments suggest that the gap is small in many cases. Our heuristic method requires on the order of $m^{3}$ operations; for $m=$ 1000 possible sensors, we can carry out sensor selection in a few seconds on a 2-GHz personal computer.      

10-GHz and 20-GHz Channel Spacing High-Resolution AWGs on InP

This letter reports on 10-GHz and 20-GHz channel-spacing arrayed waveguide gratings (AWGs) based on InP technology. The dimensions of the AWGs are 6.8$,times,$8.2 mm$^{2}$ and 5.0$,times,$6.0 mm$^{2}$, respectively, and the devices show crosstalk levels of $-$12 dB for the 10-GHz and $-$17 dB for the 20-GHz AWG without any compensation for the phase errors in the arrayed waveguides. The root-mean-square phase errors for the center arrayed waveguides were characterized by using an optical vector network analyzer, and are 18 $^{circ}$ for the 10-GHz AWG and 28$^{circ}$ for the 10-GHz AWG.      

A Low-Voltage Mobility-Based Frequency Reference for Crystal-Less ULP Radios

The design of a 100 kHz frequency reference based on the electron mobility in a MOS transistor is presented. The proposed low-voltage low-power circuit requires no off-chip components, making it suitable for application in wireless sensor networks (WSN). After a single-point calibration, the spread of its output frequency is less than 1.1% (3$sigma $) over the temperature range from $-{hbox{22}},^{circ}{hbox{C}}$ to 85$,^{circ}{hbox{C}}$ . Fabricated in a baseline 65$~$nm CMOS technology, the frequency reference circuit occupies 0.11$ hbox{mm}^{2}$ and draws 34 $ muhbox{A}$ from a 1.2 V supply at room temperature.      

A Wideband PLL-Based G/FSK Transmitter in 0.18 $mu$m CMOS

A wideband phase-locked loop (PLL)-based G/FSK transmitter (TX) architecture is presented in this paper. In the proposed TX, the G/FSK data is applied outside the loop; hence, the data rate is not constrained by the PLL bandwidth. In addition, the PLL remains locked all the time, preventing the carrier frequency from drifting. In this architecture, the G/FSK modulation signal is generated from a proposed Sigma-Delta modulated Phase Rotator $(SigmaDelta{hbox{-PR}})$. By properly combining the multi-phase signals from the PLL output, the $SigmaDelta{hbox{-PR}}$ effectively operates as a fractional frequency divider, which can synthesize modulation signals with fine-resolution frequencies. The proposed $SigmaDelta{hbox{-PR}}$ adopts the input signal as the phase transition trigger, facilitating a glitch-free operation. The impact of the $SigmaDelta{hbox{-PR}}$ on the TX output noise is also analyzed in this paper. The proposed TX with the $SigmaDelta{hbox{-PR}}$ is digitally programmable and can generate various G/FSK signals for different applications. Fabricated in a 0.18 $muhbox{m}$ CMOS technology, the proposed TX draws 6.3 mA from a 1.4 V supply, and delivers an output power of $-$11 dBm. With a maximum data rate of 6 Mb/s, the TX achieves an energy efficiency of 1.5 nJ/bit.      

Fast Characterization of Threshold Voltage Fluctuation in MOS Devices

Random microscopic fluctuations in the number and location of dopant atoms can cause a large variation in the threshold voltage $(V _{T})$ of a MOS device. In this paper, we present a technique for fast characterization of random threshold voltage mismatch in MOS devices. Our $V _{T}$ scatter characterization method measures threshold voltage shift by monitoring the change in gate-to-source voltage $V _{GS}$ for a fixed drain current $I _{DS}$ and drain-to-source voltage $V _{DS}$ . We present circuit schematics to characterize $V _{T}$ scatter by measuring $V _{GS}$ variation for a large set of devices arranged in an individually addressable array. We report experimental results of $V _{T}$ scatter measurement from test chips fabricated in 65-nm silicon-on-insulator and 65-nm bulk CMOS processes. We also measure and report the magnitude of local device current mismatch caused by $V _{T}$ fluctuation.      

The Observable Part of a Network

The union of all shortest path trees $G_{cup {rm spt}}$ is the maximally observable part of a network when traffic follows shortest paths. Overlay networks such as peer to peer networks or virtual private networks can be regarded as a subgraph of $G_{cup {rm spt}}$. We investigate properties of $G_{cup {rm spt}}$ in different underlying topologies with regular i.i.d. link weights. In particular, we show that the overlay $G_{cup {rm spt}}$ in an ErdÖs–RÉnyi random graph $G_{p}left (Nright)$ is a connected $G_{p_{c}}left (Nright)$ where $p_{c}sim {{ log N}over { N}}$ is the critical link density, an observation with potential for ad-hoc networks.      

An Edge Missing Compensator for Fast Settling Wide Locking Range Phase-Locked Loops

An edge missing compensator (EMC) is proposed to approach the function of an ideal PD with $pm 2 ^{N-1} times 2pi $ linear range with $N$-bit EMC. A PLL implemented with a 9-bit EMC achieves 320 MHz frequency hopping within 10 $~mu{hbox {s}}$ logarithmically which is about 2.4 times faster than the conventional design. The reference spur of the PLL is ${-}{hbox {48.7~dBc}}$ and the phase noise is ${-}hbox{88.31~dBc/Hz}$ at 10 kHz offset with $K_{rm VCO}= -$ 2 GHz/V.      

A 36–80 GHz High Gain Millimeter-Wave Double-Balanced Active Frequency Doubler in SiGe BiCMOS

This letter presents a high conversion gain double-balanced active frequency doubler operating from 36 to 80 GHz. The circuit was fabricated in a 200 GHz ${rm f}_{rm T}$ and ${rm f}_{max}$ 0.18 $mu$m SiGe BiCMOS process. The frequency doubler achieves a peak conversion gain of 10.2 dB at 66 GHz. The maximum output power is 1.7 dBm at 66 GHz and ${-}3.9$ dBm at 80 GHz. The maximum fundamental suppression of 36 dB is observed at 60 GHz and is better than 20 dB from 36 to 80 GHz. The frequency doubler draws 41.6 mA from a nominal 3.3 V supply. The chip area of the active frequency doubler is 640 $mu$m $,times,$424 $mu$m (0.272 mm $^{2}$) including the pads. To the best of authors' knowledge, this active frequency doubler has demonstrated the highest operating frequency with highest conversion gain and output power among all other silicon-based active frequency doublers reported to date.