Process integration and device performance of a submicrometerBiCMOS with 16-GHz ft double poly-bipolar devices

Submicrometer-channel CMOS devices have been integrated with self-aligned double-polysilicon bipolar devices showing a cutoff frequency of 16 GHz. n-p-n bipolar transistors and p-channel MOSFETs were built in an n-type epitaxial layer on an n⁺ buried layer, and n-channel MOSFETs were built in a p-well on a p⁺ buried layer. Deep trenches with depths of 4 μm and widths of 1 μm isolated the n-p-n bipolar transistors and the n- and p-channel MOSFETs from each other. CMOS, BiCMOS, and bipolar ECL circuits were characterized and compared with each other in terms of circuit speed as a function of loading capacitance, power dissipation, and power supply voltage. The BiCMOS circuit showed a significant speed degradation and became slower than the CMOS circuit when the power supply voltage was reduced below 3.3 V. The bipolar ECL circuit maintained the highest speed, with a propagation delay time of 65 ps for C_L=0 pF and 300 ps for C_L=1.0 pF with a power dissipation of 8 mW per gate. The circuit speed improvements in the CMOS circuits as the effective channel lengths of the MOS devices were scaled from 0.8 to 0.4 μm were maintained at almost the same ratio     

High-performance dual-gate CMOS utilizing a novel self-alignedpocket implantation (SPI) technology

A self-aligned pocket implantation (SPI) technology is discussed. This technology features a localized pocket implantation using the gate and drain electrodes (TiSi₂ film) as well as self-aligned masks. The gate polysilicon is patterned by KrF excimer laser lithography. The measured minimum gate length L_g (the physical gate length) is 0.21 μm for both N- and P-MOSFETs. A newly developed photoresist was used to achieve less than quarter-micrometer patterns. This process provides high punchthrough resistance and high current driving capability even in such a short channel length. The subthreshold slope of the 0.21-μm gate length is 76 mV/dec for N-MOSFETs and 83 mV/dec for P-MOSFETs. The SPI technology maintains a low impurity concentration in the well (less than 5×10 ¹⁶ cm^-3). The drain junction capacitance is decreased by 36% for N-MOSFETs and by 41% for P-MOSFETs, compared to conventional LDD devices, which results in high-speed circuit operation. The delay time per stage of a 51-stage dual-gate CMOS ring oscillator is 50 ps with a supply voltage of 3.3 V and a gate length of 0.36 μm, and 40 ps with a supply voltage of 2.5 V and a gate length of 0.21 μm     

The effects of source/drain resistance on deep submicrometer deviceperformance

As MOSFET channel lengths approach the deep-submicrometer regime, performance degradation due to parasitic source/drain resistance (R _sd) becomes an important factor to consider in device scaling. The effects of R_sd on the device performance of deep-submicrometer non-LDD (lightly doped drain) n-channel MOSFETs are examined. Reduction in the measured saturation drain current (R_sd=600 Ω-μm) relative to the ideal saturation current (R_sd=0.0 Ω-μm) is about 4% for L_eff=0.7 μm and T_ox =15.6 nm and 10% for L_eff=0.3 μm and T _ox=8.6 nm. Reduction of current in the linear regime and reduction of the simulated ring oscillator speed are both about three times higher. The effect of salicide technologies on device performance is discussed. Projections are made of the ultimate achievable performance     

Novel in-situ doped polysilicon emitter process with burieddiffusion source (BDS)

An in-situ doped polysilicon emitter process for very shallow and narrow emitter formation and minimum emitter resistance is presented. An in-situ doped film was imbedded between two undoped poly spacer layers as a buried diffusion source (BDS) to reduce the emitter resistance and to form a high-quality poly/monosilicon interface. Transistors with an emitter area of 0.25 μm×0.25 μm and with nearly ideal I -V characteristics were fabricated. A cutoff frequency of 53 GHz and a minimum ECL gate delay of 26 ps were achieved using BDS poly emitter transistors with an emitter area of 0.35 μm×4.0 μm     

A high-performance 0.5-μm BiCMOS technology for fast 4-Mb SRAMs

A high-performance 0.5-μm BiCMOS technology has been developed. Three layers of polysilicon are used to achieve a compact four-transistor SRAM bit cell size of less than 20 μm² by creating self-aligned bit-sense and V_ss contacts. A WSi_x polycide emitter n-p-n transistor with an emitter area of 0.8×2.4 μm² provides a peak cutoff frequency (f_T) of 14 GHz with a collector-emitter breakdown voltage (BV_CFO) of 6.5 V. A selectively ion-implanted collector (SIC) is used to compensate the base channeling tail in order to increase f_T and knee current without significantly affecting collector-substrate capacitance. ECL gate delays as fast as 105 ps can be obtained with this process     

A 4.2-ps ECL ring-oscillator in a 285-GHz fMAX SiGetechnology

This letter reports on the room temperature operation of a conventional SiGe bipolar ECL ring oscillator with a minimum stage delay of 4.2 ps for ~250 mV single ended voltage swing. To our knowledge, this is the lowest reported delay for a gate fabricated using transistor devices. The circuit uses 0.12 × 2 μm² emitter size SiGe n-p-n transistors with a room temperature f_T of 207 GHz and f_MAX (unilateral gain extrapolation) of 285 GHz. The ring oscillator was studied as a function of various device and circuit parameters and it was found that minimum delay is more dependent on the parasitic resistance and capacitance in the n-p-n device than on pure transit time across the device     

A high-speed bipolar technology featuring self-aligned single-polybase and submicrometer emitter contacts

An experimental bipolar transistor structure with self-aligned base-emitter contacts formed using one polysilicon layer is presented with geometries and frequency performance comparable to those of double-polysilicon structures. This structure, called STRIPE (self-aligned trench-isolated polysilicon electrodes), provides a 0.2-μm emitter-base polysilicon contact separation. A 0.4-μm emitter width is achieved with conventional 0.8-μm optical lithography. Scaling of the emitter width of 0.3 μm has been performed with minimal degradation of device performance, and scaling of the emitter width pattern to 0.2 μm has been demonstrated. These dimensions are the smallest achieved in single-polysilicon structures with polysilicon base contacts and are comparable to those achieved in double-polysilicon structures. The STRIPE structure has been used to fabricate transistors with f_t as high as 33.8 GHz     

BiCMOS technology with 60 GHz n-p-n bipolar and 0.25 μm CMOS

A BiCMOS technology has been developed that integrates a high-performance self-aligned double-polysilicon bipolar device into an advanced 0.25 μm CMOS process. The process sequence has been tailored to allow maximum flexibility in the bipolar device design without perturbation of the CMOS device parameters. Thus, n-p-n cutoff frequencies as high as 60 GHz were achieved while maintaining a CMOS ring oscillator delay per stage of about 54 ps at 2.5 V supply comparable to the performance in the CMOs-only technology. BiCMOS and BiNMOS circuits were also fabricated. BiNMOS circuits exhibited ≈45% delay improvement compared to CMOS-only circuits under high load conditions at 2.5 V     

High-performance 0.07-μm CMOS with 9.5-ps gate delay and 150 GHzfT

We report room-temperature 0.07-μm CMOS inverter delays of 13.6 ps at 1.5 V and 9.5 ps at 2.5 V for an SOI substrate; 16 ps at 1.5 V and 12 ps at 2.5 V for a bulk substrate. This is the first room-temperature sub-10 ps inverter ring oscillator delay ever reported. PFETs with very high drive current and reduction in parasitic resistances and capacitances for both NFETs and PFETs, realized by careful thermal budget optimization, contribute to the fast device speed. Moreover, the fast inverter delay was achieved without compromising the device short-channel characteristics. At V_dd=1.5 V and I_off ~2.5 nA/μm, minimum L_eff is about 0.085 μm for NFETs and 0.068 μm for PFETs. PFET I_on is 360 μA/μm, which is the highest value ever reported at comparable V_dd and I_off. The SOI MOSFET has about one order of magnitude higher I_off than a bulk MOSFET due to the floating-body effect. At around 0.07 μm L_eff, the NFET cut-off frequencies are 150 GHz for SOI and 135 GHz for bulk. These performance figures suggest that subtenth-micron CMOS is ready for multi-gigahertz digital circuits, and has good potential for RF and microwave applications     

Deep-submicrometer CMOS technology with reoxidized or annealednitrided-oxide gate dielectrics prepared by rapid thermalprocessing

Deep submicrometer CMOSFETs with re-annealed nitride-oxide gate dielectrics have been demonstrated to satisfy 3.3-V operation, unlike conventional oxide FETs. The 1/4-μm re-annealed nitrided-oxide CMOS devices achieve (1) an improved saturation transconductance g _m of ~250 μS/μm for n-FETs together with acceptably small degradation in p-FET g_m resulting in a CMOS gate delay time of 55 ps/stage comparable or superior to the device/circuit performance of oxide FETs, and (2) device lifetimes improved by ~100 times to exceed 10 years with respect to both ON- and OFF-state hot-carrier reliability for n-FETs as well as gate-dielectric integrity together with unchanged p-FET hot-carrier reliability, all at 3.3-V operation. To achieve these CMOS performance/reliability improvements, both a light nitridation and subsequent re-annealing in O ₂ (reoxidation) or in N₂ (inert-annealing) are found to be crucial     

An Amorphous Silicon Local Interconnection (ASLI) CMOS with Self-Aligned Source/Drain and Its Electrical Characteristics

A CMOS device which has an extended heavily-doped amorphous silicon source/drain layer on the field oxide and an amorphous silicon local interconnection (ASLI) layer in the self-aligned source/drain region has been studied. The ASLI layer has some important roles of the local interconnections from the extended source/drain to the bulk source/drain and the path of the dopant diffusion sources to the bulk. The junction depth and the area of the source/drain can be controlled easily by the ASLI layer thickness. The device in this paper not only has very small area of source/drain junctions, but has very shallow junction depths than those of the conventional ones. The electrical characteristics of this device are as good as those of the conventional CMOS device. An operating speed, however, is enhanced significantly compared with the conventional ones, because the junction capacitance of the source/drain is reduced remarkably due to the very small area of source/drain junctions. For a 71-stage unloaded CMOS ring oscillator, 128 ps/gate has been obtained at power supply voltage of 3.3 V. Utilizing this proposed structure, a buried channel PMOS device for the deep submicron regime, known to be difficult to implement, can be fabricated easily.     

A new fabrication technology for AlGaAs/GaAs HEMT LSIs using InGaAsnonalloyed ohmic contacts

The authors studied the nonalloyed ohmic characteristics of HEMTs (high electron mobility transistors). At high integration levels, nonalloyed ohmic contacts were found to have two advantages: an extremely short ohmic length with low parasitic source series resistance and direct connection between the source/drain and gate with the same metal. The propagation delay in a ring oscillator with a single-metal source/drain and gate formed simultaneously was 37 ps/gate (L _g=0.9 μm). The very short ohmic metal contacts and just three contact holes made it possible to reduce the memory cell area greatly. The cell is 21.5×21.5 μm², one of the smallest ever reported for a GaAs-based static RAM. Using smaller load HEMTs or resistor loads in the memory cell, combined with nonalloyed ohmic technology with quarter- or subquarter-micrometer-gate HEMTs it is possible to fabricate a very-high-speed LSI such as a 64-kb static RAM with a reasonable chip size     

Inverter performance of 0.10 μm CMOS operating at roomtemperature

The switching performance of 0.10 μm CMOS devices operating at room temperature has been discussed on the basis of both experimental and simulated results. The measured propagation delay time of a 0.10 μm gate length CMOS has been quantitatively divided into intrinsic and parasitic components for the first time. The results have shown that the drain junction capacitance strongly affects the propagation delay time in the present 0.10 μm CMOS. The switching performance of a 0.10 μm ground rule CMOS has been simulated by using device parameters extracted from the experimental results. In the 0.10 μm ground rule CMOS, it has been shown that an increase of the contact resistance will degrade the propagation delay time, which is one of the most essential problems in further device miniaturization. It has been also demonstrated that even if the specific contact resistance ρ_c is reduced to be less than 1×10^-7 Ω cm, further reduction of the gate overlap capacitance C_ov will be required to achieve the propagation delay time to be less than 10 ps in the 0.10 μm ground rule CMOS at room temperature     

Experimental high performance sub-0.1 μm channel nMOSFET's

Very high performance sub-0.1 μm channel nMOSFET's are fabricated with 35 Å gate oxide and shallow source-drain extensions. An 8.8-ps/stage delay at V_dd=1.5 V is recorded from a 0.08 μm channel nMOS ring oscillator at 85 K. The room temperature delay is 11.3 ps/stage. These are the fastest switching speeds reported to date for any silicon devices at these temperatures. Cutoff frequencies (f_T) of a 0.08 μm channel device are 93 GHz at 300 K, and 119 GHz at 85 K, respectively. Record saturation transconductances, 740 mS/mm at 300 K and 1040 mS/mm at 85 K, are obtained from a 0.05 μm channel device. Good subthreshold characteristics are achieved for 0.09 μm channel devices with a source-drain halo process     

SOI CMOS器件研究

利用0.35μm工艺条件实现了性能优良的小尺寸全耗尽的器件硅绝缘体技术(SOI)互补金属氧化物半导体(FD SOI CMOS)器件,器件制作采用双多晶硅栅工艺、低掺杂浓度源/漏(LDD)结构以及突起的源漏区。这种结构的器件防止漏的击穿,减小短沟道效应(SCE)和漏感应势垒降低效应(DIBL);突起的源漏区增加了源漏区的厚度并减小源漏区的串联电阻,增强了器件的电流驱动能力。设计了101级环形振荡器电路,并对该电路进行测试与分析。根据在3V工作电压下环形振荡器电路的振荡波形图,计算出其单级门延迟时间为45ps,远小于体硅CMOS的单级门延迟时间。     

Self-aligned silicide technology for ultra-thin SIMOX MOSFETs

The salicide technology using rapid thermal annealing was applied to MOSFETs on thin-film SOI. Since the SOI film was limited to a thickness of less than 100 nm, the silicidation reaction between Ti and Si atoms on the SOI surface exhibited new features that depended on the initial thickness of the deposited Ti. There was an optimum thickness of as-deposited Ti on silicidation due to the restricted thickness of the Si layer. Beyond the optimum point, the region adjacent to the silicided Si layer works as a Si source to assure stoichiometric TiSi₂. The subthreshold slopes and carrier mobilities were not changed by the salicide process. Junction leakage characteristics were slightly degraded; however, the change was small enough for device application. The influence on AC characteristics was well demonstrated for a high-speed CMOS ring oscillator with a gate length of 0.7 μm. The minimum delay time/stage was 46 ps/stage at 5 V. This gives 1.8 times higher speed operation than the controlled bulk CMOS ring oscillators with the same design rule     

High-speed and large noise margin tolerance E/D logic gates withLDD structure DMTs fabricated using selective RIE technology

The authors describe a novel design concept for enhancement (E) and depletion (D) mode FET formation using i-AlGaAs/n-GaAs doped-channel hetero-MISFET (DMT) and a novel self-aligned gate process technology for submicrometer-gate DMT-LSIs based on E/D logic gates. 0.5-μm gate E-DMTs (D-DMTs) with a lightly doped drain (LDD) structure show an average V_t of 0.18 (-0.46) V, a V_t standard deviation of 22.6 (24.9) mV, and a maximum transconductance of 450 (300) mS/mm. The V_t shift is less than 50 mV with a decrease in gate length down to 0.5 μm. The gate forward turn-on voltage V_f is more than 0.9 V, i.e. about 1.6 times that for MESFETs. This superiority in V _f, preserved in the high-temperature range, leads to an improvement in noise margin tolerance by a factor of three. In addition, 31-stage ring oscillators operate with a power consumption of 20 (1.0) mW/gate and a propagation delay of 4.8 (14.5) ps/gate. Circuit simulation based on the experimental data predicts 140 ps/gate and 1 mW/gate for DMT direct-coupled FET logic circuits under standard loading conditions. DMTs and the technology developed here are very attractive for realizing low-power and/or high speed LSIs     

采用新的抬高源漏工艺技术制作的全耗尽SOI CMOS器件和电路

采用新的工艺技术,成功研制了具有抬高源漏结构的薄膜全耗尽SOI CMOS器件.详细阐述了其中的关键工艺技术.器件具有接近理想的亚阈值特性,nMOSFETs和pMOSFETs的亚阈值斜率分别为65和69mV/dec.采用抬高源漏结构的1.2μm nMOSFETs的饱和电流提高了32%,pMOSFETs的饱和电流提高了24%.在3V工作电压下101级环形振荡器电路的单级门延迟为75ps.     

A high-speed and highly uniform submicrometer-gate BPLDD GaAsMESFET for GaAs LSIs

The authors present formation conditions for ion-implanted regions of a GaAs buried p-layer lightly doped drain (BPLDD) MESFET that can improve short-channel effect, V_th uniformity, and FET operating speed, simultaneously. For 0.7-μm gates, a Mg⁺ dose of 2×10¹² cm^-2 at 300 keV and a Si⁺ dose of 2×10¹² cm^-2 at 50 keV are suitable for the p layer and n' layer, respectively. A σV _th of 7 mV is realized. Gate-edge capacitance of the 0.7-μm-gate BPLDD that consists of both overlap capacitance and fringing capacitance is successfully reduced to 0.5 fF/μm, which is about 50% of that of a non-LDD buried p-layer (BP) FET. Another parasitic capacitance due to the p-layer was found to have less effect on the speed than the gate-edge one. Consequently, the gate propagation delay time of the BPLDD can be reduced to 15 ps at power dissipation of 1 mW/gate, which is about 65% of that of a BP. Applying the 0.7-μm-gate BPLDD to 16-kb SRAMs, the authors have obtained a maximum access time of less than 5 ns with a galloping test pattern     

A high-speed buried channel MOSFET isolated by an implanted silicon dioxide layer

This paper describes a high-speed buried channel MOSFET dielectrically isolated from the substrate through the use of oxygen implantation technology. An implanted silicon dioxide layer is formed just beneath the surface. An n-type epitaxial layer is grown on the remaining thin single-crystal layer at the surface. Then, buried channel MOSFET's are formed on the n-type layer. The interface between the implanted SiO2and the upper silicon is abrupt, and the interface charge density is 6.9 × 10¹⁰cm^-2. The effective carrier mobility calculated from the drain conductance is 750 cm²/V . s. Leakage current which should be inherent in this device structure can not be observed. Submicron MOSFET's show much smaller threshold voltage shifts than conventional ones, and this agrees with the results of two-dimensional numerical calculation. A ring oscillator composed of MOSFET's with 1-µm channel length shows a minimum delay time of 95 ps and a power delay product of 310 fJ at VDDof 15 V.