Optimum tapered buffer

Driver stages in MOS circuitry have been extensively investigated during the last decade. recently a tapering rule for CMOS buffers was derived showing that the tapering factor (β) is determined by the ratio of output to input capacitance. The derivation fails to account for the correlation between the short-circuit current and β. As a result, the derived formula consistently overpredicts the value of optimum β, especially for large input/output capacitance ratios. The authors present a modified formula and a method to account for the effect of the short-circuit current that is viable for buffer stages over a wide range of output/input capacitance ratios; this newly derived formula accurately predicts the optimum tapering factors for BiCMOS as well as CMOS buffer chains     

Low-power clock-deskew buffer for high-speed digital circuits

An IC containing four clock deskew buffers using the delay-locked-loop technology has been fabricated in a 0.6 μm single poly double metal CMOS process. The core chip area is 0.9×0.9 mm ². The maximum operating frequency is 80 MHz, and the total power dissipation of the four deskew buffers is 59 mW for a 3 V supply voltage. The maximum clock skew after deskewing is less than 300 ps, and the peak-to-peak clock jitter is less than 170 ps. The deskew range is 0.5-3.8 ns     

Novel frame buffer pixel circuits for liquid-crystal-on-silicon microdisplays

A 32 /spl times/ 16 liquid-crystal-on-silicon (LCOS) backplane with novel frame buffer pixels is designed and fabricated using the AMI Semiconductor's 0.5-/spl mu/m double-poly triple-metal CMOS process. The three novel pixel circuits described herein increase the brightness of an XGA LCOS microdisplay by at least 36% without sacrificing image contrast ratio. The increase of brightness is attributed to maximizing overall image view time, allowing an image to be displayed at full contrast while the next image is buffered onto the backplane. The new circuits achieve this by removing charge sharing and charge inducement problems shown in previously proposed frame buffer pixel circuits. Voltages on the pixel electrodes measured through rail-to-rail operational amplifiers with negative feedback vary from 0 to 4.25 V (6-V power source). All data voltage levels remain constant over a frame time with less than 1% drop, thus ensuring maximum contrast ratio. Modeling and experimental measurement on the fabricated chip show that these pixel circuits outperform all others to date based on storage time, data storage level, and potential for highest contrast ratio with maximum brightness.     

Optimum load device for DMOS integrated circuits

Depletion-mode load devices can be integrated with DMOS transistors without any extra diffusions or implantation processing steps by judicious choice of the substrate crystal orientation and resistivity. For low voltage operation, <1,1,1> crystal orientation should be used. The <1,1,1> crystal orientation also yields a higher transconductance for the DMOS transistor than the <1,0,0> orientation. The geometry of the load device and the DMOS transistor can be made ratioless to conserve area. Self-aligned gates, hitherto considered incompatible with DMOS transistors, have been incorporated in the structure. The experimental DMOS invertors, using a conservative design, have achieved 4-ns propagation delay, 1.3-V operation and 2-pJ propagation delay-power dissipation product.     

Design of flashlamp driving circuits

The problem of design of single mesh circuits for driving xenon flashlamps has been considered in detail. The normalized nonlinear differential equationI'pm alpha |I|^{1/2} + intmin{0}max{tau} I dtilde{tau} = 1for this system has been solved by digital computer and the solutions are presented. Since the equation is linear in time, though nonlinear in current, it is possible to provide explicit design equations. With them, for a given lamp type, energy input, pulse duration, and pulse shape factor, the inductance, capacitance, and operating voltage are easily determined. A procedure for estimating circuit losses is also presented.     

An efficient CMOS buffer for driving large capacitive loads

A CMOS class AB high-drive buffer suitable for driving large capacitive and moderate resistive loads is presented. The buffer, designed using 3-/spl mu/m technology, occupies only 100 mils/SUP 2/ of area and dissipates 1.5 mW of DC power from a /spl plusmn/2.5-V supply, yet it is capable of driving a 5000-pF capacitor at over 100-kHz clocking frequency. The buffer achieves good slew rate and fast settling by entering into a high-drive state during slewing and returning to a low-power wide-band state during the settling period. Unconditional stability is attained when C/SUB L//spl ges/100 pF and R/SUB L//spl ges/10 k/spl Omega/. Total harmonic distortion is below 0.5% for over 70% of the full supply range.     

Optimum design of nonlinear microwave circuits

This paper reports a direct optimization method of nonlinear circuits. The procedure consists in determining in the power space, a surface including all the extremum allowed powers at terminal ports of each nonlinear component of the circuit. According to the required nonlinear function, an appropriate choice of the tangent planes to this surface allows to calculate the optimum loads for the nonlinear components. This method optimizes the parameters of nonlinear devices without any constraint on the circuit. A small signal analysis is then taken in order to deduce the optimum performance of the nonlinear designed circuit. The realization of a single balanced diode mixer has shown good agreement between the calculated values and the experimental results     

Modelling of coupled interconnect lines for integrated circuits

A coupled interconnect model is developed using even mode and odd mode capacitance analysis. Signal coupling is presented in terms of interconnect width, substrate thickness, interconnect line spacing, and frequency. Picosecond photoconductor based measurements of coupled transmission lines on the integrated circuit support the even and odd mode signal transmission simulation results. SPICE circuit simulation is used to demonstrate the model utility and explore the sensitivity of the self- and mutual capacitances and inductances in signal crosstalk.     

III-nitride-based planar lightwave circuits for long wavelength optical communications

Planar lightwave circuits based on III-nitride wide-bandgap semiconductors are proposed and the feasibility of developing III-nitride-based novel photonic integrated circuits for applications in fiber-optical communications is discussed. III-nitrides have low attenuation in the near-infrared wavelength region because of their wide bandgaps, while as semiconductors their refractive indexes can be modulated by carrier injection. III-nitrides are also well known for their ability to operate at high temperatures, high power levels and in harsh environments. These characteristics make III-nitrides ideal candidates for tunable optical phased-array (PHASAR) devices for optical communications. We have characterized the optical properties of Al/sub x/Ga/sub 1-x/N epilayers in the 1550-nm wavelength region, including the refractive indexes and the impact of Al concentrations. Single-mode ridged optical waveguide devices using GaN-AlGaN heterostructures have been designed, fabricated and characterized for operation in the 1550-nm wavelength window. The birefringence of wurtzite GaN grown on sapphire substrate has been observed. Refractive indexes were found to be different for signal optical field perpendicular and parallel to the crystal c axis (n/sub /spl perp// /spl ne/ n/sub ///). More importantly, we found an approximately 10% change in the index difference /spl Delta/n=n/sub ///-n/sub /spl perp// with varying the waveguide orientation within the c plane, and a 60/spl deg/ periodicity was clearly observed. This is attributed to the hexagonal structure of the nitride materials. Various functional waveguide devices have been realized, including 2/spl times/2 directional couplers and eight-wavelength array-waveguide gratings. Theoretical predictions of temperature sensitivity and the efficiency of carrier-induced refractive change are provided.     

Analysis of printed transmission lines for monolithic integrated circuits

Planar transmission lines formed with MIS and Schottky barrier contacts are analysed based on the spectral domain technique. Depending on the frequency and the resistivity of the substrates, three different types of fundamental modes are predicted. The calculated slow-wave factors and attenuation constants agree well with experimental results.     

New equivalent circuits for inhomogeneous coupled lines withsynthesis applications

Equivalent circuits for inhomogeneous coupled-line sections are presented which enable cascade synthesis procedure to be applied to the design of very-broadband inhomogeneous filters. Here, the term inhomogeneous means that the even and odd modes have different phase velocities and different electrical lengths. The method has been implemented in the design of inhomogeneous high-pass filters constructed in suspended substrate stripline, when the even-mode characteristic impedance is much greater than the odd-mode characteristic impedance. An approximate but highly accurate synthesis of a 3:1 bandwidth-inhomogeneous distributed high-pass filter is described. The procedure is almost purely analytic, and computer-aided design is required only for fine tuning adjustments. The theoretical feasibility of designing such filters for upper-pass bandwidths of greater than 8:1 is demonstrated     

Noise in interconecction lines for submicrometer CMOS integrated circuits

The growing use of high performance portable systems is the main driving force for the significant advance in the technology of VLSI-CMOS integrated circuits. This advance has been carried out through scaling the transistor and interconnection sizes. However, as the transistor's size and interconnections are getting smaller, the signal integrity is becoming a critical issue. Therefore it is required to develop noise tolerant design circuit techniques in order to enhance the noise tolerance. In addition, these techniques should have a minimum impact on the circuit performance. In this paper, the noise immunity of dynamic logical circuits as the technology scales down is analyzed by using a reliable scaling scenario, and a new noise tolerant design technique is proposed. Prototype circuits implementing the proposed technique have been designed and fabricated. A one-bit carry look-ahead adder was designed using 0.35 mm CMOS-AMS technology. The experimental results show that the design technique here presented, results in an improvement of the ANTE by a factor of 3.4X when compared with the conventional TSPC, and an improvement by a factor of 1.7X when compared with the best noise tolerant technique currently published.     

Modeling of loaded uniform RC lines for computer-aided analysis

A simple model for loaded uniformly distributed RC (URC) lines is presented. The author presents an analytical solution based on finding the approximate poles of the transfer function of the loaded URC line, over a wide range of the load and the line constants. Based on this analytical solution a lumped network with three passive elements only can be used for modeling the performance of URC lines loaded by a parallel RC combination. This model can be easily implemented for computer-aided analysis of circuits comprising URC lines     

Generalised theory of uniform transmission lines

The conventional circuit theory of uniform two-conductor transmission lines (TEM mode) assumes that at any cross-section the current in one conductor is equal and opposite to that in the other. This is not necessarily true, and even when it is true the resulting theory does not permit solution of some simple problems such as evaluation of the voltage difference between two points on the same conductor. The author presents a more general circuit theory which does permit solution of such problems and does not demand current balance. He shows that when there is current imbalance the expressions for voltage contain a term which depends linearly upon line length, as well as the familiar hyperbolic function terms     

Surface-wave long delay lines

Recent results obtained with helical surface-acoustic-wave (SAW) delay lines of large time delay and bandwidth are described. Both unguided and guided propagation are involved, with time delays up to one millisecond and bandwidths up to 65 MHz being observed. Fiber delay lines of both capillary and cladded types are also discussed. The potential for future application of SAW delay lines of large time-bandwidth product to high-speed signal-and data-processing systems is considered.     

New multilayer planar transmission lines for microwave andmillimeter-wave integrated circuits

New types of planar transmission lines employing multilayer structures are proposed for possible applications in microwave and millimeter-wave integrated circuits. Detailed investigations are presented through numerical results calculated using the spectral domain technique. The newly proposed transmission lines have many attractive features such as a large impedance range, flexibility and ability to realize complicated, densely packed integrated circuits, as well as miniaturization through the use of thin dielectric layers. Additionally, they possess all of the inherent advantages of the CPW and microstrip line. Their use in microwave circuits is exemplified through a low-pass filter realized using the new slot-coplanar lines with less than 0.5-dB insertion loss and better than 20-dB return loss. The filter's measured and calculated performances also agree well     

Minimization of MOSFET gate leakage current in buffer amplifier circuits

It is shown that the components of gate leakage current of a MOSFET used in a previously described unity gain buffer amplifier may be reduced to a minimum under static and dynamic conditions. Modified packaging and novel biasing techniques can minimize both extrinsic and intrinsic components of gate leakage current at the input to the amplifier.     

Synthetic quasi-TEM meandered transmission lines for compacted microwave integrated circuits

This paper presents a two-dimensional transmission line (2-D TL) that supports quasi-TEM propagation mode and reduces problems associated with compacted meandering of microstrip (MS) on propagation constants and the characteristic impedances commonly observed in conventional one-dimensional MSs. The proposed 2-D TL comprises two layers of metallic surfaces on either side of a dielectric substrate. The top metal surface is a meandered connection of a unit cell with a central patch and connecting arms. The bottom surface is a meshed 2-D periodical ground plane, whose etched portion complements the patch portion of the top surface, forming a complementary-conducting-strip (CCS) TL, enabling a combination of an MS and MS with the tuning septa in a unit cell. Both theoretical and experimental investigations of the CCS TL agree well and demonstrate that it is much less susceptible to the effects of meanderings on the propagation constant and characteristic impedance than an MS for the same meandered pattern. Two design examples are presented to demonstrate the potential for a CCS TL for miniaturizing microwave passive circuits with minimal losses. The first example involves a 5.4-GHz CCS four-port rat-race hybrid realized in RO4003 and reduces the area of original MS design by 87%. The second example illustrates the applicability of a CCS TL to a monolithic RF integrated circuit using a first-pass design of a 5.2-GHz CMOS oscillator incorporating a CCS TL as a resonator with an area totaling 500/spl times/600 /spl mu/m/sup 2/ including pads base on Taiwan Semiconductor Manufacturing Company's 0.25-/spl mu/m 1P5M CMOS process techniques.     

Characterization of buried microstrip lines for constructinghigh-density microwave integrated circuits

This paper describes the characterization of a guided wave structure, buried microstrip line (BMSL), which is considered to be promising for constructing high-density microwave and millimeter-wave integrated circuits because of its high isolation characteristics. The BMSL includes a dielectric medium surrounded by ground conductor walls and a strip conductor on the top of the dielectric. The BMSL structure is characterized by the two methods, the rectangular boundary division (RBD) method and the finite-difference time-domain (FDTD) method. The RBD method is employed to obtain basic parameters of the BMSL such as characteristic impedances and coupling coefficients over a wide range of line sizes taking advantages of its high calculation efficiency. On the other hand, the FDTD method has been used for more detailed characterization such as the frequency performances of stub matching circuits. The FDTD method is also used to confirm the validity of the quasi-TEM wave approximation which the RBD is based on. The analysis results reveal that the BMSL structure possesses much lower coupling coefficients than a conventional microstrip line does, from -15 dB to -100 dB depending on their burial depths     

Natural frequencies of piecewise uniform transmission lines

A transmission line composed of a number of cascaded uniform lines with different characteristic impedances and lengths is considered. Approximate expressions for the chain parameters and natural frequencies useful to a variational synthesis are given.