LPCVD制备氮化硅薄膜工艺

氮化硅（摘要）薄膜具有许多优良特性,在半导体、微电子和MEMS领域应用广泛。本文简要介绍了利用CVD方法制备摘要薄膜以及Si3N4薄膜的特性,详细介绍了低压化学气相淀积（Low Pressure Chemical Vapor Deposition）LPCVD制备氮化硅的工艺。工艺制备中通过工艺参数的调整使批量生产的淀积膜的均匀性达到技术要求。     

正交试验法优选LPCVD最佳工艺

本文采用正交试验法,经过次数不多的试验,在一台未能正常使用的LPCVD设备上,优选出淀积氮化硅薄膜的最佳工艺.上述工艺找到了淀积氮化硅的一些规律,氮化硅薄膜在抗氧化能力、腐蚀速率、折射率.薄膜生长速率等方面都获好的水平.本方法也可用于半导体工艺改革和新产品的研制.     

CeO2高K栅介质薄膜的制备工艺及其电学性质

研究了CeO2作为高K（高介电常数）栅介质薄膜的制备工艺,深入分析了衬底温度,淀积速率,氧化压等工艺条件和利用N离子轰击氧化Si衬底表面工艺对CeO2薄膜的生长及其与Si界面结构特征的影响,利用脉冲激光淀积方法在Si(100)衬底生成了具有（100）和（111）取向的CeO2外延薄膜,研究了N离子轰击氮化Si衬底表面处理工艺对Pt/CeO2/Si结构电学性质的影响,研究结果显示,利用N离子轰击氮化Si表面／界面工艺不仅影响CeO2薄膜的生长结构,还可以改善CeO2与Si界面的电学性质。     

用SiH_4-NH_3体系减压化学汽相淀积氮化硅薄膜的工艺研究

近些年来,使用扩散炉由减压方式产生的化学汽相淀积技术(简称LPCVD技术),在一些技术发达的国家中已有很大的突破和进展,国内对这项技术也引起了极大的重视,并且取得了较快的进展。LPCVD技术所以能被迅速的接受,是由于它采用密集垂直装片方式,生产量大,效率高。同时,它在一个固定的电阻炉内硅片直接受热,在低压下可以导致淀积非常均匀的薄膜厚度和组份。 采用LPCVD技术淀积多晶硅、氮化硅、二氧化硅和磷硅玻璃等薄膜,近些年国外不断有所报导。表1列出了各种淀积膜的现状。 近两年来用LPCVD技术淀积多晶硅、氮化硅薄膜国内也有些报导。特别是LPCVD多晶硅报导的较多,进展较显著,问题点也不多。而LPCVD氮化硅薄膜与多晶硅比较,生长     

CeO2高K栅介质薄膜的制备工艺及其电学性质

研究了CeO2作为高K(高介电常数)栅介质薄膜的制备工艺,深入分析了衬底温度、淀积速率、氧分压等工艺条件和利用N离子轰击氮化Si衬底表面工艺对CeO2薄膜的生长及其与Si界面结构特征的影响,利用脉冲激光淀积方法在Si(100)衬底生长了具有(100)和(111)取向的CeO2外延薄膜;研究了N离子轰击氮化Si衬底表面处理工艺对Pt/CeO2/Si结构电学性质的影响.研究结果显示,利用N离子轰击氮化Si表面/界面工艺不仅影响CeO2薄膜的生长结构,还可以改善CeO2与Si界面的电学性质.     

沟槽栅IGBT非晶Si填槽工艺研究与优化

采用低压化学气相淀积(LPCVD)非晶Si填槽工艺代替LPCVD多晶Si填槽工艺,对沟槽绝缘栅双极型晶体管(IGBT)器件的沟槽进行非晶Si回填,研究并优化了高深宽比非晶Si填槽工艺.分析了LPCVD非晶Si工艺参数如PH3体积流量和沉积时间等对LPCVD非晶Si填槽能力的影响,通过调制P掺杂浓度和优化非晶Si淀积时间,得到槽底侧壁与槽口侧壁非晶Si厚度差值为0.022 μm的基准非晶Si填槽工艺,优化了LPCVD非晶Si反复多次填槽工艺条件.结果表明,采用优化后的工艺可实现沟槽栅IGBT器件沟槽非晶Si无缝回填,器件的栅极电阻降低了0.150 Ω,漏电流降低了1.408 nA,成品率提升了0.4％.     

CeO_2高K栅介质薄膜的制备工艺及其电学性质

研究了 Ce O2 作为高 K (高介电常数 )栅介质薄膜的制备工艺 ,深入分析了衬底温度、淀积速率、氧分压等工艺条件和利用 N离子轰击氮化 Si衬底表面工艺对 Ce O2 薄膜的生长及其与 Si界面结构特征的影响 ,利用脉冲激光淀积方法在 Si(10 0 )衬底生长了具有 (10 0 )和 (111)取向的 Ce O2 外延薄膜 ;研究了 N离子轰击氮化 Si衬底表面处理工艺对 Pt/ Ce O2 / Si结构电学性质的影响 .研究结果显示 ,利用 N离子轰击氮化 Si表面 /界面工艺不仅影响 Ce O2 薄膜的生长结构 ,还可以改善 Ce O2 与 Si界面的电学性质     

LPCVD氮化硅薄膜工艺研究

氮化硅薄膜在半导体器件制造、薄膜加工、MEMS中有着广泛的应用。利用低压化学气相淀积（LPCVD）技术,在800℃温度下,不同的工艺气体流量比生成的氮化硅薄膜,其薄膜成份中的硅氮比会有不同,造成薄膜特性也不同。通过测试氮化硅薄膜在缓冲腐蚀液（BOE）中的腐蚀速率,来推定氮化硅所含硅氮成分,寻找出适合生产的最佳工艺条件。     

运用低温Purge降低LPCVD氮化硅工艺的微粒污染

LPCVD制备的氮化硅薄膜具有良好的阶梯覆盖性,但是这种薄膜的应力偏高,在石英工艺腔管使用到8μm后易形成剥落微粒。特别是半导体工艺发展到了亚微米阶段,这一问题对于产品良率的影响也越来越大。文中以垂直式LPCVD设备为研究对象,通过利用晶圆冷却时间,运用降低工艺腔体温度并使用N2Purge的方法来改善微粒状况。通过大量对比实验来得出最优温度设定。运用这种方式不但改善了LPCVD设备制备氮化硅膜的微粒状况,还延长了设备的维护周期,增加设备利用时间。     

PECVD淀积Si3N4作为光刻掩膜版的保护膜

采用等离子增强化学汽相淀积(PECVD)方法淀积Si3N4薄膜作为光刻掩膜版的保护膜,可以降低掩膜版受损程度,延长使用寿命.分析了Si3N4膜厚的选取要求,给出了PECVD淀积Si3N4膜的工艺条件.实际制作了带有Si3N4保护的光刻掩膜版,并与不带Si3N4保护的掩膜版的使用情况做了对比.结果表明,带有Si3N4保护的光刻掩膜版的使用寿命可明显延长2倍以上.     

Work function of boron-doped polycrystallineSixGe1-x films

The work function of p-type polycrystalline Si_xGe_1-x films deposited by LPCVD using SiH₄ and GeH₄ was determined by CV measurements on MOS structures. Boron was introduced in the Si_xGe_1-x films either exsitu by ion implantation or insitu by adding B₂H₆ in the reactants during film deposition. The work function of the Si_xGe_1-x films is found to decrease as the Ge content increases; it is 5.16 eV for Si, 4.76 eV for Si_0.49Ge_0.51, and 4.67 eV for Ge. The work function of the Si and Ge films coincides well with that of single crystalline Si and Ge, respectively. It is also found that a thin Si adhesion layer of about 3 nm (nominal thickness), deposited prior to the Si_xGe_1-x, has a negligible effect on the work function determination     

ECR-PECVD制备UHF大功率管浅结芯片中Si3N4钝化膜的应用研究

利用ＥＣＲ－ＰＥＣＶＤ技术将Ｓｉ３Ｎ４薄膜成功地应用于ＵＨＦ大功率晶体管浅结芯片中的钝化膜，使芯片电特性有较好改善，完全避免了芯片后加工工序中划伤造成的芯片报废现象，提高了成品率，分析了Ｓｉ３Ｎ４膜的钝化机理。     

MgO缓冲层对Si衬底上制备Fe3Si薄膜性能的影响

采用磁控溅射方法和热加工工艺在n型Si衬底上溅射不同厚度的MgO层并制备Fe-Si薄膜层,退火后形成Fe3Si/MgO/Si多层膜结构.利用MgO缓冲层对退火时Si衬底扩散原子进行屏蔽,并分析MgO层对Fe3Si薄膜结构和电学性质的影响.通过X射线衍射仪(XRD)、扫描电子显微镜(SEM)和四探针测试仪对Fe3Si薄膜的晶体结构、表面形貌、断面形貌和电阻率进行表征与分析.研究结果表明:当MgO层厚度为20 nm时生成Fe0.9Si0.1薄膜,当厚度为50,100,150和200 nm时都生成了Fe3Si薄膜,生成的Fe3Si和Fe0.9Si0.1薄膜以(110)和(211)取向为主.随MgO缓冲层厚度增加,Si衬底扩散原子对Fe3Si薄膜的影响减小,Fe3 Si薄膜的晶格常数逐渐减小,晶粒大小趋向均匀,平均电阻率呈现先增大后减小趋势.研究结果为后续基于Fe3 Si薄膜的器件设计与制备提供了参考.     

用于微传感器中PZT压电薄膜的制备和图形化

采用溶胶-凝胶法在Si/Si3N4/Poly-Si/Ti/Pt基片上制备PZT压电薄膜, 为了选择更适合微电子机械系统(MEMS)器件的压电薄膜,采用一般热处理和快速热处理对锆钛酸铅(PZT)压电薄膜进行干燥和结晶.首先,采用V(H2O):V(HCL):V(HF)＝280 mL:120 mL:4drops(4滴HF溶液)配比的腐蚀液在室温下对未结晶的PZT压电薄膜进行了湿法腐蚀微细加工;然后,对图形化好的压电薄膜进行再结晶的热处理,实验结果表明这种方法可用于压电薄膜微器件的制备.     

Structural,optical, and surface science studies of 4H-SiC epilayers grown by low pressure chemical vapor deposition

A series of epitaxial 4H-SiC thin films grown by low pressure chemical vapor deposition (LPCVD) were characterized using various techniques, including x-ray diffraction (XRD), Fourier transform infrared (FTIR) reflectance, Raman scattering, and x-ray photoelectron spectroscopy (XPS). The epilayers were grown on heavily doped n-type 4H-SiC substrates using different gas compositions. XRD showed that the thin films were single crystal. Raman scattering identified the films to be 4H polytype. FTIR reflectivity spectra indicated improvement in the film quality over that of the substrate and atmospheric pressure-grown epilayers. XPS scans revealed the existence of Si, C, and O along with C-contaminant species in the form of CH and carbon oxides. Variations in crystalline quality, optical, and surface properties with the growth conditions were studied. This study also provides an important comparison between low and atmospheric pressure-grown 4H-SiC epilayers.     

The effect of low pressure chemical vapor deposition of silicon nitride on the electronic interface properties of oxidized silicon wafers

The effect of LPCVD Si₃N₄ film deposition on oxidized Si wafers, to form Si₃N₄/SiO₂/Si stacks, is studied using capacitance–voltage and carrier lifetime measurements. The deposition of a nitride film leads to an increase in the density of defects at the Si–SiO₂ interface, with the increase being greater the thinner the oxide. However, even the presence of a very thin intermediate oxide results in a dramatic improvement in interface properties compared to the direct deposition of the Si₃N₄ film on Si. The interface degradation occurs in the initial stages of nitride film deposition and appears to be largely the result of increased interfacial stress. Subsequent thermal treatments do not result in significant further degradation of the Si–SiO₂ interface (except for a loss of hydrogen), again in contrast to the case where the nitride films is deposited onto Si. Copyright © 2007 John Wiley & Sons, Ltd.     

SiO_2-Si_3N_4栅介质膜陷阱特性的高频C-V分析

采用高频 C-V特性测试技术 ,研究由热氧化生成的超薄 Si O2 膜和低压化学汽相淀积法制备的非均匀结构 Si3N4膜 ,两者组成的栅介质膜的陷阱特性 (包括陷阱密度、能量和空间分布深度等参数 )。结果表明 :在栅复合膜陷阱电荷非稳态释放模型下建立的高频 C-V理论及其分析方法 ,可以很好地表征实验曲线 ,并获取所需的存储陷阱分布参数     

PECVD生长氮化硅介质膜的工艺研究

对PECVD生长氮化硅介质膜的工艺条件进行了实验研究,获得了生长氮化硅介质膜的最佳工艺条件,制出了高质量的氮化硅介质膜,对样品进行了湿法腐蚀和超声实验,在显微镜下观察无膜脱落现象发生。阐述了几种工艺参数对介质膜生长的影响。     

Correlation between infrared transmission spectra and the interface trap density of SiO2 films

This work is an attempt to estimate the electrical properties of SiO₂ thin films by recording and analyzing their infrared transmission spectra. In order to study a big variety of films having different infrared and electrical properties, we studied SiO₂ films prepared by low pressure chemical vapor deposition (LPCVD) from SiH₄ + O₂ mixtures at 425 °C and annealed at 750 °C and 950 °C for 30 min. In addition thermally grown gate quality SiO₂ films of similar thickness were studied in order to compare their infrared and electrical properties with the LPCVD oxides. It was found that all studied SiO₂ films have two groups of Si–O–Si bridges. The first group corresponds to bridges located in the bulk of the film and far away from the interfaces, the grain boundaries and defects and the second group corresponds to all other bridges located near the interfaces, the grain boundaries and defects. The relative population of the bulk over the boundary bridges was found equal to 0.60 for the LPCVD film after deposition and increased to 4.0 for the LPCVD films after annealing at 950 °C. Thermally grown SiO₂ films at 950 °C were found to have a relative population of Si–O–Si bridges equal to 3.9. The interface trap density of the LPCVD film after deposition was found equal to 5.47 × 10¹² eV⁻¹ cm⁻² and decreases to 6.50 × 10¹⁰ eV⁻¹ cm⁻² after annealing at 950 °C for 30 min. The interface trap density of the thermally grown film was found equal to 1.27 × 10¹¹ eV⁻¹ cm⁻² showing that films with similar Si–O–Si bridge populations calculated from the FTIR analysis have similar interface trap densities.     

镍酸镧缓冲层的制备及对钙锶铋钛的影响

采用溶胶-凝胶(Sol-Gel)法在Si(100)衬底上制备了LaNiO3薄膜,然后在LaNiO3/Si(100)上制备了钙锶铋钛薄膜。研究了热处理工艺对LaNiO3(LNO)薄膜的影响。研究结果表明,当热分解温度为350℃、退火温度为750℃,厚为250nm时,制备的LNO薄膜的(110)衍射峰取向择优最明显,电阻率也较低,(为1.8×10-3Ω.cm)。LNO缓冲层的引入促进钙锶铋钛薄膜沿A轴方向生长,明显改善了钙锶铋钛薄膜的电性能,即剩余极化强度Pr=15.2μC/cm2,矫顽电场Ec=70kV/cm。