Nanoscale circuit implementation using tri-metal gate engineered nanowire MOSFET with gate stack for analog/RF applications

In this work, the potential benefit of tri-metal gate engineered nanowire MOSFET with gate stack for analog/RF applications is developed and presented. A systematic, quantitative investigation of main figure of merit for the device is carried out to demonstrate its improved RF/analog performance. The results show an improvement in drain current, \(I_{\mathrm{on}} /I_{\mathrm{off}}\) ratio, transconductance, unity-gain frequency (\(f_{\mathrm{T}}\)), maximum oscillation frequency (\(f_{\mathrm{max}}\)) providing superior RF performance as compared to single and dual-metal gate stack nanowire MOSFET. The suitability of the device for analog/RF applications is also analyzed by implementing the device in a low-noise amplifier circuit, and the S-parameter values are estimated.     

Ambipolar leakage suppression in electron–hole bilayer TFET: investigation and analysis

In this paper, we propose and simulate two new structures of electron–hole bilayer tunnel field-effect transistors (EHBTFET). The proposed devices are n-heterogate with \(\hbox {M}_{1}\) as overlap gate, \(\hbox {M}_{2}\) as underlap gate and employs a high-k dielectric pocket in the drain underlap. Proposed structure 1 employs symmetric underlaps (Lgs = Lgd = Lu). The leakage analysis of this structure shows that the lateral ambipolar leakage between channel and drain is reduced by approximately three orders, the OFF-state leakage is reduced by one order, and the \(I_{\mathrm{ON}}/I_{\mathrm{OFF}}\) ratio is increased by more than one order at \(V_\mathrm{{GS}}=V_{\mathrm{DS}} =1.0\) V as compared to the conventional Si EHBTFET. The performance is improved further by employing asymmetric underlaps (\(\hbox {Lgs}\ne \hbox {Lgd}\)) with double dielectric pockets at source and drain, called as proposed structure 2. The pocket dimensions have been optimized, and an average subthreshold swing of 17.7 mV/dec (25.5% improved) over five decades of current is achieved with an ON current of \(0.23~\upmu \hbox {A}/\upmu \hbox {m}\) (11% improved) in proposed structure 2 in comparison with the conventional EHBTFET. Further, the parasitic leakage paths between overlap/underlap interfaces are blocked and the OFF-state leakage is reduced by more than two orders. A high \(I_{\mathrm{ON}}/I_{\mathrm{OFF}}\,\hbox {ratio}~>10^{9}\) (two orders higher) is achieved at \(V_{\mathrm{DS}} =V_{\mathrm{GS}} =1.0~\hbox {V}\) in the proposed structure 2 in comparison with the conventional one.     

Design and structural optimization of junctionless FinFET with Gaussian-doped channel

A junctionless (JL) fin field-effect transistor (FinFET) structure with a Gaussian doping distribution, named the Gaussian-channel junctionless FinFET, is presented. The structure has a nonuniform doping distribution across the device layer and is designed with the aim of improving the mobility degradation caused by random dopant fluctuations in JL FinFET devices. The proposed structure shows better performance in terms of ON-current (\(I_{\mathrm{ON}}\)), OFF-current (\(I_{\mathrm{OFF}}\)), ON-to-OFF current ratio (\(I_{\mathrm{ON}}{/}I_{\mathrm{OFF}}\)), subthreshold swing, and drain-induced barrier lowering. In addition, we optimized the structure of the proposed design in terms of doping profile, spacer width, gate dielectric material, and spacer dielectric material.     

Analog and RF performance of doping-less tunnel FETs with $$\hbox {Si}_{0.55} \hbox {Ge}_{0.45}$$ source

This paper reports studies of a doping-less tunnel field-effect transistor (TFET) with a \(\hbox {Si}_{0.55} \hbox {Ge}_{0.45}\) source structure aimed at improving the performance of charge-plasma-based doping-less TFETs. The proposed device achieves an improved ON-state current (\(I_{{\mathrm{ON}}} \sim {4.88} \times {10}^{-5}\,{\mathrm{A}}/\upmu {\mathrm{m}}\)), an \(I_\mathrm{ON}/I_\mathrm{OFF}\) ratio of \({6.91} \times {10}^{12}\), an average subthreshold slope (\(\hbox {AV-SS}\)) of \(\sim \) \({64.79}\,{\mathrm{mV/dec}}\), and a point subthreshold slope (SS) of 14.95 mV/dec. This paper compares the analog and radio of frequency (RF) parameters of this device with those of a conventional doping-less TFET (DLTFET), including the transconductance (\(g_{{\mathrm{m}}}\)), transconductance-to-drain-current ratio \((g_\mathrm{m}/I_\mathrm{D})\), output conductance \((g_\mathrm{d})\), intrinsic gain (\(A_{{\mathrm{V}}}\)), early voltage (\(V_{{\mathrm{EA}}}\)), total gate capacitance (\( C_{{\mathrm{gg}}}\)), and unity-gain frequency (\(f_{{\mathrm{T}}}\)). Based on the simulated results, the \(\hbox {Si}_{0.55}\hbox {Ge}_{0.45}\)-source DLTFET is found to offer superior analog as well as RF performance.     

Investigation of trigate JLT with dual-<Emphasis Type="Italic">k</Emphasis> sidewall spacers for enhanced analog/RF FOMs

This paper shows the potential benefits of using the trigate junctionless transistor (JLT) with dual-k sidewall spacers to enhance analog/radio-frequency (RF) performance at 20-nm gate length. Simulation study shows that the source-side-only dual-k spacer (dual-kS) JLT can improve all analog/RF figures of merit (FOMs) compared with the conventional JLT structure. The dual-kS JLT shows improvement in intrinsic voltage gain (\(A_{V0}\)) by \(\sim \)44.58 %, unity-gain cutoff frequency (\(f_\mathrm{T}\)) by \(\sim \)7.67 %, and maximum oscillation frequency (\(f_\mathrm{MAX}\)) by \(\sim \)6.4 % at drain current \((I_\mathrm{ds}) = 10\,\upmu \hbox {A}/\upmu \hbox {m}\) compared with the conventional JLT structure. To justify the improvement in all analog/RF FOMs, it is also found that the dual-kS structure shows high electron velocity near the source region because of the presence of an additional electric field peak near the source region, resulting in increased electron transport efficiency and hence improved transconductance (\(g_\mathrm{m}\)). Furthermore, the dual-kS JLT shows a reduction in the electric field value near the drain end, thereby improving short-channel effects.     

Improvement in microwave dielectric properties of Sr<Subscript>2</Subscript>TiO<Subscript>4</Subscript> ceramics through post-annealing treatment

Sr₂TiO₄ ceramics were synthesized via the conventional solid-state reaction process, and the effects of post-annealing treatment in air on the microwave dielectric properties and defect behavior of title compound were investigated systematically. The Q?×?f values could be effectively improved from 107,000 GHz to 120,300 GHz for the specimens treated at 1450 °C for 16 h. The thermally stimulated depolarization currents (TSDC) revealed two kinds of defect dipoles [\( \left({\mathrm{Ti}}_{\mathrm{Ti}}^{\hbox{'}}-{V}_{\mathrm{O}}^{\bullet \bullet}\right) \) and \( \left({V}_{\mathrm{Sr}}^{"}-{V}_{\mathrm{O}}^{\bullet \bullet}\right) \)] and oxygen vacancies \( \left({V}_{\mathrm{O}}^{\bullet \bullet}\right) \) were considered the main defects in Sr₂TiO₄. Under a post-annealing treatment in air, the concentrations of such defects in the ceramics decreased. Meanwhile, the impedance spectrum revealed the activation energy of the grain boundaries increased. These evidences could account for the improvement of Q?×?f values. Accompanied with a high ε_r of 40.4 and a large τ_f of 126 ppm/°C, the enhanced high-Q Sr₂TiO₄ ceramics can be good candidates for applications in wireless passive temperature sensing.     

20-nm T-gate composite channel enhancement-mode metamorphic HEMT on GaAs substrates for future THz applications

In this paper, the RF and DC behaviours of a SiN-passivated 20-nm gate length metamorphic high electron mobility transistor (MHEMT) on GaAs substrate with \({\updelta }\)-doped sheets on either side of the composite channel are studied using the Synopsys TCAD tool. The 20-nm enhancement-mode MHEMT with \({\updelta }\)-doped sheets on either side of the \(\hbox {In}_{0.75}\hbox {Ga}_{0.25}\hbox {As}\)/InAs/ \(\hbox {In}_{0.75}\hbox {Ga}_{0.25}\hbox {As}\) multilayer channel shows a transconductance of 3000 mS/mm, cut-off frequency (\({f}_{\mathrm{T}}\)) of 760 GHz and a maximum-oscillation frequency (\({f}_{\mathrm{max}}\)) of 1270 GHz. The threshold voltage of the device is found to be 0.07 V. The room-temperature Hall mobilities of the two-dimensional sheet charge density (2DEG) are measured to be over \(12800\,\hbox {cm}^{2}\)/Vs with a sheet charge density larger than 4 \(\times \) \(10^{12}\,\hbox {cm}^{-2}\). These high-performance enhancement-mode MHEMTs are attractive candidates for future terahertz applications such as high-resolution radars for space research and also for low-noise wide-bandwidth amplifier for future communication systems.     

Simulation-based performance analysis of an ultra-low specific on-resistance trench SOI LDMOS with a floating vertical field plate

An ultra-low specific on-resistance \((R_\mathrm{{on,sp}})\) trench SOI LDMOS with a floating vertical field plate structure (FVFPT SOI) is proposed in this paper. A floating vertical plate (FVFP) is introduced into the filled oxide trench of a conventional trench SOI LDMOS (CT SOI) to improve its electrical performance. We conduct related performance analysis to this device by simulation and investigate the effects of different parameters on its performance. The FVFP causes an assisted depletion effect especially for the trench surface regions. An ultra-low \(R_\mathrm{{on,sp}}\) is therefore obtained in the FVFP device due to higher drift region doping concentration \((N_\mathrm{{d}})\). A breakdown voltage (BV) of 188V and a \(R_\mathrm{{on,sp}}\) of \(0.9 \hbox { m}\Omega \, \hbox { cm}^{2}\) are realized on a 4.8-\({\upmu }\hbox {m}\)-long drift region, a 7.5-\({\upmu }\hbox {m}\)-thick top-silicon layer and a 0.5-\({\upmu }\hbox {m}\)-thick buried oxide (BOX) layer by our simulation. Eventually, the \(R_\mathrm{{on,sp}}\) for the FVFPT SOI can be reduced by more than 60%, while its BV is maintained the same class as the CT SOI, and the figure of merit (FOM) is enhanced by 155%. And a set of optimal parameters, including the structure parameters of plate and the property parameters of device, are obtained.     

Delta-doped tunnel FET (D-TFET) to improve current ratio ($$I_\mathrm{ON}/I_\mathrm{OFF}$$) and ON-current performance

A two dimensional (2D) analytical drain current model has been developed for a delta-doped tunnel field-effect transistor (D-TFET) that can address the ON-current issues of the conventional TFET. Insertion of a highly doped delta layer in the source region paves the way for improved tunneling volume and thus provides high drain current as compared with TFETs. The present model takes into account the effects of the distance between the delta-doping region and the source–channel interface on the subthreshold swing (SS), current ratio, and ON-current performance. The D-TFET is predicted to have a higher current ratio \(\left( {\frac{I_\mathrm{ON} }{I_\mathrm{OFF} }\cong 10^{11}} \right) \) compared with TFETs \(\left( {\frac{I_\mathrm{ON} }{I_\mathrm{OFF} }\cong 10^{10}} \right) \) with a reasonable SS \(\left( {{\sim }52\,\mathrm{mV/dec}} \right) \) and \(V_\mathrm{th}\) performance at an optimal position of 2 nm from the channel. The surface potential, electric field, and minimum tunneling distance have been derived using the solution of the 2D Poisson equation. The accuracy of the D-TFET model is validated using the technology computer aided design (TCAD) device simulator from Synopsys.     

Series and parallel resistance effects on the C–V and G–V characteristics of $$\mathrm{Al}/\mathrm{SiO}_{2}$$/Si structure

This paper investigates the electrical behavior of the C–V and G–V characteristics of \(\mathrm{Al}/\mathrm{SiO}_{2}/\mathrm{Si}\) structure. The modeling of capacitance and conductance has been developed from complex admittance treatment applied to the proposed equivalent circuit. Poisson transport equations have been used to determine the charge density, surface potential, total capacitance, and flatband and threshold voltages as a function of the gate voltage, frequency (\(\omega )\), and series \(({R}_{\mathrm{s}})\) and parallel \(({R}_{\mathrm{p}})\) resistances. Results showed a frequency dispersion of C–V and G–V curves in both accumulation and inversion regimes. With increasing frequency, the accumulation capacitance is decreased, whereas the conductance is strongly increased. The shape, dispersion, and degradation of C–V and G–V characteristics are more influenced when parallel and series resistances \((\mathrm{R}_{\mathrm{s}}\), \(\mathrm{R}_{\mathrm{p}})\) are dependent to substrate doping density. The variation of \(\mathrm{R}_{\mathrm{s}}\) and \(\mathrm{R}_{\mathrm{p}}\) values led to a reduction of flatband voltage from ?1.40 to ?1.26 V and increase of the threshold voltage negatively from ?0.28 to ?0.74 V. A good agreement has been observed between simulated and measured C–V and G–V curves obtained at high frequency.     

Dual-material double-gate tunnel FET: gate threshold voltage modeling and extraction

A new analytical model for the gate threshold voltage (\(V_\mathrm{TG}\)) of a dual-material double-gate (DMDG) tunnel field-effect transistor (TFET) is reported. The model is derived by solving the quasi-two-dimensional Poisson’s equation in the lightly doped Si film and employing the physical definition of \(V_\mathrm{TG}\). A numerical simulation study of the transfer characteristics and \(V_\mathrm{TG}\) of a DMDG TFET has been carried out to verify the proposed analytical model. In the numerical calculations, extraction of \(V_\mathrm{TG}\) is performed based on the transconductance change method as already used for conventional metal–oxide–semiconductor FETs (MOSFETs). The effects of gate length scaling, Si film thickness scaling, and modification of the gate dielectric on \(V_\mathrm{TG}\) are reported. The dependence of \(V_\mathrm{TG}\) on the applied drain bias is investigated using the proposed model. The proposed model can predict the effect of variation of all these parameters with reasonable accuracy.     

Analog performance investigation of dual electrode based doping-less tunnel FET

In this paper, we have proposed a device and named it dual electrode doping-less TFET (DEDLTFET), in which electrodes on top and bottom of source and drain are considered to enhance the ON state current and Analog performances. The charge plasma technique is used to generate electron’s and hole’s clouding depending upon their respective work functions at top and bottom of source/drain electrode. Band-to-band-tunneling rate is similar on both sides of source-channel junctions, which increases ON state current. The analog performance parameters of DEDLTFET are investigated and using device simulation the demonstrated characteristics are compared with doping-less (DLTFET) and the conventional doped double gate TFET (DGTFET), such as transconductance \((\hbox {g}_\mathrm{m})\), transconductance to drain current ratio \((\hbox {g}_\mathrm{m}/\hbox {I}_\mathrm{D})\), output-conductance (g\(_{d})\), output resistance \((\hbox {r}_\mathrm{d})\), early voltage \((\hbox {V}_\mathrm{EA})\), intrinsic gain \((\hbox {A}_\mathrm{V})\), total gate capacitance \((\hbox {C}_\mathrm{gg})\) and unity gain frequency \((\hbox {f}_\mathrm{T})\). From the simulation results, it is observed that DEDLTFET has significantly improved analog performance as compared to DGTFET and DLTFET.     

Computational study of a new resonant tunneling diode based on an $$\hbox {MoS}_{2}$$ nanoribbon with sulfur line vacancies

Recent experimental studies have shown that sulfur vacancies in monolayer \(\hbox {MoS}_{2}\) are mobile under exposure to an electron beam and tend to accumulate as sulfur line vacancies (Komsa in Phys Rev B 88: 035301, 2013). In this work, we designed a new resonant tunneling diode (RTD) based on this natural property. Two rows of sulfur vacancies are introduced into armchair \(\hbox {MoS}_{2}\) nanoribbons (\(\hbox {A-MoS}_{2}\) NRs) to tune the nanoribbons’ bandgap to obtain the double-barrier quantum well structure of the resonant tunneling diode. This arrangement has a unique benefit that will result in very little physical distortion. A tight-binding (TB) model, with five 4d-orbitals of the Mo atom and three 3p-orbitals of the S atom, is employed for calculations. In the TB model, which is described in terms of Slater–Koster parameters, we also incorporate the changes of edge bonds. Density functional theory is used to determine all the necessary parameters of the TB model. They are obtained by an optimization procedure which achieves very fine parameter values, which can regenerate the most important energy bands of \(\hbox {A-MoS}_{2}\) NRs of different widths, with highly satisfactory precision. The introduction of these new parameters is another contribution of this work. Lastly, the nonequilibrium Green’s function formalism based on the TB approximation is used to explore the properties of the new RTD structures based on \(\hbox {A-MoS}_{2}\) NRs. Negative differential resistance with peak to valley ratio (PVR) of about 78 at room temperature is achieved for one RTD, having peak current \(I_\mathrm{p}=90\) nA. We show that the PVR can exceed 120 when increasing the barrier length of the RTD at the expense of lower \(I_\mathrm{p}\).     

Double aperture double-gate vertical high-electron-mobility transistor

In this paper, we propose a double aperture double-gate AlGaN/GaN vertical high-electron-mobility transistor (HEMT) to improve the device characteristics, such as the current and the ON resistance (\(\hbox {\textit{R}}_{\mathrm{ON}}\)). The proposed vertical HEMT results are compared to the conventional single aperture single-gate vertical HEMT of equal dimensions, and increased drain current and lower \(\hbox {\textit{R}}_{\mathrm{ON}}\) are shown. A comprehensive simulation study has also been carried out for the proposed device, to analyse the impact of thickness and doping concentration of aperture, drift region, and current blocking layer. In addition, the effect of different materials in current blocking layer on device characteristics is also studied. The obtained results and their effect on device characteristics have been thoroughly analysed and explained accordingly.     

Analysis of independent gate operation in Si nano tube FET and threshold prediction model using 3D numerical simulation

In this paper, silicon nanotube field effect transistors (SiNT-FETs) are investigated for independent gate operation using 3D numerical simulation. The parameters, \(\mathrm{I_{ON} , I_{OFF}, V_{T}}\), and the unity gain cut-off frequency \(\mathrm{(f_{T}}\)) are studied in the independent-gate mode. The SiNT-FET we have considered has two gates, namely outer and inner gates, and can be simultaneously driven or independently driven. The physical gate oxide thicknesses of the outer and inner gates of the device are to be converted into effective gate oxide thicknesses due to the non-Euclidean geometry associated with the tube structure. The effective gate oxide thicknesses are different for the same outer and inner physical gate oxide thickness. Since the inner and outer gates are asymmetric, the device parameters extracted at the outer and inner gates are different. Since the independent gate operation allows dynamic threshold voltage adjustment, a model to predict the threshold voltage also known as the threshold voltage sensitivity model is developed for the SiNT device by modifying the double gate FinFET model. These models are verified by TCAD simulation results to validate their accuracy.     

Analysis of tunneling currents in multilayer black phosphorous and $$\hbox {MoS}_{2}$$ non-volatile flash memory cells

This paper presents a theoretical study of tunneling current density and the leakage current through multi-layer (stacked) trapping layer in the gate dielectric in MOS non-volatile memory devices. Two different 2D materials (\(\hbox {MoS}_{2}\) and black phosphorous) with a combination of high-k dielectric (\(\hbox {HfO}_{2}\)) have been used for the study with differently ordered stacks i.e., as trapping layer and substrate. The material properties of 2D materials like density of states, effective mass and band structure has been evaluated using density functional theory simulations. Using the Maxwell–Garnett effective medium theory we have calculated the effective barrier height, effective bandgap, effective dielectric constant and effective mass of the gate dielectric stacks. By applying WKB approximation in the multi-layer trapping layer we have studied the effect of the direct and Fowler–Nordheim tunneling currents. The leakage current in all the different stack combinations used has also been evaluated. The results obtained have shown to match the required dynamics of a memory device.     

Intravoxel incoherent motion analysis of abdominal organs: computation of reference parameters in a large cohort of C57Bl/6 mice and correlation to microvessel density

Objective

Diffusion-weighted magnetic resonance imaging (DW-MRI) combined with intravoxel incoherent motion (IVIM) analysis may be applied for assessment of organ lesions, diffuse parenchymal pathologies, and therapy monitoring. The aim of this study was to determine IVIM reference parameters of abdominal organs for translational research in a large cohort of C57Bl/6 laboratory mice.

Materials and methods

Anesthetized mice (n = 29) were measured in a 4.7 T small-animal MR scanner with a diffusion-weighted echo-planar imaging sequence at the \(b\)-values 0, 13, 24, 55, 107, 260, 514, 767, 1020 s/mm². IVIM analysis was conducted on the liver, spleen, renal medulla and cortex, pancreas, and small bowel with computation of the true tissue diffusion coefficient \(D_{\text{t}}\), the perfusion fraction \(f_{\text{p}}\), and the pseudodiffusion coefficient \(D_{\text{p}}\). Microvessel density (MVD) was assessed by immunohistochemistry (IHC) against panendothelial cell antigen CD31.

Results

Mean values of the different organs [\(D_{\text{t}}\) (10^?3 mm²/s); \(f_{\text{p}}\) (%); \(D_{\text{p}}\) (10^?3 mm²/s); MVD (MV/mm²)]: liver 1.15 ± 0.14; 14.77 ± 6.15; 50.28 ± 33.21, 2008.48 ± 419.43, spleen 0.55 ± 0.12; 9.89 ± 5.69; 24.46 ± 17.31; n.d., renal medulla 1.50 ± 0.20; 14.63 ± 4.07; 35.50 ± 18.01; 1231.88 ± 290.61, renal cortex 1.34 ± 0.18; 10.83 ± 3.70; 16.74 ± 6.74; 810.09 ± 193.50, pancreas 1.23 ± 0.22; 20.12 ± 7.46; 29.35 ± 17.82, 591.15 ± 86.25 and small bowel 1.06 ± 0.13; 16.48 ± 3.63; 15.31 ± 7.00; 420.50 ± 168.42. Unlike \(D_{\text{t}}\) and \(f_{\text{p}}\), \(D_{\text{p}}\) correlates significantly with MVD (r = 0.90, p = 0.037).

Conclusion

This systematic evaluation of murine abdominal organs with IVIM and MVD analysis allowed to establish reference parameters for future DW-MRI translational research studies on small-animal disease models.

     

Analysis and modeling of unipolar junction transistor with excellent performance: a novel DG MOSFET with $${N}^{+}{-}{P}^{-}$$ junction

We propose herein a new dual-gate metal–oxide–semiconductor field-effect transistor (MOSFET) with just a unipolar junction (UJ-DG MOSFET) on the source side. The UJ-DG MOSFET structure is constructed from an \({N}^{+}\) region on the source side with the rest consisting of a \({P}^{-}\) region over the gate and drain, forming an auxiliary gate over the drain region with appropriate length and work function (named A-gate), converting the drain to an \({N}^{+}\) region. The new structure behaves as a MOSFET, exhibiting better efficiency than the conventional double-gate MOSFET (C-DG MOSFET) thanks to the modified electric field. The amended electric field offers advantages including improved electrical characteristics, reliability, leakage current, \({I}_{\mathrm{ON}}/I_{\mathrm{OFF}}\) ratio, gate-induced drain leakage, and electron temperature. Two-dimensional analytical models of the surface potential and electric field over the channel and drain are applied to investigate the drain current in the UJ-DG MOSFET. To confirm their accuracy, the MOSFET characteristics obtained using the 2D Atlas simulator for the UJ-DG and C-DG are analyzed and compared.     

3D analytical modeling of surface potential,threshold voltage,and subthreshold swing in dual-material-gate (DMG) SOI FinFETs

Here, we develop a 3D analytical model for potential in a lightly doped dual-material-gate FinFET in the subthreshold region. The model is based on the perimeter-weighted sum of a dual-material double-gate (DMDG) asymmetric MOSFET and a DMDG symmetric MOSFET. The potential model is used to determine the minimum surface potential needed to obtain the threshold voltage \((V_{\mathrm{T}})\) and subthreshold swing (SS) by considering the source barrier changes in the leakiest channel path. The proposed model is capable of reducing the drain-induced barrier lowering (DIBL) as well as the hot carrier effects offered by this device. The impact of control gate ratio and work function difference between the two metal gates on \(V_{\mathrm{T}}\) and SS are also correctly established by the model. All model derivations are validated by comparing the results with technology computer-aided design (TCAD) simulation data.     

Theoretical study of structural,electronic and optical properties of novel ternary alloys $$\hbox {MgO}_{1-{x}}{\hbox {Se}}_{{x}}$$ ($$x =$$x= 0.25, 0.50 and 0.75)

We report on the investigation of the structural, electronic, and optical properties of binary compounds (MgO and MgSe) and their ternary \(\hbox {MgO}_{1-{x}}\hbox {Se}_{{x}}\) (\(x=0.25, 0.5, 0.75\)) alloys within the density functional theory based on the full-potential linearized augmented plane wave method as implemented in the WIEN2k code. We have used the revised Perdew–Burke–Ernzerhof generalized gradient approximation (GGA-PBEsol) to calculate the structural properties and analyze the effect of the Se composition on the lattice constant and the bulk modulus of \(\hbox {MgO}_{1-{x}}\hbox {Se}_{{x}}\). The calculated electronic properties by employing the GGA-PBEsol and TB-mBJ approaches show that \(\hbox {MgO}_{1-{x}}\hbox {Se}_{{x}}\) alloys have a direct band gap \(\Gamma \)–\(\Gamma \) for \(x = 0, 0.25, 0.5\) and 0.75, suggesting the possibility of their use in the long wavelength optoelectronic applications. The optical properties such as the real and imaginary parts of the dielectric function, the refractive index, and the reflectivity of \(\hbox {MgO}_{1-{x}}\hbox {Se}_{{x}}\) are computed by using the accurate TB-mBJ potential. The wide band gaps larger than 3.1 eV mean that \(\hbox {MgO}_{1-{x}}\hbox {Se}_{{x}}\) alloys can be used in the applications of the ultraviolet region of the spectrum. Our data for all studied bowing parameters of \(\hbox {MgO}_{1-{x}}\hbox {Se}_{x}\) may serve as references for future experimental studies.