Dual material gate junctionless tunnel field effect transistor

This paper proposes a junctionless tunnel field effect transistor (JLTFET) with dual material gate (DMG) structure and the performance was studied on the basis of energy band profile modulation. The two-dimensional simulation was carried out to show the effect of conduction band minima on the abruptness of transition between the ON and OFF states, which results in low subthreshold slope (SS). Appropriate selection of work function for source and drain side gate metal of a double metal gate JLTFET can also significantly reduce the subthreshold slope (SS), OFF state leakage and hence gives improved I _ON/I _OFF.     

A junctionless tunnel field effect transistor with low subthreshold slope

we demonstrate the design of a triple gate n-channel junctionless transistor that we call a junctionless tunnel field effect transistor (JLTFET). The JLTFET is a heavily doped junctionless transistor which uses the concept of tunneling, by narrowing the barrier between source and channel of the device, to turn the device ON and OFF. Simulation shows significant improvement compared to simple junctionless field effect transistor both in I _ON/I _OFF ratio and subthreshold slope. Here, junctionless tunnel field effect transistors with high-k dielectric and low-k spacers are demonstrated through simulation and shows an ON-current of 0.25 mA/μm for the gate voltage of 2 V and an OFF current of 3 pA/μm (neglecting gate leakage). In addition, our device shows optimized performance with high I _ON/I _OFF (～10⁹). Moreover, a subthreshold slope of 47 mV/decade is obtained for a 50 nm gate length of simulated JLTFET at room temperature which indicates that JLTFET is a promising candidate for switching performance.     

Radiation performance of planar junctionless devices and junctionless SRAMs

The objective of this work is to analyze the radiation performance of the planar junctionless devices and junctionless device-based SRAMs. Bulk planar junctionless transistor (BPJLT) and silicon-on-insulator planar junctionless transistors (SOIPJLT) under heavy ions irradiation have been studied using TCAD simulations. 6T-SRAM cells built up of BPJLTs and SOIPJLTs have been investigated for their soft error performance. Even though the bipolar amplification of the SOIPJLT is more compared to BPJLT, the soft error performance of the SOIPJLT SRAM is better compared to BPJLT SRAM.     

Electrostatic characteristics of a high-k stacked gate-all-around heterojunction tunnel field-effect transistor using the superposition principle

Journal of Computational Electronics - We use the superposition method to model the electrostatic characteristics of a high-k stacked gate-all-around heterojunction tunneling field-effect...     

Impact of high-k spacer on device performance of a junctionless transistor

The impact of spacer dielectric on both sides of gate oxide on the device performance of a symmetric double-gate junctionless transistor (DGJLT) is reported for the first time. The digital and analog performance parameters of the device considered in this study are drain current (I _D ), ON-state to OFF-state current ratio (I _ON /I _OFF ), subthreshold slope (SS), drain induced barrier lowering (DIBL), intrinsic gain (G _m R _O ), output conductance (G _D ), transconductance/drain current ratio (G _m /I _D ) and unity gain cut-off frequency (f _T ). The effects of varying the spacer dielectric constant (k _sp ) on the electrical characteristics of the device are studied. It is observed that the use of a high-k dielectric as a spacer brings an improvement in the OFF-state current by more than one order of magnitude thereby making the device more scalable. However, the ON-state current is only marginally affected by increasing dielectric constant of spacer. The effects of spacer width (W _sp ) on device performance are also studied. ON-state current marginally decreases with spacer width.     

Immunity to random fluctuations induced by interface trap variability in Si gate-all-around n-nanowire field-effect transistor devices

Journal of Computational Electronics - The impact of variations in the donor and acceptor interface trap distributions on the fluctuation characteristics of 7-nm-node Si gate-all around n-nanowire...     

Quantum ballistic transport in the junctionless nanowire pinch-off field effect transistor

In this work we investigate quantum ballistic transport in ultrasmall junctionless and inversion mode semiconducting nanowire transistors within the framework of the self-consistent Schrödinger-Poisson problem. The quantum transmitting boundary method is used to generate open boundary conditions between the active region and the electron reservoirs. We adopt a subband decomposition approach to make the problem numerically tractable and make a comparison of four different numerical approaches to solve the self-consistent Schrödinger-Poisson problem. Finally we discuss the IV-characteristics for small (r≤5 nm) GaAs nanowire transistors. The novel junctionless pinch-off FET or junctionless nanowire transistor is extensively compared with the gate-all-around (GAA) nanowire MOSFET.     

A surface-potential based drain current model for short-channel symmetric double-gate junctionless transistor

Junctionless transistors, which do not have any pn junction in the source-channel-drain path have become an attractive candidate in sub-20 nm regime. They have homogeneous and uniform doping in source-channel-drain region. Despite some similarities with conventional MOSFETs, the charge-potential relationship is quite different in a junctionless transistor, due to its different operational principle. In this report, models for potential and drain current are formulated for shorter channel symmetric double-gate junctionless transistor (DGJLT). The potential model is derived from two dimensional Poisson’s equation using “variable separation technique”. The developed model captures the physics in all regions of device operation i.e., depletion to accumulation region without any fitting parameter. The model is valid for a range of channel doping concentrations, channel thickness and channel length. Threshold voltage and drain-induced barrier lowering values are extracted from the potential model. The model is in good agreement with professional TCAD simulation results.     

Performance estimation of sub-30 nm junctionless tunnel FET (JLTFET)

In this paper we examined the short channel behavior of junction less tunnel field effect transistor (JLTFET) and a comparison was made with the conventional MOSFET on the basis of variability of device parameter. The JLTFET is a heavily doped junctionless transistor which uses the concept of tunneling, by narrowing the barrier between source and channel of the device, to turn the device ON and OFF. The JLTFET exhibits an improved subthreshold slope (SS) of 24 mV/decade and drain-induced barrier lowering (DIBL) of 38 mV/V as compared to SS of 73 mV/decade and DIBL of 98 mV/V for the conventional MOSFET. The simulation result shows that the impact of length scaling on threshold voltage for JLTFET is very less as compared to MOSFET. Even a JLTFET with gate length of 10 nm has better SS than MOSFET with gate length of 25 nm, which enlightens the superior electrostatic integrity and better scalability of JLTFET over MOSFET.     

New nanoscale band-to-band tunneling junctionless GNRFETs: potential high-performance devices for the ultrascaled regime

High-performance sub-10-nm field-effect transistors (FETs) are considered to be a prerequisite for the development of nanoelectronics and modern integrated circuits. Herein, new band-to-band tunneling (BTBT) junctionless (JL) graphene nanoribbon field-effect transistors (GNRFETs) endowed with sub-10-nm gate length are proposed using a quantum transport simulation. The nonequilibrium Green’s function (NEGF) formalism is used in quantum simulations considering the self-consistent electrostatics and the ballistic transport limit. The computational assessment includes the I_DS–V_GS transfer characteristics, the potential and electron density distributions, the current spectrum, the ambipolar behavior, the leakage current, the subthreshold swing, the current ratio, and the scaling capability. It is found that BTBT JL-GNRFETs can provide subthermionic subthreshold swings and moderate current ratios for sub-10-nm gate lengths. Moreover, a new doping profile, based on the use of lateral lightly n-type-doped pockets, is adopted to boost their performance. The numerical results reveal that BTBT JL-GNRFETs with the proposed doping profile can exhibit improved performance in comparison with uniformly doped BTBT JL-GNRFETs. In addition, the role of the length and n-type doping concentration of the pockets in boosting the device performance is also studied and analyzed while considering the scaling capability of such devices, revealing that low doping concentrations and long pocket lengths are useful for performance improvement. The merits of the BTBT JL-GNRFETs based on the proposed nonuniform doping profile, namely sub-10-nm scale, steep subthermionic subthreshold swing, low leakage current, and improved current ratio and ambipolar behavior, make them promising nanodevices for use in modern nanoelectronics and high-performance integrated circuits.

     

Physics-based drain current modeling of gate-all-around junctionless nanowire twin-gate transistor (JN-TGT) for digital applications

Vertically stacked dielectric separated independently controlled gates can be used to realize dual-threshold voltage on a single silicon channel MOS device. This approach significantly reduces the effective layout area and is similar to merging two transistors in series. This multiple independent gate device enables the design of new class of compact logic gates with low power and reduced area. In this paper, we present the junctionless concept based twin gate transistor for digital applications. To analyse the appropriate behaviour of device, this paper presents the modeling, simulation and digital overview of novel gate-all-around junctionless nanowire twin-gate transistor for advanced ultra large scale integration technology. This low power single MOS device gives the full functionality of “AND” gate and can be extended to full functionality of 2-input digital “NAND” gate. To predict accurate behaviour, a physics based analytical drain current model has been developed which also includes the impact of gate depleted source/drain regions. The developed model is verified using ATLAS 3D device simulator. This single channel device can function as “NAND” gate even at low operating voltage.     

Development of combined low-emissions burner devices for low-power boilers

Low-power water boilers are widely used for autonomous heat supply in various industries. Firetube and water-tube boilers of domestic and foreign manufacturers are widely represented on the Russian market. However, even Russian boilers are supplied with licensed foreign burner devices, which reduce their competitiveness and complicate operating conditions. A task of developing efficient domestic low-emissions burner devices for low-power boilers is quite acute. A characteristic property of ignition and fuel combustion in such boilers is their flowing in constrained conditions due to small dimensions of combustion chambers and flame tubes. These processes differ significantly from those in open combustion chambers of high-duty power boilers, and they have not been sufficiently studied yet. The goals of this paper are studying the processes of ignition and combustion of gaseous and liquid fuels, heat and mass transfer and NO _x emissions in constrained conditions, and the development of a modern combined low-emissions 2.2 MW burner device that provides efficient fuel combustion. A burner device computer model is developed and numerical studies of its operation on different types of fuel in a working load range from 40 to 100% of the nominal are carried out. The main features of ignition and combustion of gaseous and liquid fuels in constrained conditions of the flame tube at nominal and decreased loads are determined, which differ fundamentally from the similar processes in steam boiler furnaces. The influence of the burner devices design and operating conditions on the fuel underburning and NO _x formation is determined. Based on the results of the design studies, a design of the new combined low-emissions burner device is proposed, which has several advantages over the prototype.     

遥控器等低功耗设备上的定时校准方法

遥控器等低功耗设备上采用内部低速振荡器作为副时钟,芯片休眠时只有内部低速振荡器可以运行,而芯片内部振荡器精度很低,如果遥控器上设定定时功能,则定时精度也会变低,影响用户使用,故探讨一种采用芯片内部高速振荡器来对芯片内部低速振荡器进行定时校准的方法,以提高定时精度.     

Hydrogen sensitive field-effect transistor based on germanene nanoribbon and optical properties of hydrogenated germanene

Physisorption of hydrogen molecules on armchair germanene nanoribbon (GeNR) is studied with density functional methods. The adsorption geometries, adsorption energies and transferred charge are obtained. To take the Van der Waals forces into account, the Grimme correction is added to the calculation method. The physisorption effect on the electrical properties of the ribbon is explored as a function of \(\hbox {H}_{2}\) concentration through the Green’s function techniques. Sensing features of the GeNR are investigated as a channel of a back gated field effect transistor. The optical properties of the nanoribbon are obtained for parallel and perpendicular polarizations. The results point out that, the germanene is a suitable substrate for \(\hbox {H}_{2}\) encapsulation. Moreover, \(\hbox {H}_{2}\) physisorption can improve the I–V characteristics and suppress the optical spectrum of the GeNR. The current through the nanoribbon increases by increasing \(\hbox {H}_{2}\) concentration at the same bias voltage. Also, the germanene back gated FET improve the sensing properties. The results show that the GeNR dielectric function is anisotropic and the GeNR becomes more transparent by increasing \(\hbox {H}_{2}\) density. Finally, by applying the spin-orbit coupling (SOC) effect, the obtained results are re-calculated and the changes in the results are studied. The SOC opens up the electronic band gap of the GeNR about 20 meV and increases the current slightly through the GeNR.     

Modeling the threshold voltage of PNIN SSOI tunnel field‐effect transistor

In this paper, a physically based analytical threshold voltage model for PNIN strained‐silicon‐on‐insulator tunnel field‐effect transistor (PNIN SSOI TFET) is proposed by solving the two‐dimensional (2D) Poisson equation in narrow N⁺ layer and intrinsic region. In the proposed model, the effect of strain (in terms of equivalent Ge mole fraction), narrow N⁺ layer and gate dielectric, and so on, is being considered. The validity of the proposed model is verified by comparing the model results with 2D device simulation results. It is demonstrated that the proposed model can correctly predicts the trends in threshold voltage with varying the device parameters. This proposed model can be effectively used to design, simulate, and fabricate the PNIN SSOI TFETs with the desired performance. Copyright © 2015 John Wiley & Sons, Ltd.