First-principles investigation on transport properties of $$\hbox {Zn}_{2}\hbox {SnO}_{4}$$ molecular device and response toward $$\hbox {NO}_{2}$$NO2 gas molecules

The transport properties of a \(\hbox {Zn}_{2}\hbox {SnO}_{4}\) device along with adsorption properties of \(\hbox {NO}_{2}\) gas molecules on \(\hbox {Zn}_{2}\hbox {SnO}_{4}\) (ZTO) molecular devices are investigated with density functional theory using the non-equilibrium Green’s function technique. The transmission spectrum and device density of states spectrum confirm the changes in HOMO–LUMO energy level due to transfer of electrons between the ZTO-based material and the \(\hbox {NO}_{2}\) molecules. I–V characteristics demonstrate the variation in the current upon adsorption of \(\hbox {NO}_{2}\) gas molecules on the ZTO device. The findings of the present study clearly suggest that ZTO molecular devices can be used to detect \(\hbox {NO}_{2}\) gas molecules in the trace level.     

Optimal design of the multiple-apertures-GaN-based vertical HEMTs with $$\hbox {SiO}_{2}$$ current blocking layer

Gallium nitride (GaN) based vertical high electron mobility transistor (HEMT) is very crucial for high power applications. Combination of advantageous material properties of GaN for high speed applications and novel vertical structure makes this device very beneficial for high power application. To improve the device performance especially in high drain bias condition, a novel GaN based vertical HEMT with silicon dioxide \((\hbox {SiO}_{2})\) current blocking layer (CBL) was reported recently. In this paper, effects of the thickness of CBL layer and the aperture length on the electrical and breakdown characteristics of GaN vertical HEMTs with \(\hbox {SiO}_{2}\) CBL are simulated by using two-dimensional quantum-mechanically corrected device simulation. Intensive numerical study on the device enables us to optimize and conclude that devices with \(0.5\hbox {-}\upmu \hbox {m}\)-thick \(\hbox {SiO}_{2}\) layer and \(1\hbox {-}\upmu \hbox {m}\)-long aperture will be beneficial considerations to improve the device performance. Notably, using the multiple apertures can effectively reduce the on-state conducting resistance of the device. On increasing the number of apertures, the drain current is increased but the breakdown voltage is decreased. Therefore, device with four apertures is taken as an optimized result. The maximum drain current of 84 mA at \(\hbox {V}_\mathrm{G}= 1\,\hbox {V}\) and \(\hbox {V}_\mathrm{D}= 30\,\hbox {V}\), and the breakdown voltage of 480 V have been achieved for the optimized device.     

Analog performance investigation of dual electrode based doping-less tunnel FET

In this paper, we have proposed a device and named it dual electrode doping-less TFET (DEDLTFET), in which electrodes on top and bottom of source and drain are considered to enhance the ON state current and Analog performances. The charge plasma technique is used to generate electron’s and hole’s clouding depending upon their respective work functions at top and bottom of source/drain electrode. Band-to-band-tunneling rate is similar on both sides of source-channel junctions, which increases ON state current. The analog performance parameters of DEDLTFET are investigated and using device simulation the demonstrated characteristics are compared with doping-less (DLTFET) and the conventional doped double gate TFET (DGTFET), such as transconductance \((\hbox {g}_\mathrm{m})\), transconductance to drain current ratio \((\hbox {g}_\mathrm{m}/\hbox {I}_\mathrm{D})\), output-conductance (g\(_{d})\), output resistance \((\hbox {r}_\mathrm{d})\), early voltage \((\hbox {V}_\mathrm{EA})\), intrinsic gain \((\hbox {A}_\mathrm{V})\), total gate capacitance \((\hbox {C}_\mathrm{gg})\) and unity gain frequency \((\hbox {f}_\mathrm{T})\). From the simulation results, it is observed that DEDLTFET has significantly improved analog performance as compared to DGTFET and DLTFET.     

Numerical analysis of transmission coefficient,LDOS, and DOS in superlattice nanostructures of cubic $$\hbox {Al}_{x}\hbox {Ga}_{1-x}\hbox {N/GaN}$$ resonant tunneling MODFETs

Numerical analysis of the transmission coefficient, local density of states, and density of states in superlattice nanostructures of cubic \(\hbox {Al}_{x}\hbox {Ga}_{1-x}\hbox {N/GaN}\) resonant tunneling modulation-doped field-effect transistors (MODFETs) using \(\hbox {next}{} \mathbf{nano}^{3}\) software and the contact block reduction method is presented. This method is a variant of non-equilibrium Green’s function formalism, which has been integrated into the \(\hbox {next}\mathbf{nano}^{3}\) software package. Using this formalism in order to model any quantum devices and estimate their charge profiles by computing transmission coefficient, local density of states (LDOS) and density of states (DOS). This formalism can also be used to describe the quantum transport limit in ballistic devices very efficiently. In particular, we investigated the influences of the aluminum mole fraction and the thickness and width of the cubic \(\hbox {Al}_{x}\hbox {Ga}_{1-x}\hbox {N}\) on the transmission coefficient. The results of this work show that, for narrow width of 5 nm and low Al mole fraction of \(x = 20\,\%\) of barrier layers, cubic \(\hbox {Al}_{x}\hbox {Ga}_{1-x}\hbox {N/GaN}\) superlattice nanostructures with very high density of states of 407 \(\hbox {eV}^{-1}\) at the resonance energy are preferred to achieve the maximum transmission coefficient. We also calculated the local density of states of superlattice nanostructures of cubic \(\hbox {Al}_{x}\hbox {Ga}_{1-x}\hbox {N/GaN}\) to resolve the apparent contradiction between the structure and manufacturability of new-generation resonant tunneling MODFET devices for terahertz and high-power applications.     

Memristive computing devices and applications

Advances in electronics have revolutionized the way people work, play and communicate with each other. Historically, these advances were mainly driven by CMOS transistor scaling following Moore’s law, where new generations of devices are smaller, faster, and cheaper, leading to more powerful circuits and systems. However, conventional scaling is now facing major technical challenges and fundamental limits. New materials, devices, and architectures are being aggressively pursued to meet present and future computing needs, where tight integration of memory and logic, and parallel processing are highly desired. To this end, one class of emerging devices, termed memristors or memristive devices, have attracted broad interest as a promising candidate for future memory and computing applications. Besides tremendous appeal in data storage applications, memristors offer the potential to enable efficient hardware realization of neuromorphic and analog computing architectures that differ radically from conventional von Neumann computing architectures. In this review, we analyze representative memristor devices and their applications including mixed signal analog-digital neuromorphic computing architectures, and highlight the potential and challenges of applying such devices and architectures in different computing applications.     

Assessing the Reliability of Elastomer Sockets in Temperature Environments

This paper presents a study on the contact resistance behavior of elastomer sockets used to interconnect microprocessors and printed circuit boards in enterprise servers. The integrated circuit sockets, installed in production representative assemblies, were evaluated at 25 $^{circ}hbox{C}$ , 55 $^{circ}hbox{C}$, and 75 $^{circ}hbox{C}$ for 2000 h. A sample subset was evaluated up to 16 500 h at 25 $^{circ}hbox{C}$ and up to 4500 h at 55 $^{circ}hbox{C}$. The test results show that contact resistance decreases over time for all test conditions, as much as 50% from their initial values. Elastomer contact behavior is strongly dependent on temperature and time. The resistance behavior over temperature is modeled with multiple statistical distributions. The mean contact resistance is represented with a physics-of-failure model, and the elastomer contact reliability is estimated using a log-normal distribution.      

Physics-based modeling approaches of resistive switching devices for memory and in-memory computing applications

The semiconductor industry is currently challenged by the emergence of Internet of Things, Big data, and deep-learning techniques to enable object recognition and inference in portable computers. These revolutions demand new technologies for memory and computation going beyond the standard CMOS-based platform. In this scenario, resistive switching memory (RRAM) is extremely promising in the frame of storage technology, memory devices, and in-memory computing circuits, such as memristive logic or neuromorphic machines. To serve as enabling technology for these new fields, however, there is still a lack of industrial tools to predict the device behavior under certain operation schemes and to allow for optimization of the device properties based on materials and stack engineering. This work provides an overview of modeling approaches for RRAM simulation, at the level of technology computer aided design and high-level compact models for circuit simulations. Finite element method modeling, kinetic Monte Carlo models, and physics-based analytical models will be reviewed. The adaptation of modeling schemes to various RRAM concepts, such as filamentary switching and interface switching, will be discussed. Finally, application cases of compact modeling to simulate simple RRAM circuits for computing will be shown.     

Temperature Stability Analysis of CMOS-SAW Devices by Embedded Heater Design

The design, finite element (FE) modeling, and electrical characterization of an embedded heater in complementary metal–oxide–semiconductor (CMOS) are presented. The heater is used to analyze the temperature stability behavior of CMOS-surface acoustic wave (SAW) devices. The heater employs n-well layer of standard CMOS technology to provide high efficiency resistive heating without physically perturbing the SAW architectures and performances. A detailed 3-D model and FE investigation is laid out to characterize the heat, current, temperature, and thermal energy distributions within the substrate and the piezoelectric material of interest ZnO. Electrical characterization based on Wheatstone configuration is presented to analyze the temperature stability of the sputtered ZnO and the CMOS-SAW delay lines. A temperature coefficient of frequency of $-hbox{48.815} hbox{ppm}/^{circ}hbox{C}$ for the fabricated SAW devices with operating frequency of 322.5 MHz is obtained. The experimental results show close agreement with the FE simulations. The results demonstrate that the embedded heater design can be used as a robust analytical tool to investigate temperature stability of CMOS-SAW devices and potentially be utilized as an on-chip element for chemical, biological, and temperature sensor applications.      

A GMR device based on a magnetic nanostructure with a $$\updelta $$-doping

We study how to manipulate by the \(\updelta \)-doping a giant magnetoresistance (GMR) device, which can be realized experimentally by depositing two parallel ferromagnetic stripes on top and bottom of the semiconductor \(\hbox {GaAs/Al}_{x}\hbox {Ga}_{1-x}\mathrm{As}\) heterostructure. We demonstrate an obvious GMR effect in the device with a \(\updelta \)-doping. We also reveal that the magnetoresistance ratio depends not only on the weight but also on the position of the \(\updelta \)-doping. These interesting results will be helpful for designing controllable GMR devices.     

Theoretical insights and experimental characterization of $$\hbox {HfO}_2$$-based OxRRAMs operation

The intensive research in resistive random access memories (RRAM) field has brought in significant improvements in the performance, optimization and reliability of the devices as well as more understanding on their operation. This was made possible through the combination of different tools starting from material engineering to device characterization, modeling and simulations. In this review, we bring an overview of our recent work on RRAM through experimental characterization and first-principles calculations. We explore the effects of metal electrodes on the switching performance and conductive filament (CF) stability of \(\hbox {HfO}_2\) oxide-based RRAM (OxRRAM). With the insight gained from the experimental data, we employ first-principles calculations to have a better microscopic understanding on OxRRAM operation. We show that CF stability and device operating voltages strongly depend on the electrode material. Ti being an electrode material of high interest, we investigate the type of \(\hbox {Ti/HfO}_2\) interface that may be formed and propose a probable composition. We also study the formation and migration of extended Frenkel-pair (EFP) defect in \(\hbox {HfO}_2\) which we consider to be the prototype defect responsible for OxRRAM degradation leading to CF formation. This EFP emission occurs through a cascading migration of O atoms inside \(\hbox {HfO}_2\) lattice. Based on EFP formation and diffusion, we present a simplified CF formation model. Finally, we study low resistance data retention failure in OxRRAM through \(\hbox {HfO}_2\), \(\hbox {Hf}_{1x}\hbox {Al}_{2x}\hbox {O}_{2+x}\) (HfAlO) and \(\hbox {Hf}_{1-x}\hbox {Ti}_{x}\hbox {O}_{2}\) (HfTiO) type of cells. We link its origin to the lateral diffusion of oxygen vacancies at the constriction/tip of the conductive filament in \(\hbox {HfO}_2\)-based RRAM.     

Transport studies of $$\hbox {CeO}_{2}$$ molecular device and adsorption behavior of CO on $$\hbox {CeO}_{2}$$ device: a first-principles investigation

Using density functional theory and the non-equilibrium Green’s function formalism, the transport and CO adsorption properties of \(\hbox {CeO}_{2}\) molecular device are studied. The band structure shows that \(\hbox {CeO}_{2}\) nanostructure exhibits semiconducting nature. The electron density is found to be more in oxygen sites rather than in cerium sites along \(\hbox {CeO}_{2}\) nanostructure. The density of states spectrum shows the variation in density of charge upon adsorption of CO on CeO\(_2\) device. The transmission spectrum provides the insights on the transition of charge in \(\hbox {CeO}_{2}\) molecular device upon adsorption of CO along the scattering region. I–V characteristics confirm the adsorption of CO with the variation of current along \(\hbox {CeO}_{2}\) molecular device. The findings show that \(\hbox {CeO}_{2}\) two probe molecular device can be efficiently used for CO detection in the atmosphere.     

控制与保护开关电器用4~20mA标准电流输出电路

提出了一种用于控制与保护开关电器的4~20 m A标准电流输出电路。阐述了基于脉宽调制技术实现数模转换的原理,在电路仿真的基础上设计了硬件电路,分析了电路的各个部分并详细讨论了实现脉宽调制输出的软件设计方法。对导致输出电流产生误差的因素作了进一步探讨,改进了相关器件选型,试验表明提高了电路精度和线性度。该电路抗干扰能力强、安全性高且比采用数模转换器实现方式的成本低,适合传输远程模拟量信号,可用于工业现场设备及自动化仪表的相关开发。     

$${ SIM}^2{ RRAM}$$: a physical model for RRAM devices simulation

In the last few years, resistive random access memory (RRAM) has been proposed as one of the most promising candidates to overcome the current Flash technology in the market of non-volatile memories. These devices have the ability to change their resistance state in a reversible and controlled way applying an external voltage. In this way, the resulting high- and low-resistance states allow the electrical representation of the binary states “0” and “1” without storing charge. Many physical models have been developed with the aim of understanding the mechanisms that control the resistive switching. In this work, we have compiled the main theories accepted as well as their corresponding models for the conduction characteristics. In addition, simulation tools play a very important role in the task of checking these theories and understanding these mechanisms. For this reason, the simulation tool called \(\hbox {SIM}^{2}\hbox {RRAM}\) has been presented. This simulator is capable of replicating the global behavior of RRAM cell based on \(\hbox {HfO}_{x}\).     

基于现场可编程门阵列Buck变换器的实时仿真技术

利用FPGA的并行计算特性,在电力电子模型的实时仿真中FPGA可以实现纳秒级的仿真步长,能够更加真实的呈现电力电子开关器件的特性.通过分析Buck变换器在电感电流连续导通模式下的数学模型,基于XILINX公司的System Generator搭建了Buck变换器的数学模型,并对其进行了实时仿真,与器件仿真的结果进行了对比,从仿真结果中,可以看出该数学模型的有效性,可以在一定误差范围内取代Buck变换器的器件模型,同时也为实际的电路研制和调试提供了思路.     

Analog and RF performance of doping-less tunnel FETs with $$\hbox {Si}_{0.55} \hbox {Ge}_{0.45}$$ source

This paper reports studies of a doping-less tunnel field-effect transistor (TFET) with a \(\hbox {Si}_{0.55} \hbox {Ge}_{0.45}\) source structure aimed at improving the performance of charge-plasma-based doping-less TFETs. The proposed device achieves an improved ON-state current (\(I_{{\mathrm{ON}}} \sim {4.88} \times {10}^{-5}\,{\mathrm{A}}/\upmu {\mathrm{m}}\)), an \(I_\mathrm{ON}/I_\mathrm{OFF}\) ratio of \({6.91} \times {10}^{12}\), an average subthreshold slope (\(\hbox {AV-SS}\)) of \(\sim \) \({64.79}\,{\mathrm{mV/dec}}\), and a point subthreshold slope (SS) of 14.95 mV/dec. This paper compares the analog and radio of frequency (RF) parameters of this device with those of a conventional doping-less TFET (DLTFET), including the transconductance (\(g_{{\mathrm{m}}}\)), transconductance-to-drain-current ratio \((g_\mathrm{m}/I_\mathrm{D})\), output conductance \((g_\mathrm{d})\), intrinsic gain (\(A_{{\mathrm{V}}}\)), early voltage (\(V_{{\mathrm{EA}}}\)), total gate capacitance (\( C_{{\mathrm{gg}}}\)), and unity-gain frequency (\(f_{{\mathrm{T}}}\)). Based on the simulated results, the \(\hbox {Si}_{0.55}\hbox {Ge}_{0.45}\)-source DLTFET is found to offer superior analog as well as RF performance.     

$hbox{1}/f$ Noise Characterization of n- and p-Type Polycrystalline-Silicon Thin-Film Transistors

This paper presents a study of low-frequency-noise properties of n- and p-type polycrystalline-silicon (poly-Si) thin-film transistors (TFTs). The $hbox{1}/f$ noise behavior of these devices prompted the use of the carrier number with correlated mobility fluctuation model for data analysis. From this model, trap densities in this study were found to range from $hbox{3.5} times hbox{10}^{16}$ to $hbox{4} times hbox{10}^{17} hbox{states/eV} cdot hbox{cm}^{3}$, which is indicative of a good top surface of the channel and interface between the oxide and poly-Si. The normalized current noise of the p-channel TFTs changes with the inverse of current, independent of the width $(W)$ -to-length $(L)$ ratio of the channel; the normalized current noise of the n-channel TFTs also changes with the inverse of current, but not independent of the $W/L$ ratio. For smaller currents, noise is caused by traps at or near the oxide/semiconductor interface, whereas for larger currents, the larger contribution to the noise is believed to originate from the bulk.      

Analysis of the floating‐gate transistor using the charge sheet model

The multiple‐input floating‐gate transistor is a semiconductor device that has found wide application in digital and analog electronic integrated circuits. Simulating an electronic circuit is an essential step in the design flow, prior to manufacturing. Therefore, an advanced model for the multiple‐input floating‐gate transistor is needed for analog design. This paper shows a method for adapting the charge sheet model for advanced models of the device. In addition, the problem of obtaining the drain to source current numerically as a function of external voltages is addressed. Furthermore, important plots are presented in order to clarify the behavior of the concerned device. The small signal analysis of the device is included. This summary may be interesting to those seeking to model the multiple‐input floating‐gate transistor, looking for alternatives to analog electronic design, needing low operating voltage, generating new design strategies, or wishing to understand of the operation of the device or the use of alternatives to implement analog circuits. Copyright © 2015 John Wiley & Sons, Ltd.