Physics-based modeling approaches of resistive switching devices for memory and in-memory computing applications

The semiconductor industry is currently challenged by the emergence of Internet of Things, Big data, and deep-learning techniques to enable object recognition and inference in portable computers. These revolutions demand new technologies for memory and computation going beyond the standard CMOS-based platform. In this scenario, resistive switching memory (RRAM) is extremely promising in the frame of storage technology, memory devices, and in-memory computing circuits, such as memristive logic or neuromorphic machines. To serve as enabling technology for these new fields, however, there is still a lack of industrial tools to predict the device behavior under certain operation schemes and to allow for optimization of the device properties based on materials and stack engineering. This work provides an overview of modeling approaches for RRAM simulation, at the level of technology computer aided design and high-level compact models for circuit simulations. Finite element method modeling, kinetic Monte Carlo models, and physics-based analytical models will be reviewed. The adaptation of modeling schemes to various RRAM concepts, such as filamentary switching and interface switching, will be discussed. Finally, application cases of compact modeling to simulate simple RRAM circuits for computing will be shown.     

Resistive random access memory (RRAM) technology: From material,device, selector, 3D integration to bottom-up fabrication

Emerging non-volatile memory technologies are promising due to their anticipated capacity benefits, non-volatility, and zero idle energy. One of the most promising candidates is resistive random access memory (RRAM) based on resistive switching (RS). This paper reviews the development of RS device technology including the fundamental physics, material engineering, three-dimension (3D) integration, and bottom-up fabrication. The device operation, physical mechanisms for resistive switching, reliability metrics, and memory cell selector candidates are summarized from the recent advancement in both industry and academia. Options for 3D memory array architectures are presented for the mass storage application. Finally, the potential application of bottom-up fabrication approaches for effective manufacturing is introduced.     

$${ SIM}^2{ RRAM}$$: a physical model for RRAM devices simulation

In the last few years, resistive random access memory (RRAM) has been proposed as one of the most promising candidates to overcome the current Flash technology in the market of non-volatile memories. These devices have the ability to change their resistance state in a reversible and controlled way applying an external voltage. In this way, the resulting high- and low-resistance states allow the electrical representation of the binary states “0” and “1” without storing charge. Many physical models have been developed with the aim of understanding the mechanisms that control the resistive switching. In this work, we have compiled the main theories accepted as well as their corresponding models for the conduction characteristics. In addition, simulation tools play a very important role in the task of checking these theories and understanding these mechanisms. For this reason, the simulation tool called \(\hbox {SIM}^{2}\hbox {RRAM}\) has been presented. This simulator is capable of replicating the global behavior of RRAM cell based on \(\hbox {HfO}_{x}\).     

Effects of lithography non-uniformity on device electrical behavior. Simple stochastic modeling of material and process effects on device performance

Understanding how lithographic material and processing, affect linewidth roughness (LWR), and finally device operation is of immense importance in future scaled MOS transistors. The goal of this work is to determine the impact of LWR on device operation and to connect material and process parameters with it. To this end, we examine the effects of photoresist polymer length and acid diffusion length on LWR and transistor performance. Through the application of a homemade simulator of the lithographic process, it is shown that photoresists with small polymer chains and small acid diffusion lengths form lines with low LWR and thus lead to transistors with more reliable electrical performance.     

Toward reliable RRAM performance: macro- and micro-analysis of operation processes

Resistive random access memory (RRAM) technology promises superior performance and scalability while employing well-developed fabrication processes. Conductance in insulating oxides employed in RRAM devices can be strongly affected by atomic-level changes that makes cell switching properties extremely sensitive to operation conditions inducing local structural modifications. This opens an opportunity to condition the memory cell stack by forming a conductive filament capable of high frequency, low energy switching. Certain materials with pre-existing conductive paths, in particular some polycrystalline oxides, like hafnia, are shown to respond well to this approach. For this class of materials, the concept of ultra-fast pulse technique as an ultimate method for assessing RRAM switching capabilities in circuitry operations is discussed. Hafnia-based cells demonstrate compliance-free (1R) forming with no current overshoot, low operation currents, and reduced variability.     

Semi-analytical modeling of Ag and Au nanoparticles and fullerene (C60) embedded gate oxide compound semiconductor MOSFET memory devices

In this paper we present an analytical simulation study of Non-volatile MOSFET memory devices with Ag/Au nanoparticles/fullerene (C60) embedded gate dielectric stacks. We considered a long channel planar MOSFET, having a multilayer SiO₂–HfO₂ (7.5?nm)–Ag/Au nc/C60 embedded HfO₂ (6?nm)–HfO₂ (30?nm) gate dielectric stack. We considered three substrate materials GaN, InP and the conventional Si substrate, for use in such MOSFET NVM devices. From a semi-analytic solution of the Poisson equation, the potential and the electric fields in the substrate and the different layers of the gate oxide stack were derived. Thereafter using the WKB approximation, we have investigated the Fowler-Nordheim tunneling currents from the Si inversion layer to the embedded nanocrystal states in such devices. From our model, we simulated the write-erase characteristics, gate tunneling currents, and the transient threshold voltage shifts of the MOSFET NVM devices. The results from our model were compared with recent experimental results for Au nc and Ag nc embedded gate dielectric MOSFET memories. From the studies, the C60 embedded devices showed faster charging performance and higher charge storage, than both the metallic nc embedded devices. The nc Au embedded device displayed superior characteristics compared to the nc Ag embedded device. From the model GaN emerged as the overall better substrate material than Si and InP in terms of higher threshold voltage shift, lesser write programming voltage and better charge retention capabilities.     

Efficient and realistic device modeling from atomic detail to the nanoscale

As semiconductor devices scale to new dimensions, the materials and designs become more dependent on atomic details. NEMO5 is a nanoelectronics modeling package designed for comprehending the critical multi-scale, multi-physics phenomena through efficient computational approaches and quantitatively modeling new generations of nanoelectronic devices as well as predicting novel device architectures and phenomena. This article seeks to provide updates on the current status of the tool and new functionality, including advances in quantum transport simulations and with materials such as metals, topological insulators, and piezoelectrics.     

Graded channel doping junctionless MOSFET: a potential high performance and low power leakage device for nanoelectronic applications

In this paper, a graded channel doping paradigm is proposed to improve the nanoscale double gate junctionless DGJL MOSFET electrical performance. A careful mechanism study based on numerical investigation and a performance comparison between the proposed and conventional design is carried out. The device figures-of-merit, governing the switching and leakage current behavior are investigated in order to reveal the transistor electrical performance for ultra-low power consumption. It is found that the channel doping engineering feature has a profound implication in enhancing the device electrical performance. Moreover, the impact of the high-k gate dielectric on the device leakage performance is also analyzed. The results show that the proposed design with gate stacking demonstrates superior \(I_{{\textit{ON}}}/I_{{\textit{OFF}}}\) ratio and lower leakage current as compared to the conventional counterpart. Our analysis highlights the good ability of the proposed design including a high-k gate dielectric for the reduction of the leakage current. These characteristics underline the distinctive electrical behavior of the proposed design and also suggest the possibility for bridging the gap between the high derived current capability and low leakage power. This makes the proposed GCD-DGJL MOSFET with gate stacking a potential alternative for high performance and ultra-low power consumption applications.     

混凝土仿真材料特性及其应用的试验研究

大型混凝土结构模型试验材料的选择对于试验结果有重要意义。本文作者对低强度仿真混凝土材料的材料配比、力学性能以及实际应用进行了分析研究 ,分析结果表明 ,仿真材料对于大体积混凝土结构的物模试验是比较理想的材料。     

Nanomagnetic logic: compact modeling of field-coupled computing devices for system investigations

In this paper we investigate error rates of nanomagnetic logic devices with perpendicular magnetization by compact modeling. Two different types of nanomagnets for information propagation and logic computing are introduced. The switching behavior of field-coupled nanomagnets is measured and analyzed. A compact model is derived from physics and experimental results are applied to the magnetic compact model. General requirements for fabrication parameters and clocking fields for reliable operation are extracted. We perform simulations and measurements on single devices to demonstrate the accuracy of the macromodel. Simulations on complex systems show that the error rate of a field-coupled magnetic system strongly depends on the variation of the switching field and the strength of the coupling field between the nanomagnets. The error rate of a 1-bit full adder is investigated for varying dot parameters. The results demonstrate the importance of fast simulation tools for investigations on the design of nanomagnetic computing devices and systems.     

EMAP: An aid to understanding energy conversion device performance

There is an ongoing effort to effectively use the computer in the teaching of electromagnetic energy conversion. To that end, a computer program (Electric Machine Analysis Program, or EMAP), was developed to facilitate steady state and dynamic analysis of all common rotating machine performance. EMAP also analyzes magnetic core and transformer operation and provides a format for simple power factor correction calculations. Although the program is designed for educational purposes, it can be, and has been, used to solve practical engineering problems     

提高数字接口设备抗干扰性能的措施

继电保护要求数字接口设备在有故障、受干扰时数据传输不出现任何误码。针对可能存在的电磁干扰采取了有效的抗干扰措施。改进了机箱结构,提高机箱的屏蔽性能;使用了屏蔽性能更好的通信电缆;改进了通信电缆的接地方式;给通信电缆加套磁环;改变电缆和机箱之间的接口方式,在接口处安装滤波器,减小通信电缆上耦合的干扰对数字接口设备造成的影响。结果表明,在国家标准所规定的最高等级的电磁干扰下,继电保护装置中用于监视通道状态的相应计数器没有变化,数字接口设备工作正常。     

Simulation of thin-TFETs using transition metal dichalcogenides: effect of material parameters,gate dielectric on electrostatic device performance

In recent years, significant of scientific research effort has focused on the investigation of transition metal dichalcogenides (TMDC) and other two-dimensional (2D) materials like graphene or boron nitride. Theoretical investigation on the physical aspects of these materials has revealed a whole new range of exciting applications due to wide tunability in electronic and optoelectronic properties. Besides theoretical exploration, these materials have been successfully implemented in electronic and optoelectronic devices with promising results. In this work, we have investigated the effect of monolayer TMDC materials and monolayer TMDC alloys on the performance of thin tunneling field-effect transistors or thin-TFETs. These are promising electronic devices that can achieve steep switching characteristics. We have used the self-consistent determination of the conduction and valence band levels in the device and a simplified model of interlayer tunneling current reported in recent literature that treats scattering semiclassically and incorporates the energy broadening effect using a Gaussian approximation . We have also explored the effect of gate dielectric material variation, interlayer dielectric variation, top gate metal workfunction on the performance of the device. Our study shows that proper choice of material in the top and bottom layers, optimization of materials used as gate and interlayer dielectric are necessary to extract the full potential of these devices. The electron affinity and bandgap of the TMDCs used in different layers effectively control the threshold voltage and current in the device. As seen from our simulation, interlayer materials with high dielectric constant can degrade subthreshold device performance, increase threshold voltage, whereas lowering interlayer thickness could increase device ‘on’ current at the expense of degraded subthreshold performance.     

Ferroelectric properties and reliability of La-Sr-Co-O/Pb-La-Zr-Ti-O/La-Sr-Co-O heterostructures on si for non-volatile memory applications

Abstract

Highly oriented La-Sr-Co-O(LSCO)/Pb-La-Zr-Ti-O(PLZT)/La-Sr-Co-O heterostructures have been successfully grown on a highly oriented Pt film which was grown on a thermally oxidized Si (SiO₂/Si) substrate. The growth of oriented Pt film on the SiO₂/Si substrate was made possible through the use of a thin bismuth titanate template layer which is c-axis oriented on the SiO₂/Si substrate. The hybrid LSCO/Pt structure effectively reduced the sheet resistance of the electrodes by at least 3–5 times compared with a single LSCO electrode. These ferroelectric PLZT capacitors on Si exhibited symmetric hysteresis loops with very desirable ferroelectric properties. The test capacitors showed reliable performance at both room and high (100°C) temperatures with respect to fatigue, retention, aging, and imprint, suggesting that they can be used as reliable, nonvolatile memory elements.     

一种完善电动机启动性能的装置

针对三相交流异步电动机的软启动,给出了一种用单片机、步进电机、多圈电位器组成的软启动装置,分析了软启动装置的工作原理、硬件组成及试验结果。该装置除了可以提高电动机启动时的功率因素,进一步减小启动电流及电网压降,还可以有效地消除常用软启动电路中的高次谐波并且可以方便地实现无级调压。特别合适于对调压精度、运行平稳性有较高要求的中、小型三相交流异步电动机的启动。     

Application of SiC-Si functionally gradient material to thermoelectric energy conversion device

Because of its high–temperature chemical stability, SiC ceramic is a promising material for high-temperature device applications such as thermoelectric energy converters. However, the electrical conductivity of SiC ceramic is too low for it to be used as a thermoelectric energy converter at the cold junction. Therefore, we propose a SiC-Si functionally gradient material (FGM) in order to improve the electrical conductivity of the SiC ceramic at the cold junction. An SiC rod was fired in a temperature gradient furnace. One end of the SiC rod was maintained at 2473 K and the other end was maintained at 1973 K for 30 min. After firing, the porous SiC edge fired at 1973 K was dipped into molten Si in order to infiltrate molten Si into the porous SiC. The microstructure of the FGM is classified into three regions: the SiC-Si composite material; the porous SiC ceramic; and the densified SiC ceramic. The electrical conductivity, the Seebeck coefficient and the thermal conductivity for each region of SiC-Si FGM was measured at 300 K; a figure of merit was calculated. The figure of merit of the SiC-Si FGM at the cold junction, at room temperature, was 10⁸ times higher than that of a nongradient SiC ceramic.     

管式固体氧化物燃料电池模型研究进展

管式结构是固体氧化物燃料电池一种重要结构类型,在设计和密封方面具有优势。近年来建模成为管式固体氧化物燃料电池研究的一种重要手段,已经发展出各种各样的模型。介绍了电化学模型、综合模型(同时耦合电化学、流动及传热)以及动态模型,比较各类模型优点和不足,指出有必要建立能同时从宏观和微观多层面多角度评价电池的全面模型。