Modeling resistive switching materials and devices across scales

Resistance switching devices based on electrochemical processes have attractive significant attention in the field of nanoelectronics due to the possibility of switching in nanosecond timescales, miniaturization to tens of nanometer and multi-bit storage. Their deceptively simple structures (metal-insulator-metal stack) hide a set of complex, coupled, processes that govern their operation, from electrochemical reactions at interfaces, diffusion and aggregation of ionic species, to electron and hole trapping and Joule heating. A combination of experiments and modeling efforts are contributing to a fundamental understanding of these devices, and progress towards a predictive understanding of their operation is opening the possibility for the rational optimization. In this paper we review recent progress in modeling resistive switching devices at multiple scales; we briefly describe simulation tools appropriate at each scale and the key insight that has been derived from them. Starting with ab initio electronic structure simulations that provide an understanding of the mechanisms of operation of valence change devices pointing to the importance of the aggregation of oxygen vacancies in resistance switching and how dopants affect performance. At slightly larger scales we describe reactive molecular dynamics simulations of the operation of electrochemical metallization cells. Here the dynamical simulations provide an atomic picture of the mechanisms behind the electrochemical formation and stabilization of conductive metallic filaments that provide a low-resistance path for electronic conduction. Kinetic Monte Carlo simulations are one step higher in the multiscale ladder and enable larger scale simulations and longer times, enabling, for example, the study of variability in switching speed and resistance. Finally, we discuss physics-based simulations that accurately capture subtleties of device behavior and that can be incorporated in circuit simulations.     

Memristive computing devices and applications

Advances in electronics have revolutionized the way people work, play and communicate with each other. Historically, these advances were mainly driven by CMOS transistor scaling following Moore’s law, where new generations of devices are smaller, faster, and cheaper, leading to more powerful circuits and systems. However, conventional scaling is now facing major technical challenges and fundamental limits. New materials, devices, and architectures are being aggressively pursued to meet present and future computing needs, where tight integration of memory and logic, and parallel processing are highly desired. To this end, one class of emerging devices, termed memristors or memristive devices, have attracted broad interest as a promising candidate for future memory and computing applications. Besides tremendous appeal in data storage applications, memristors offer the potential to enable efficient hardware realization of neuromorphic and analog computing architectures that differ radically from conventional von Neumann computing architectures. In this review, we analyze representative memristor devices and their applications including mixed signal analog-digital neuromorphic computing architectures, and highlight the potential and challenges of applying such devices and architectures in different computing applications.     

Stochastic modeling of bipolar resistive switching in metal-oxide based memory by Monte Carlo technique

A stochastic model of the resistive switching mechanism in bipolar metal-oxide based resistive random access memory (RRAM) is presented. The distribution of electron occupation probabilities obtained is in agreement with previous work. In particular, a low occupation region is formed near the cathode. Our simulations of the temperature dependence of the electron occupation probability near the anode and the cathode demonstrate a high robustness of the low occupation region. This result indicates that a decrease of the switching time with increasing temperature cannot be explained only by reduced occupations of the vacancies in the low occupation region, but is related to an increase of the mobility of the oxide ions. A hysteresis cycle of RRAM switching simulated with the stochastic model including the ion dynamics is in good agreement with experimental results.     

Multiscale modeling of oxide RRAM devices for memory applications: from material properties to device performance

RRAM devices have been subjected to intense research efforts and are proposed for nonvolatile memory and neuromorphic applications. In this paper we describe a multiscale modeling platform connecting the microscopic properties of the resistive switching material to the electrical characteristics and operation of RRAM devices. The platform allows self-consistently modeling the charge and ion transport and the material structural modifications occurring during RRAM operations and reliability, i.e., conductive filament creation and partial disruption. It allows describing the electrical behavior (current, forming, switching, cycling, reliability tests) of RRAM devices in static and transient conditions and their dependence on external conditions (e.g., temperature). Thanks to the kinetic Monte Carlo approach, the inherent variability of physical processes is properly accounted for. Simulation results can be used both to investigate material properties (including atomic defect distributions) and to optimize stack and bias pulses for optimum device performances and reliability.     

Physics-based drain current modeling of gate-all-around junctionless nanowire twin-gate transistor (JN-TGT) for digital applications

Vertically stacked dielectric separated independently controlled gates can be used to realize dual-threshold voltage on a single silicon channel MOS device. This approach significantly reduces the effective layout area and is similar to merging two transistors in series. This multiple independent gate device enables the design of new class of compact logic gates with low power and reduced area. In this paper, we present the junctionless concept based twin gate transistor for digital applications. To analyse the appropriate behaviour of device, this paper presents the modeling, simulation and digital overview of novel gate-all-around junctionless nanowire twin-gate transistor for advanced ultra large scale integration technology. This low power single MOS device gives the full functionality of “AND” gate and can be extended to full functionality of 2-input digital “NAND” gate. To predict accurate behaviour, a physics based analytical drain current model has been developed which also includes the impact of gate depleted source/drain regions. The developed model is verified using ATLAS 3D device simulator. This single channel device can function as “NAND” gate even at low operating voltage.     

Nanomagnetic logic: compact modeling of field-coupled computing devices for system investigations

In this paper we investigate error rates of nanomagnetic logic devices with perpendicular magnetization by compact modeling. Two different types of nanomagnets for information propagation and logic computing are introduced. The switching behavior of field-coupled nanomagnets is measured and analyzed. A compact model is derived from physics and experimental results are applied to the magnetic compact model. General requirements for fabrication parameters and clocking fields for reliable operation are extracted. We perform simulations and measurements on single devices to demonstrate the accuracy of the macromodel. Simulations on complex systems show that the error rate of a field-coupled magnetic system strongly depends on the variation of the switching field and the strength of the coupling field between the nanomagnets. The error rate of a 1-bit full adder is investigated for varying dot parameters. The results demonstrate the importance of fast simulation tools for investigations on the design of nanomagnetic computing devices and systems.     

MMC整流器开关器件的损耗及温升建模研究

适用于环境保护需求,替代船上柴油发电机发电的岸电系统蓬勃发展。应用于岸电系统的模块化多电平整流器工作时温升过高会降低其运行可靠性,损耗是反映其温升的重要参数。在忽略整流器其他损耗因素情况下,针对开关器件的损耗建立简化模型,并结合电热转换原理建立模块化多电平变换器(MMC)整流器半桥子模块开关器件的温升分析模型,从而确定温升与开关器件损耗的关系式。基于建立的损耗及温升模型,仿真分析载波移相和最近电平逼近2种调制方式对开关器件温升的影响,与实际工程条件下的验证一致。结果表明载波移相调制方式下开关器件温升更小,实际工程中选用该调制方式可以在一定程度上抑制温升。文中搭建的温升模型可为后续研究其他温升抑制措施提供模型依据,可验证温升抑制措施的有效性。     

Piecewise empirical model (PEM) of resistive memory for pulsed analog and neuromorphic applications

With the end of Dennard scaling and the ever-increasing need for more efficient, faster computation, resistive switching devices (ReRAM), often referred to as memristors, are a promising candidate for next generation computer hardware. These devices show particular promise for use in an analog neuromorphic computing accelerator as they can be tuned to multiple states and be updated like the weights in neuromorphic algorithms. Modeling a ReRAM-based neuromorphic computing accelerator requires a compact model capable of correctly simulating the small weight update behavior associated with neuromorphic training. These small updates have a nonlinear dependence on the initial state, which has a significant impact on neural network training. Consequently, we propose the piecewise empirical model (PEM), an empirically derived general purpose compact model that can accurately capture the nonlinearity of an arbitrary two-terminal device to match pulse measurements important for neuromorphic computing applications. By defining the state of the device to be proportional to its current, the model parameters can be extracted from a series of voltages pulses that mimic the behavior of a device in an analog neuromorphic computing accelerator. This allows for a general, accurate, and intuitive compact circuit model that is applicable to different resistance-switching device technologies. In this work, we explain the details of the model, implement the model in the circuit simulator Xyce, and give an example of its usage to model a specific \(\hbox {Ta}/\hbox {TaO}_{\mathrm{x}}\) device.     

Review of mechanisms proposed for redox based resistive switching structures

Mechanisms proposed for redox-based memristors are reviewed. Emphasis is given on MIM (metal/insulator/metal) devices of the type MOM where the insulator is an oxide. The oxide conducts oxygen via oxygen vacancies. MOM devices in which the insulator conducts intercalated cations are analogous to the ones with mobile oxygen vacancies. Switching, memory and short term hysteresis are three independent phenomena governed by different mechanisms. A necessary condition for memory is presented. Electroforming, filament formation and alteration and I-V curve crossing are discussed. A new mechanism for unipolar switching is suggested. The metal electrodes are sorted into four types according to the nature of their oxygen transfer. The effect of humidity in the ambient is discussed.     

A visual-inspection system for switching devices

This paper considers the implementation of an automated system for monitoring and controlling switching devices in remote-controlled stations. Switching-equipment breakdowns in the process of operation that cannot be quickly tracked without being at the location itself create a problem. The concept of a visual-inspection system for remote devices is developed. The system operates in the standalone mode without human intervention, allowing the dispatcher to visually monitor the condition of plants. The control zone covers the external condition of equipment and the heating parameters of its current-carrying parts. The visual-inspection system is designed to work with the telemetry and remote-signaling systems already installed at a plant. The proposed technology provides the power dispatcher with the complete information on a plant and allows the maintenance personnel to quickly respond to emergencies so as to prevent electricalequipment breakdown and accidents.     

Extraction and modeling methods for FET devices

The proposed method is based on spline functions, takes into account thermal and noise effects, allows a scaling of different FET device geometries, and is available in commercial CAD software like Agilents Series IV or ADS     

Current-interruption testing of vacuum switching devices

In the international IEC standards for medium and HV switching devices no distinction in test requirements is made between switching devices with different arc-quenching media, like SF₆, oil and vacuum. This had led to the situation that due to the different technology of arc interruption applied, various aspects of the prescribed test-procedures have a different weight in terms of severity for various types of breakers. Additional test-requirements and interpretations that are specific to vacuum switching devices have been formulated commonly by the joint major test laboratories. In this contribution, the background and practical application of several procedures, now generally adopted by certifying test-laboratories, regarding the peculiarities of vacuum switching devices are elucidated. Because the vacuum switching device has an excellent capability to interrupt current of high frequency, the main part of this contribution will be related to the consequences for test procedures of this aspect that is not encountered in SF₆ or oil breakers. In particular, the judgment of non-sustained disruptive discharges, multiple re-ignition and virtual current chopping in test-circuits is addressed. Results of a new high-resolution high-frequency current-zero measuring system are presented. This system is able to give insight into the high-frequency arc phenomena in the immediate vicinity of are interruption, and is designed to get more specific information on arc behavior during standard high-power tests     

Capacitor placement for switching noise reduction using genetic algorithms and distributed computing

This work investigates capacitor placement on a printed circuit board (PCB) to reduce the effect of simultaneous switching noise as a genetic algorithm (GA) search problem. The solution process makes use of distributed computing resources available on a local area network in order to solve larger problems more efficiently. The objective is to determine the number of added capacitors with minimum cost, and their position on the PCB, while keeping the maximum voltage deviation within some specified noise margin. The presence of capacitors at the selected positions is represented by a stream of zeros and ones, which is interpreted as a genotype. At each generation, the GA assesses the fitness function of a population of genotypes using linear transient circuit analysis, which involves a single matrix inversion, by determining the maximum voltage dip given the capacitor locations. For large systems, the fitness calculations are divided among several processors according to a simple distributed computing algorithm.     

Numerical techniques for modeling guided-wave photonic devices

Accurate modeling of photonic devices is essential for the development of new, higher performance optical components required by current and future high-bandwidth communications systems. This paper reviews several key techniques for such modeling, many of which are used in commercial design tools. These include several mode-solving techniques, the beam propagation method, the method of lines, and the finite-difference time-domain technique     

On distributed computing for on-line power system applications

This paper reviews the state-of-the-art of distributed computing (also called coarse-grained parallel computing) technology, which has rapidly evolved over the last two decades, with emphasis on the trend towards standardization that has occurred in the last few years. The review is focused on on-line power system applications, and excludes fine-grained parallel applications and planning applications. The applications are divided into two categories. The first category consists of applications where the motivation for distributed processing stems from geographical distribution. The second category is the rest of the on-line applications where the parallelism stems from the easily decomposable abstract (mathematical) model of the problem as opposed to being ‘physically based’. Some of the issues in such distributed computing are illustrated using the example of security-constrained optimal power flows. The paper concludes with some projections on the use of this technology in energy management systems (EMS) in the near future.     

A .NET solution for distributed computing applications

Distributed computing is used to solve computational complexity problems. This paper explores the suitability of the .NET platform and XML Web services for distributed computing applications. This study demonstrates the practical feasibility of a .NET Web-services application in distributed computing and it also exposes APIs on the Internet. Thus from the experimental results, the speed of the algorithm introduced by Web services are determined and the cluster performance is achieved by scheduling algorithm, which properly selects the size of the work slice for each client to assign.     

A lossless switching technique for smart grid applications

Smart grid is an upgrade of the existing electricity infrastructure in which integration of non conventional energy sources are an integral part. This leads to the introduction of harmonics and increased switching losses in the system. Thus there is a need of loss less switching techniques for smart grid applications. Switched mode power supplies (SMPSs) are being extensively used in most power processes [1]. Developments were carried out centered on hard switched converters, where switching frequency is limited to 10 s of kHz [2]. The uses of soft switching techniques, [3], [4], [5], [6] zero voltage switching (ZVS) or zero current switching (ZCS), is an attempt to substantially reduce the switching losses and hence attain high efficiency at increased switching frequency. The soft-switching topologies belong to families namely resonant load converters [3], resonant switch converters [2], [4], resonant transition converters [5], [6], and most recently active clamped PWM converters [7], [8], [9]. The active clamp topology adds an active clamp network, consisting of a small auxiliary switch in series with a capacitance plus the associated drive circuitry to the traditional hard switch converters. The proposed paper basically deals with the design, modeling and simulation of a ZVS–PWM active clamp/reset forward converter having features like zero switching power losses, constant frequency and PWM operation, Soft-switching for all devices and Low voltage stresses on active devices due to clamping action.     

Pulse switching characteristics of MAGTs for pulsed power applications

For pulsed power systems such as lasers and accelerators, semiconductor switches with their longer service life have actively been developed as replacements for thyratrons. The MOS-driven thyristors are suitable for pulsed power applications because they have high-power handling and fast turn-on capabilities. The MOS-assisted gate-triggered thyristor (MAGT), designed especially for pulsed power, is a promising candidate in this field. This paper presents the results of an investigation into the performance of MAGTs. Using a pulse-forming network (PEN), the pulse-switching characteristics and the dynamic resistance characteristics during the current flow are investigated. A maximum current density of 21.8 kA/cm² and di/dt of 106 kA/μs/cm² with 1550-V anode voltage on a single-shot basis were obtained. Furthermore, a life test with 10⁹ shots at a high repetition rate showed no degradation in the observed characteristics. Based on these experimental results, a carrier flow model of MAGT during turn-on process is proposed and the turn-on mechanism is considered.