Impact of channel length,gate insulator thickness,gate insulator material,and temperature on the performance of nanoscale FETs

Aggressive technology scaling as per Moore’s law has led to elevated power dissipation levels owing to an exponential increase in subthreshold leakage power. Short channel effects (SCEs) due to channel length reduction, gate insulator thickness change, application of high-k gate insulator, and temperature change in a double-gate metal–oxide–semiconductor field-effect transistor (DG MOSFET) and carbon nanotube field-effect transistor (CNTFET) were investigated in this work. Computational simulations were performed to investigate SCEs, viz. the threshold voltage (V_th) roll-off, subthreshold swing (SS), and I_on/I_off ratio, in the DG MOSFET and CNTFET while reducing the channel length. The CNTFET showed better performance than the DG MOSFET, including near-zero SCEs due to its pure ballistic transport mechanism. We also examined the threshold voltage (V_th), subthreshold swing (SS), and I_on/I_off ratio of the DG MOSFET and CNTFET with varying gate insulator thickness, gate insulator material, and temperature. Finally, we handpicked almost similar parameters for both the CNTFET and DG MOSFET and carried out performance analysis based on the simulation results. Comparative analysis of the results showed that the CNTFET provides 47.8 times more I_on/I_off ratio than the DG MOSFET. Its better control over the threshold voltage, near-zero SCEs, high on-current, low leakage power consumption, and ability to operate at high temperature make the CNTFET a viable option for use in enhanced switching applications and low-voltage digital applications in nanoelectronics.     

Heterogate junctionless tunnel field-effect transistor: future of low-power devices

Gate dielectric materials play a key role in device development and study for various applications. We illustrate herein the impact of hetero (high-k/low-k) gate dielectric materials on the ON-current (\(I_{\mathrm{ON}}\)) and OFF-current (\(I_{\mathrm{OFF}}\)) of the heterogate junctionless tunnel field-effect transistor (FET). The heterogate concept enables a wide range of gate materials for device study. This concept is derived from the well-known continuity of the displacement vector at the interface between low- and high-k gate dielectric materials. Application of high-k gate dielectric material improves the internal electric field in the device, resulting in lower tunneling width with high \(I_{\mathrm{ON}}\) and low \(I_{\mathrm{OFF}}\) current. The impact of work function variations and doping on device performance is also comprehensively investigated.     

Nanoscale circuit implementation using tri-metal gate engineered nanowire MOSFET with gate stack for analog/RF applications

In this work, the potential benefit of tri-metal gate engineered nanowire MOSFET with gate stack for analog/RF applications is developed and presented. A systematic, quantitative investigation of main figure of merit for the device is carried out to demonstrate its improved RF/analog performance. The results show an improvement in drain current, \(I_{\mathrm{on}} /I_{\mathrm{off}}\) ratio, transconductance, unity-gain frequency (\(f_{\mathrm{T}}\)), maximum oscillation frequency (\(f_{\mathrm{max}}\)) providing superior RF performance as compared to single and dual-metal gate stack nanowire MOSFET. The suitability of the device for analog/RF applications is also analyzed by implementing the device in a low-noise amplifier circuit, and the S-parameter values are estimated.     

Graded channel doping junctionless MOSFET: a potential high performance and low power leakage device for nanoelectronic applications

In this paper, a graded channel doping paradigm is proposed to improve the nanoscale double gate junctionless DGJL MOSFET electrical performance. A careful mechanism study based on numerical investigation and a performance comparison between the proposed and conventional design is carried out. The device figures-of-merit, governing the switching and leakage current behavior are investigated in order to reveal the transistor electrical performance for ultra-low power consumption. It is found that the channel doping engineering feature has a profound implication in enhancing the device electrical performance. Moreover, the impact of the high-k gate dielectric on the device leakage performance is also analyzed. The results show that the proposed design with gate stacking demonstrates superior \(I_{{\textit{ON}}}/I_{{\textit{OFF}}}\) ratio and lower leakage current as compared to the conventional counterpart. Our analysis highlights the good ability of the proposed design including a high-k gate dielectric for the reduction of the leakage current. These characteristics underline the distinctive electrical behavior of the proposed design and also suggest the possibility for bridging the gap between the high derived current capability and low leakage power. This makes the proposed GCD-DGJL MOSFET with gate stacking a potential alternative for high performance and ultra-low power consumption applications.     

MOSFET开关过程的研究及米勒平台振荡的抑制

设计功率MOSFET驱动电路时需重点考虑寄生参数对电路的影响。米勒电容作为MOSFET器件的一项重要参数,在驱动电路的设计时需要重点关注。重点观察了MOSFET的开通和关断过程中栅极电压、漏源极电压和漏源极电流的变化过程,并分析了米勒电容、寄生电感等寄生参数对漏源极电压和漏源极电流的影响。分析了栅极电压在米勒平台附近产生振荡的原因,并提出了抑制措施,对功率MOSFET的驱动设计具有一定的指导意义。     

Accurate modeling of Metal/HfO<Subscript>2</Subscript>/Si capacitors

In this work, we study the differences caused in the Capacitance-Voltage (C-V) characteristics of MOS devices when SiO₂ is replaced by HfO₂ as the gate dielectric. A self-consistent Schrödinger-Poisson solver has been developed to include the effects of quantum confinement and the influence of different parameters such as the effective mass, barrier height, and dielectric constant (κ) of the gate insulator material. Two different devices are considered: A Double Gate MOSFET and a Surrounding Gate Transistor. The validity of the Equivalent Oxide Thickness (EOT) is studied.     

Investigation of trigate JLT with dual-<Emphasis Type="Italic">k</Emphasis> sidewall spacers for enhanced analog/RF FOMs

This paper shows the potential benefits of using the trigate junctionless transistor (JLT) with dual-k sidewall spacers to enhance analog/radio-frequency (RF) performance at 20-nm gate length. Simulation study shows that the source-side-only dual-k spacer (dual-kS) JLT can improve all analog/RF figures of merit (FOMs) compared with the conventional JLT structure. The dual-kS JLT shows improvement in intrinsic voltage gain (\(A_{V0}\)) by \(\sim \)44.58 %, unity-gain cutoff frequency (\(f_\mathrm{T}\)) by \(\sim \)7.67 %, and maximum oscillation frequency (\(f_\mathrm{MAX}\)) by \(\sim \)6.4 % at drain current \((I_\mathrm{ds}) = 10\,\upmu \hbox {A}/\upmu \hbox {m}\) compared with the conventional JLT structure. To justify the improvement in all analog/RF FOMs, it is also found that the dual-kS structure shows high electron velocity near the source region because of the presence of an additional electric field peak near the source region, resulting in increased electron transport efficiency and hence improved transconductance (\(g_\mathrm{m}\)). Furthermore, the dual-kS JLT shows a reduction in the electric field value near the drain end, thereby improving short-channel effects.     

Selection of the heating method of semiconductor devices during their testing in a high-conductivity state

Possible heating methods of power semiconductor devices during their testing in a high-conductivity state are discussed. It is shown that the diffusion capacitance of the p–n junction has a significant effect on measurements of device parameters. The effect of the diffusion capacitance on the results of testing of power semiconductor devices at various shapes of heating-current pulses was investigated. Conclusions on the possibility of using current pulses of various shapes for testing power semiconductor devices in the highconductivity state are drawn.     

Rapid measurement of intravoxel incoherent motion (IVIM) derived perfusion fraction for clinical magnetic resonance imaging

Objective

This study aimed to investigate the reliability of intravoxel incoherent motion (IVIM) model derived parameters D and f and their dependence on b value distributions with a rapid three b value acquisition protocol.

Materials and methods

Diffusion models for brain, kidney, and liver were assessed for bias, error, and reproducibility for the estimated IVIM parameters using b values 0 and 1000, and a b value between 200 and 900, at signal-to-noise ratios (SNR) 40, 55, and 80. Relative errors were used to estimate optimal b value distributions for each tissue scenario. Sixteen volunteers underwent brain DW-MRI, for which bias and coefficient of variation were determined in the grey matter.

Results

Bias had a large influence in the estimation of D and f for the low-perfused brain model, particularly at lower b values, with the same trends being confirmed by in vivo imaging. Significant differences were demonstrated in vivo for estimation of D (P = 0.029) and f (P < 0.001) with [300,1000] and [500,1000] distributions. The effect of bias was considerably lower for the high-perfused models. The optimal b value distributions were estimated to be brain_500,1000, kidney_300,1000, and liver_200,1000.

Conclusion

IVIM parameters can be estimated using a rapid DW-MRI protocol, where the optimal b value distribution depends on tissue characteristics and compromise between bias and variability.

     

Uncoupled mode space approach for analysis of nanoscale strained junctionless double-gate MOSFET

In this paper, we have analyzed the electrical characteristics of Strained Junctionless Double-Gate MOSFET (Strained JL DG MOSFET). A quantum mechanical transport approach based on non-equilibrium Green’s function (NEGF) method with the use of uncoupled mode space approach has been employed for this analysis. We have investigated the effects of high-\(\kappa \) materials as gate and spacer dielectrics on the device performance. Low OFF-state current, low DIBL, and low subthreshold slope have been obtained with increase in the gate and spacer dielectric constants. The electrical characteristics of strained JL DG MOSFET have also been compared with conventional JL DG MOSFET and Inversion Mode (IM) DG MOSFET. The results indicated that the Strained JL DG MOSFET outperforms the conventional JL and IM DG MOSFETs, yielding higher values of drain current.     

Analog performance investigation of dual electrode based doping-less tunnel FET

In this paper, we have proposed a device and named it dual electrode doping-less TFET (DEDLTFET), in which electrodes on top and bottom of source and drain are considered to enhance the ON state current and Analog performances. The charge plasma technique is used to generate electron’s and hole’s clouding depending upon their respective work functions at top and bottom of source/drain electrode. Band-to-band-tunneling rate is similar on both sides of source-channel junctions, which increases ON state current. The analog performance parameters of DEDLTFET are investigated and using device simulation the demonstrated characteristics are compared with doping-less (DLTFET) and the conventional doped double gate TFET (DGTFET), such as transconductance \((\hbox {g}_\mathrm{m})\), transconductance to drain current ratio \((\hbox {g}_\mathrm{m}/\hbox {I}_\mathrm{D})\), output-conductance (g\(_{d})\), output resistance \((\hbox {r}_\mathrm{d})\), early voltage \((\hbox {V}_\mathrm{EA})\), intrinsic gain \((\hbox {A}_\mathrm{V})\), total gate capacitance \((\hbox {C}_\mathrm{gg})\) and unity gain frequency \((\hbox {f}_\mathrm{T})\). From the simulation results, it is observed that DEDLTFET has significantly improved analog performance as compared to DGTFET and DLTFET.     

High-blocking-voltage UMOSFETs with reformed electric field distribution

A high-performance vertical GaN metal–oxide–semiconductor field-effect transistor (MOSFET) with a U-shaped gate (UMOSFET) and high blocking voltage is proposed. The main concept behind this work is to reform the electric field distribution to achieve high blocking voltage. The proposed structure includes p-regions in the drift region, which we call reformed electric field (REF) regions. Simulations using the two-dimensional SILVACO simulator reveal the optimum doping concentration, and width and height of the REF regions to achieve the maximum depletion region at the breakdown voltage in the drift region. Also, the electric field distribution in the REF-UMOSFET is reformed by producing additional peaks, which decreases the common peaks under the gate trench. We discuss herein the impact of the height, width, and doping concentration of the REF regions on the ON-resistance (R_ON) and blocking voltage. The blocking voltage, specific ON-resistance, and figure of merit \( \left( {{\text{FOM}} = \frac{{V_{{{\text{BR}}}}^{2} }}{{R_{{{\text{ON}}}} }}} \right) \) are 1140 V, 0.587 mΩ cm² (V_GS = 15 V, V_DS = 1 V), and 2.214 GW/cm², respectively. The blocking voltage and FOM are increased by about 72 % and 171 % in comparison with a conventional UMOSFET (C-UMOSFET).     

Relative enhanced diffusivity: noise sensitivity,protocol optimization,and the relation to intravoxel incoherent motion

Objective

To explore the relationship between relative enhanced diffusivity (RED) and intravoxel incoherent motion (IVIM), as well as the impact of noise and the choice of intermediate diffusion weighting (b value) on the RED parameter.

Materials and methods

A mathematical derivation was performed to cast RED in terms of the IVIM parameters. Noise analysis and b value optimization was conducted by using Monte Carlo calculations to generate diffusion-weighted imaging data appropriate to breast and liver tissue at three different signal-to-noise ratios.

Results

RED was shown to be approximately linearly proportional to the IVIM parameter f, inversely proportional to D and to follow an inverse exponential decay with respect to D*. The choice of intermediate b value was shown to be important in minimizing the impact of noise on RED and in maximizing its discriminatory power. RED was shown to be essentially a reparameterization of the IVIM estimates for f and D obtained with three b values.

Conclusion

RED imaging in the breast and liver should be performed with intermediate b values of 100 and 50 s/mm², respectively. Future clinical studies involving RED should also estimate the IVIM parameters f and D using three b values for comparison.

     

DCE-MRI of hepatocellular carcinoma: perfusion quantification with Tofts model versus shutter-speed model—initial experience

Objective

To quantify hepatocellular carcinoma (HCC) perfusion and flow with the fast exchange regime-allowed Shutter-Speed model (SSM) compared to the Tofts model (TM).

Materials and methods

In this prospective study, 25 patients with HCC underwent DCE-MRI. ROIs were placed in liver parenchyma, portal vein, aorta and HCC lesions. Signal intensities were analyzed employing dual-input TM and SSM models. ART (arterial fraction), K ^trans (contrast agent transfer rate constant from plasma to extravascular extracellular space), v _e (extravascular extracellular volume fraction), k _ep (contrast agent intravasation rate constant), and τ _i (mean intracellular water molecule lifetime) were compared between liver parenchyma and HCC, and ART, K ^trans, v _e and k _ep were compared between models using Wilcoxon tests and limits of agreement. Test–retest reproducibility was assessed in 10 patients.

Results

ART and v _e obtained with TM; ART, v _e , k _e and τ _i obtained with SSM were significantly different between liver parenchyma and HCC (p < 0.04). Parameters showed variable reproducibility (CV range 14.7–66.5 % for both models). Liver K ^trans and v _e ; HCC v _e and k _ep were significantly different when estimated with the two models (p < 0.03).

Conclusion

Our results show differences when computed between the TM and the SSM. However, these differences are smaller than parameter reproducibilities and may be of limited clinical significance.

     

A first-principles study of the structural,elastic, electronic,vibrational, and optical properties of BaSe<Subscript>1−<Emphasis Type="Italic">x</Emphasis></Subscript>Te<Subscript><Emphasis Type="Italic">x</Emphasis></Subscript>

The structural, elastic, electronic, vibrational, and optical properties of BaSe_1?xTe_x alloys are investigated by means of the full-potential linearized augmented plane wave method. The exchange–correlation effects are treated with the local density approximation, as well as the GGA-PBE, GGA-PBEsol, and GGA?+?mBJ schemes of the generalized gradient approximation. Ternary BaSe_1?xTe_x compounds have not yet been synthesized. Improved predictions of the structural parameters are obtained using the GGA-PBEsol approach. Calculations of the electronic and optical properties with the GGA?+?mBJ approach yield accurate results. Ternary BaSe_1?xTe_x alloys are wide-band-gap semiconductors with a direct gap Γ–Γ. The upper valence band is mainly due to Se p and Te p states, while the bottom of the conduction band results essentially from Ba d states. The dielectric function, refractive index, reflectivity, absorption coefficient, and energy-loss function are calculated in the range 0–35 eV. The increase in x gives rise to a redshift of the optical spectra. BaSe_1?xTe_x alloys exhibit reflective properties of metals in some energy ranges. The static dielectric constant ?₁(0) and the static refractive index n₀ are calculated. The investigation of the elastic and vibrational properties shows that ternary BaSe_1?xTe_x should be mechanically and dynamically stable, elastically anisotropic, brittle, and relatively soft.     

Analysis and modeling of unipolar junction transistor with excellent performance: a novel DG MOSFET with $${N}^{+}{-}{P}^{-}$$ junction

We propose herein a new dual-gate metal–oxide–semiconductor field-effect transistor (MOSFET) with just a unipolar junction (UJ-DG MOSFET) on the source side. The UJ-DG MOSFET structure is constructed from an \({N}^{+}\) region on the source side with the rest consisting of a \({P}^{-}\) region over the gate and drain, forming an auxiliary gate over the drain region with appropriate length and work function (named A-gate), converting the drain to an \({N}^{+}\) region. The new structure behaves as a MOSFET, exhibiting better efficiency than the conventional double-gate MOSFET (C-DG MOSFET) thanks to the modified electric field. The amended electric field offers advantages including improved electrical characteristics, reliability, leakage current, \({I}_{\mathrm{ON}}/I_{\mathrm{OFF}}\) ratio, gate-induced drain leakage, and electron temperature. Two-dimensional analytical models of the surface potential and electric field over the channel and drain are applied to investigate the drain current in the UJ-DG MOSFET. To confirm their accuracy, the MOSFET characteristics obtained using the 2D Atlas simulator for the UJ-DG and C-DG are analyzed and compared.     

Quantitative effects of acquisition duration and temporal resolution on the measurement accuracy of prostate dynamic contrast-enhanced MRI data: a phantom study

Objectives

The aim of this study was to investigate the effect of the temporal resolution (T _res) and acquisition duration (AD) on the measurement accuracy of contrast concentration–time curves (CTCs), and derived phenomenological and pharmacokinetic parameter values, in a dynamic contrast-enhanced MRI experiment using a novel phantom test device.

Materials and methods

‘Ground truth’ CTCs were established using a highly precise optical imaging system. These precisely known CTCs were produced in an anthropomorphic environment, which mimicked the male pelvic region, and presented to the MRI scanner for measurement. The T _res was varied in the range [2–24.4 s] and the AD in the range [30–600 s], and the effects on the measurement accuracy were quantified.

Results

For wash-in parameter measurements, large underestimation errors (up to 40%) were found using T _res values ≥16.3 s; however, the measured wash-out rate did not vary greatly across all T _res values tested. Errors in derived K ^trans and v _e values were below 14 and 12% for acquisitions with {T _res ≤ 8.1 s, AD ≥ 360 s} and {T _res ≤ 16.3 s, AD ≥ 360 s}, respectively, but increased dramatically outside these ranges.

Conclusions

Errors in measured wash-in, wash-out, K ^trans, and v _e parameters were minimised using T _res ≤ 8.1 s and AD ≥ 360 s, with large errors recorded outside of this range.

     

DFT study on structural,electronic, and optical properties of cubic and monoclinic CuO

First-principles calculations were made to explore the structural, electronic, and optical properties of copper oxide (CuO) with monoclinic (m-CuO) and cubic (c-CuO) structures. We calculated the equilibrium structural parameters: lattice parameters (a, b, and c), angle \(\beta \), and volume V. The obtained results were in good agreement with the experimental data reported in the literature. The cohesive energy showed that m-CuO is more stable than c-CuO. The band structure indicated that c-CuO is an indirect band gap semiconductor with a band gap of 0.87 eV along R–G, while m-CuO has a metallic behavior. Furthermore, electrovalent and covalent bonds were observed in both c-CuO and m-CuO. The linear optical properties were calculated and analyzed along different polarization directions of the incident light. The results indicated that m-CuO possesses optical anisotropic properties. In particular, c-CuO can be used as a potential UV detector material because of its high absorption coefficient (356351.3).     

Asymmetric dual-k spacer trigate FinFET for enhanced analog/RF performance

In this paper, we aim to explore the potential benefits of using source side only dual-k spacer (Dual-kS) trigate FinFET structure to improve the analog/RF figure of merit (FOM) for low power operation at 20 nm gate length. It has been observed from the results that Dual-kS (inner spacer high-k) FinFET structure improves the coupling of the gate fringe field to the underlap region towards the source side and results into improvement in transconductance \((g_{m})\) and output conductance \((g_{ds})\). It was also found that drain side only dual-k spacer (Dual-kD) improves the coupling of the gate fringe field to the underlap region towards the drain side which helps to shift away the drain field from gate edge and results into improvement in output conductance \((g_{ds})\) only at the cost of increase in Miller capacitance. A comparative simulation study has been performed on four different device structures namely both side low-k spacers (conventional), both side dual-k spacer (Dual-kB), Dual-kD and Dual-kS structures. From the simulation study, it was found that that Dual-kS structure has potential to improve \(g_{m}\) by \(\sim \)8.7 %, \(g_{ds}\) by \(\sim \)32.24 %, intrinsic gain \((A_{V0})\) by \(\sim \)11.44 %, early voltage \((V_{EA})\) by \(\sim \)47.59 %, maximum oscillation frequency (\(f_{MAX}\)) by \(\sim \)1.7 % and the ratio of gate-source capacitance and gate-drain capacitance \((C_{gs}/C_{gd})\) by \(\sim \)15.27 % with a slight reduction in the value of unity gain cut-off frequency (\(f_{T}\)) by \(\sim \)0.58 % in comparison to the conventional structure at drain current \((I_{ds})\) of \(10\,\upmu \)A/\(\upmu \)m. Furthermore, to reduce the drain field influence on the channel region, we also studied the effect of asymmetric drain extension length on Dual-kS FinFET structure.     

An improved model to assess temperature-dependent DC characteristics of submicron GaN HEMTs

A modified analytical model for the current–voltage (I–V) characteristics of AlGaN/GaN high-electron-mobility transistors (HEMTs) is presented, considering the temperature-dependent: (a) Schottky barrier height, (b) energy bandgap discontinuity, (c) carrier mobility, and (d) saturation velocity. It is demonstrated that the Schottky barrier height and energy bandgap discontinuity decrease with increase of the temperature. The effective mobility of the two-dimensional electron gas (2-DEG) also decreases with increasing temperature, causing a reduction in the output current of the device. The model was tested over a wide range of temperatures (300–500 K) and bias, and it was observed that the developed model can successfully predict the I–V characteristic of the device with reasonable accuracy, especially at high temperatures (\(\sim 500\) K). It is shown that the developed model offers, on average, a 39 % improvement for the temperature variation, from 300–500 K, relative to the best model reported in literature.