Impact of series resistance on Si nanowire MOSFET performance

In gate all around (GAA) nanowire (NW) MOSFETs large series resistance due to narrow width extension regions is an important issue, playing a critical role in determining device and circuit performance. In this paper, we present a series resistance model and analyze its dependence on geometry/process parameters. The series resistance is modelled by dividing it into five resistance components namely spreading resistance, extension resistance, interface resistance, deep source-drain resistance and contact resistance. The model is validated using 3-D device simulations of 22 nm GAA devices with Source/Drain extension (SDE) length of 15 nm to 35 nm, diameter of 8 nm to 16 nm and oxide thickness of 10 A to 40 A for both n-FET and p-FET. It is found that the spreading resistance due to lateral doping gradient contributes significantly to the total series resistance. Further, the dependence of NW device performance on series resistance is quantitatively investigated with change of diameter, SDE length and Source/Drain (S/D) implantation dose. Results show a strong NW device performance dependence on S/D doping profile and extension length defining a design trade-off between Short Channel Effects (SCEs) and series resistance. It is seen that the increase in series resistance due to increase of extension length or decrease of implantation dose beyond a certain limit reduces the device drive current significantly with nearly constant OFF-state leakage current. Hence, optimization of extension length and S/D implant dose is an important device design issue for sub 22 nm technology nodes.     

Enhancing the design and performance of a gate-all-around (GAA) charge plasma nanowire field-effect transistor with the help of the negative-capacitance technique

A gate-all-around charge plasma nanowire field-effect transistor (GAA CP NW FET) device using the negative-capacitance technique is introduced, termed the GAA CP NW negative-capacitance (NC) FET. In the face of bottleneck issues in nanoscale devices such as rising power dissipation, new techniques must be introduced into FET structures to overcome their major limitations. Negative capacitance is an efficient effect that can be incorporated into a device to enhance its performance for low-power applications and help to reduce the operating voltage. The Landau–Khalatnikov equation can be applied in such cases to obtain the effective bias. To determine the effects of negative capacitance, lead zirconate titanate (PZT) ferroelectric material, a ceramic material with perovskite properties, is adopted as a gate insulator. This approach diminishes the supply voltage and reduces the power dissipation in the device. Excluding their polarization properties, ferroelectric materials are similar to dielectric materials, and PZT offers abundant polarization with improved reliability and a higher dielectric capacitance. Without proper tuning of the thickness of the PZT material, hysteresis behavior mat occur. Hence, the thickness of the PZT material (t_FE) is an essential parameter to optimize the device performance and achieve a reduced threshold voltage for the GAA CP NW NC-FET device proposed herein. Furthermore, varying the thickness of the PZT ferroelectric material can also enhance the performance. When using the highest values of t_FE, improved outcomes with an analogously lower operating voltage are observed. The effects of varying t_FE on the performance characteristics of the device including the drain current, transconductance, polarized charge, etc. are also interpreted herein.

     

An analytic drain current model for long‐channel undoped gate stack surrounding‐gate MOSFETs including interface fixed charges

On the basis of the exact solution of Poisson's equation and Pao–Sah double integral for long‐channel bulk MOSFETs, a continuous and analytic drain current model for the undoped gate stack (GS) surrounding‐gate (SRG) metal–oxide–semiconductor field‐effect transistor (MOSFET) including positive or negative interface fixed charges near the drain junction is presented. Considering the effect of the interface fixed charges on the flat‐band voltage and the electron mobility, the model, which is expressed with the surface and body center potentials evaluated at the source and drain ends, describes the drain current from linear region to saturation region through a single continuous expression. It is found that the surface and body center potentials are increased/decreased in the case of positive/negative interface fixed charges, respectively, and the positive/negative interface fixed charges can decrease/increase the drain current. The model agrees well with the 3D numerical simulations and can be efficiently used to explore the effects of interface fixed charges on the drain current of the gate stack surrounding‐gate MOSFETs of the charge‐trapped memory device. Copyright © 2013 John Wiley & Sons, Ltd.     

3D Monte Carlo simulation of current trends and performance in scaled trigate MOSFET

Silicon nanowires with multiple-gates provide better source drain isolation and are thought to be the most promising candidate to replace bulk Si MOSFETs as we downscale deep into the nanometer regime. In this study we utilize a 3D full-band particle Monte Carlo (MOCA3D) simulator to investigate the performance and current trends of fully-depleted Trigate MOSFETs with different cross-sections. Results indicate that as we reduce the cross-section, the increased coupling between the top and lateral gates reduces the channel potential in different axes. In addition, device current normalized with respect to the Trigate perimeter alleviates as we scale the cross-section.     

Performance analysis and enhancement of 10-nm GAA CNTFET-based circuits in the presence of CNT-metal contact resistance

The gate-all-around (GAA) CNTFET is one of the most efficient types of CNTFETs which provides the conditions for scaling the technology to 10 nm and beyond, due to the extraordinary features of carbon nanotubes and the superior gate control through a high-k insulator over the CNT channel. However, the high CNT-metal contact resistance at the source/drain terminals can significantly degrade the device and circuit performance in CNTFET technology compared to what we have expected. In this study, first a comprehensive comparative assessment of performance and robustness of the gate-all-around CNTFET- and FinFET-based devices and circuits is performed. In the GAA CNTFET-based circuits the contact resistance can be defined as a series resistor at each contacted node of transistors. In addition, an effective circuit-level solution for improving the performance of GAA CNTFET-based circuits in the presence of contact resistance is proposed. In this approach, the contact lengths of the devices located on the critical path are increased to an effective value to reduce the contact resistance considerably and the other contact lengths remain minimum-sized. The results demonstrate that applying this solution significantly improves the speed, energy consumption and energy-delay product of GAA CNTFET-based circuits.     

Analytical subthreshold current and subthreshold swing models of short-channel dual-metal-gate (DMG) fully-depleted recessed-source/drain (Re-S/D) SOI MOSFETs

In this paper, analytical subthreshold current and subthreshold swing models are derived for the short-channel dual-metal-gate (DMG) fully-depleted (FD) recessed-source/ drain (Re-S/D) SOI MOSFETs considering that diffusion is the dominant current flow mechanism in subthreshold regime of the device operation. The two-dimensional (2D) channel potential is derived in terms of back surface potential and other device parameters. The so called virtual cathode potential in term of the minimum of back surface potential is also derived from 2D channel potential. The virtual cathode potential based subthreshold current and surface potential based subthreshold swing model results are extensively analyzed for various device parameters like the oxide and silicon thicknesses, thickness of source/drain extension in the BOX, control to screen gate length ratio and channel length. The numerical simulation results obtained from ATLAS \(^{\text{ TM }}\) , a 2D numerical device simulator from SILVACO Inc have been used as a tool to verify the model results.     

The Impact of Drift Implant and Layout Parameters on ESD Robustness for On-Chip ESD Protection Devices in 40-V CMOS Technology

The dependences of drift implant and layout parameters on electrostatic discharge (ESD) robustness in a 40-V CMOS process have been investigated in silicon chips. From the experimental results, the high-voltage (HV) MOSFETs without drift implant in the drain region have better transmission line pulsing (TLP)-measured secondary breakdown current (It2) and ESD robustness than those with drift implant in the drain region. Furthermore, the It2 and ESD level of HV MOSFETs can be increased as the layout spacing from the drain diffusion to polygate is increased. It was also demonstrated that a specific test structure of HV n-type silicon-controlled rectifier (HVNSCR) embedded into HV NMOS without N-drift implant in the drain region has the excellent TLP-measured It2 and ESD robustness. Moreover, due to the different current distributions in HV NMOS and HVNSCR, the dependences of the TLP-measured It2 and human-body-model ESD levels on the spacing from the drain diffusion to polygate are different.     

Collapse of MOSFET drain current after soft breakdown

Gate-oxide soft breakdown (SB) can have a severe impact on MOSFET performance even when not producing any large increase of the gate leakage current. The SB effect on the MOSFET characteristics strongly depends on the channel width W: drain saturation current and MOSFET transconductance dramatically drop in transistors with small W after SB. As W increases, the SB effect on the drain current fades. The drain saturation current and transconductance collapse is due to the formation of an oxide defective region around the SB spot, whose area is much larger than the SB conductive path. Similar degradation can be observed even in heavy ion irradiated MOSFETs where localized damaged oxide regions are generated by the impinging ions without producing any increase of gate leakage current.     

Study of fluctuations in advanced MOSFETs using a 3D finite element parallel simulator

Two important new sources of fluctuations in nanoscaled MOSFETs are the polysilicon gates and the introduction of high-κ gate dielectrics. Using a 3D parallel drift-diffusion device simulator, we study the influence of the polycrystal grains in polysilicon and in the high-κ dielectric on the device threshold for MOSFETs with gate lengths of 80 and 25 nm. We model the surface potential pinning at the grain boundaries in polysilicon through the inclusion of an interfacial charge between the grains. The grains in the high-κ gate dielectric are distinguished by different dielectric constants. We have found that the largest impact of the polysilicon grain boundary in the 80 nm gate length MOSFET occurs when it is positioned perpendicular to the current flow. At low drain voltage the maximum impact occurs when the grain boundary is close to the middle of the gate. At high drain voltage the impact is stronger when the boundary is moved toward the source end of the channel. Similar behaviour is observed in the 25 nm gate length MOSFET.     

An Improved Energy Transport Model Suitable for Simulation of Partially Depleted SOI MOSFETs

When applied to partially depleted SOI MOSFETs, the energy transport model predicts anomalous output characteristics. The effect that the drain current reaches a maximum and then decreases is peculiar to the energy transport model. It is not present in drift-diffusion simulations and its occurrence in measurements is questionable. The effect is due to an overestimation of the diffusion of channel hot carriers into the floating body. A modified energy transport model is proposed which describes hot carrier diffusion more realisticly and allows for proper simulation of SOI MOSFETs.     

Analysis of soft breakdown failure with ESD on output buffernMOSFETs and its improvement

The leakage increase of the off-state MOSFETs after an ESD event has been studied for output transistors with the thin gate oxide and LDD structures. Leakage increase called “soft breakdown” has been found at relatively low ESD testing voltages (200-300 V). This soft breakdown is caused by the creation of interface traps due to the snap-back stressing during the ESD event. The creation of interface traps has enhanced the interface trap to band tunneling current at the drain side of the MOSFETs. The improvement of the ESD threshold has also been proposed with an additional arsenic implantation into the n^$ region. It has been confirmed that the arsenic implantation improved the HBM ESD threshold to more than 2000 V     

Study of RF Linearity in sub-50 nm MOSFETs Using Simulations

We investigate the linearity performance of dual-gate and fully-depleted silicon-on-insulator MOSFETs through use of 2D computer simulations, which take into account quantum mechanical considerations and non-equilibrium transport effects. We show that DG MOSFET is superior not only in terms of g _m /I _d characteristics, central to analog performance, but also in terms of linearity performance, by up to 5 dBm, in most operating conditions. Linearity figures of devices considered in this work range from ?10 to ?20 dBm, which answer the needs of mobile communication standards currently in use. We also observe that, when properly scaled, bulk MOSFETs display competitive analog performance and have third-order intercept figures very similar to SOI device. We can identify, through simulation experiments, that quantum mechanical effects have positive impact on linearity, while non-equilibrium conditions lower linearity performance. With increasing drain bias, we find that linearity saturates at a moderately low voltage (～1 V) in all devices.     

Superior hot carrier reliability of single halo (SH) silicon-on-insulator (SOI) nMOSFET in analog applications

In this paper, for the first time, we report a study on the hot carrier reliability performance of single halo (SH) thin film silicon-on-insulator (SOI) nMOSFETs for analog and mixed-signal applications. The SH structure has a high pocket impurity concentration near the source end of the channel and low impurity concentration in the rest of the channel. Besides excellent dc output characteristics and experimental characterization results on these devices show better V/sub th/-L roll-off, low DIBL, higher breakdown voltages, and kink-free operation. Further SH SOI MOSFETs have been shown to exhibit reduced parasitic bipolar junction transistor effect in comparison to the homogeneously doped channel (conventional) SOI MOSFETs. Small-signal characterization on these devices shows higher ac transconductance, higher output resistance, and better dynamic intrinsic gain (g/sub m/R/sub o/) in comparison with the conventional homogeneously doped SOI MOSFETs. Also, the low drain junction capacitance as a result of low impurity concentration near the drain region is beneficial for improved circuit performance. The experimental results show that SH SOI MOSFETs exhibit a lower hot carrier degradation in small-signal transconductance and dynamic output resistance in comparison with conventional homogeneously doped SOI MOSFETs. From 2-D device simulations, the lower hot carrier degradation mechanism in SH SOI MOSFETs is analyzed and compared with the conventional SOI MOSFETs.     

Drain current model of double‐gate MOSFETs considering both electrons and holes

We present a rigorously derived current solution for undoped double‐gate (DG) MOSFETs with two carriers, which is based on surface potentials. The third‐order Newton–Raphson (NR) method is used to solve the surface‐potential equations resulting from the application of the boundary conditions to the general Poisson solution, with an initial guess very close to the true solution. The results demonstrate surface‐potential solutions for DG MOSFETs with 2–7 iterations to achieve an accuracy of 10⁻¹⁵. The drain current model for two carriers is presented as a benchmark to test the accuracy of one‐carrier current approximation. © 2014 Institute of Electrical Engineers of Japan. Published by John Wiley & Sons, Inc.     

A new parallel ZVS converter with less power switches and low current stress components

A new direct current (DC)/DC converter with parallel circuits is presented for medium voltage and power applications. There are five pulse‐width modulation circuits in the proposed converter to reduce current stress at low voltage side for high output current applications. These five circuits share the same power switches in order to reduce switch counts. To reduce the converter size, conduction loss, and voltage stress of power semiconductors, the series connections of power metal‐oxide‐semiconductor field‐effect transistor (MOSFET) with high switching frequency instead of insulated gate bipolar transistor (IGBT) with low switching frequency are adopted. Thus, the voltage stress of MOSFETs is clamped at half of input voltage. The switched capacitor circuit is adopted to balance input split capacitor voltages. Asymmetric pulse‐width modulation scheme is adopted to generate the necessary switching signals of MOSFETs and regulate output voltage. Based on the resonant behavior at the transition interval of power switches, all MOSFETs are turned on under zero voltage switching from 50% load to 100% load. The circuit configuration, operation principle, converter performance, and design example are discussed in detail. Finally, experimental verifications with a 1.92 kW prototype are provided to verify the performance of the proposed converter. Copyright © 2015 John Wiley & Sons, Ltd.     

Impact of Strain or Ge Content on the Threshold Voltage of Nanoscale Strained-Si/SiGe Bulk MOSFETs

The impact of strain on the threshold voltage of nanoscale strained-Si/SiGe MOSFETs is studied by developing a compact analytical model. Our model includes the effects of strain (Ge mole fraction in SiGe substrate), short-channel length, source/drain junction depths, substrate (body) doping, strained silicon thin-film thickness, gate work function, and other device parameters. The model correctly predicts a decrease in threshold voltage with increasing strain in the silicon thin film, i.e., with increasing Ge concentration in SiGe substrate. The accuracy of the results obtained using our analytical model is verified using two-dimensional device simulations.     

Computational study of double-gate graphene nano-ribbon transistors

The ballistic performance of graphene nanoribbon (GNR) MOSFETs with different width of armchair GNRs is examined using a real-space quantum simulator based on the Non-equilibrium Green’s Function (NEGF) approach, self-consistently coupled to a 3D Poisson’s equation for electrostatics. GNR MOSFETs show promising device performance, in terms of low subthreshold swing and small drain-induced-barrier-lowing due to their excellent electrostatics and gate control (single monolayer). However, the quantum tunneling effects play an import role in the GNR device performance degradation for wider width GNR MOSFETs due to their reduced bandgap. At 2.2 nm width, the OFF current performance is completely dominated by tunneling currents, making the OFF-state of the device difficult to control.     

应用于1-MHz Boost PFC变换器的自适应连续电流源驱动

针对高频功率因数校正(power factor correction,PFC)变换器,提出自适应电流源驱动电路(current source driver,CSD)。由于PFC变换器的占空比在一个输入工频周期内不断变化,半桥结构CSD驱动拓扑很难应用于PFC电路中。为了解决这个问题,提出全桥结构CSD电路并运用到PFCBoost变换器中。该CSD电路不仅可以有效减少高频开关损耗,而且驱动电流会随着主功率MOSFET开关电流的自适应调整。详细给出电路工作原理、损耗分析和设计优化方法,并进行实验验证。     

An analytical model of threshold voltage for short-channel double-material-gate (DMG) strained-Si (s-Si) on Silicon-Germanium-on-Insulator (SGOI) MOSFETs

In this paper, an analytical short-channel threshold voltage model is presented for double-material-gate (DMG) strained-Si (s-Si) on Silicon-Germanium-on-Insulator (SGOI) MOSFETs. The threshold voltage model is based on the “virtual cathode” concept which is determined by the two-dimensional (2D) channel potential of the device. The channel potential has been determined by solving 2D Poisson’s equation with suitable boundary conditions in both the strained-Si layer and relaxed Si_1?x Ge _x layer. The effects of various device parameters like Ge mole fraction, Si film thickness, SiGe thickness and gate-length ratio have been considered on threshold voltage. Further, the drain induced barrier lowering (DIBL) has also been estimated. The validity of the present 2D analytical model is verified by using ATLAS?, a 2D device simulator from Silvaco.