An adaptive PAM-4 5-Gb/s backplane transceiver in 0.25-/spl mu/m CMOS

This paper describes a backplane transceiver, which uses pulse amplitude modulated four-level (PAM-4) signaling and continuously adaptive transmit-based equalization to move 2.5-GBd/s symbols totalling 5 Gb/s across typical FR-4 backplanes for total distances of up to 50 inches through two sets of backplane connectors. The 17-mm/sup 2/ device is implemented in a 0.25-/spl mu/m CMOS process, operates off of 2.5- and 3.3-V supply voltages, and consumes 1 W.     

Low-power fully integrated 10-Gb/s SONET/SDH transceiver in 0.13-/spl mu/m CMOS

Here, we present a low-power fully integrated 10-Gb/s transceiver in 0.13-/spl mu/m CMOS. This transceiver comprises full transmit and receive functions, including 1:16 multiplex and demultiplex functions, high-sensitivity limiting amplifier, on-chip 10-GHz clock synthesizer, clock-data recovery, 10-GHz data and clock drivers, and an SFI-4 compliant 16-bit LVDS interface. The transceiver exceeds all SONET/SDH (OC-192/STM-64) jitter requirements with significant margin: receiver high-frequency jitter tolerance exceeds 0.3 UI/sub pp/ and transmitter jitter generation is 30 mUI/sub pp/. All functionality and specifications (core and I/O) are achieved with power dissipation of less than 1 W.     

An analog GFSK modulator in 0.35-/spl mu/m CMOS

An analog Gaussian frequency shift keying (GFSK) modulator designed in 0.35-/spl mu/m CMOS consumes 600 /spl mu/A from a 3-V supply and realizes an analog implementation of the FM differential equation. The modulator operates at baseband and is intended for use in a direct-conversion Bluetooth transmitter. It achieves a frequency deviation of 160 kHz with better than /spl plusmn/3% accuracy. The modulator implements an amplitude control loop to achieve a well-defined output swing. The total output harmonic distortion is less than 1%.     

A 2-Gb/s 0.5-/spl mu/m CMOS parallel optical transceiver with fast power-on capability

This paper describes an optical transceiver designed for power-efficient connections within high-speed digital systems, specifically for board- and backplane-level interconnections. A 2-Gb/s, four-channel, dc-coupled differential optical transceiver was fabricated in a 0.5-/spl mu/m complementary metal-oxide-semiconductor (CMOS) silicon-on-sapphire (SoS) process and incorporates fast individual-channel power-down and power-on functions. A dynamic sleep transistor technique is used to turn off transceiver circuits and optical devices during power-down. Differential signaling (using two optical channels per signal) enables self-thresholding and allows the transceiver to quickly return from power-down to normal operation. A free-space optical link system was built to evaluate transceiver performance. Experimental results show power-down and power-on transition times to be within a few nanoseconds. Crosstalk measurements show that these transitions do not significantly impact signal integrity of adjacent active channels.     

A 0.13-/spl mu/m CMOS 5-Gb/s 10-m 28AWG cable transceiver with no-feedback-loop continuous-time post-equalizer

The frequency-dependent attenuation of the transmission lines between chips and printed circuit boards, for example, is an obstacle to improving the performance of a system enhanced with LSI technology scaling. This is because large frequency-dependent attenuation results in poor eye-opening performance and a high bit-error rate in data transmission. This paper presents a 5-Gb/s 10-m 28AWG cable transceiver fabricated by using 0.13-/spl mu/m CMOS technology. In this transceiver, a continuous-time post-equalizer, with recently developed no-feedback-loop high-speed analog amplifiers, can handle up to 9dB of frequency-dependent attenuation in cables and also achieve an 18-dB improvement in the attenuation (27dB total improvement) by using pre- and post-equalization techniques in combination.     

A 0.35-/spl mu/m CMOS 2-GHz VCO in wafer-level package

This letter presents a complementary metal oxide semiconductor (CMOS) voltage-controlled oscillator (VCO) with a high-Q inductor in a wafer-level package for the LC-resonator. The on-chip inductor is implemented using the redistribution metal layer of the wafer-level package (WLP), and therefore it is called a WLP inductor. Using the thick passivation and copper metallization, the WLP inductor has high quality-factor (Q-factor). A 2-nH inductor exhibits a Q-factor of 8 at 2 GHz. The center frequency of the VCO is 2.16 GHz with a tuning range of 385 MHz (18%). The minimum phase noise is measured to be -120.2 dBc/Hz at an offset frequency of 600 kHz. The dc power consumed by the VCO-core is 1.87 mW with a supply voltage of 1.7 V and a current of 1.1 mA. The output power with a 50-/spl Omega/ load is -12.5/spl plusmn/1.3 dBm throughout the whole tuning range. From the best of our knowledge, compared with recently published 2-GHz-band 0.35 /spl mu/m CMOS VCOs in the literature, the VCO in this work shows the lowest power consumption and the best figure-of-merit.     

A dual-mode 802.11b/bluetooth radio in 0.35-/spl mu/m CMOS

A fully integrated dual-mode CMOS transceiver tuned to 2.4 GHz consumes 65 mA in receive mode and 78 mA in transmit mode from a 3-V supply. The radio includes all the receive and transmit building blocks, such as frequency synthesizer, voltage-controlled oscillator (VCO), and power amplifier, and is intended for use in 802.11b and Bluetooth applications. The Bluetooth receiver uses a low-IF architecture for higher level of integration and lower power consumption, while the 802.11b receiver is direct conversion. The receiver achieves a typical sensitivity of -88 dBm at 11 Mb/s for 802.11b, and -83 dBm for Bluetooth mode. The receiver minimum IIP3 is -8 dBm. Both transmitters use a direct-conversion architecture, and deliver a nominal output power of 0 dBm, with a power range of 20 dB in 2-dB steps.     

A 3-V, 0.35-/spl mu/m CMOS Bluetooth receiver IC

A fully integrated CMOS low-IF Bluetooth receiver is presented. The receiver consists of a radio frequency (RF) front end, a phase-locked loop (PLL), an active complex filter, a Gaussian frequency shift keying (GFSK) demodulator, and a frequency offset cancellation circuit. The highlights of the receiver include a low-power active complex filter with a nonconventional tuning scheme and a high-performance mixed-mode GFSK demodulator. The chip was fabricated on a 6.25-mm/sup 2/ die using TSMC 0.35-/spl mu/m standard CMOS process. -82 dBm sensitivity at 1e-3 bit error rate, -10 dBm IIP3, and 15 dB noise figure were achieved in the measurements. The receiver active current is about 65 mA from a 3-V power supply.     

A 40-Gb/s clock and data recovery circuit in 0.18-/spl mu/m CMOS technology

A phase-locked clock and data recovery circuit incorporates a multiphase LC oscillator and a quarter-rate bang-bang phase detector. The oscillator is based on differential excitation of a closed-loop transmission line at evenly spaced points, providing half-quadrature phases. The phase detector employs eight flip-flops to sample the input every 12.5 ps, detecting data transitions while retiming and demultiplexing the data into four 10-Gb/s outputs. Fabricated in 0.18-/spl mu/m CMOS technology, the circuit produces a clock jitter of 0.9 ps/sub rms/ and 9.67 ps/sub pp/ with a PRBS of 2/sup 31/-1 while consuming 144 mW from a 2-V supply.     

10-Gb/s limiting amplifier and laser/modulator driver in 0.18-/spl mu/m CMOS technology

A limiting amplifier incorporates active feedback, inductive peaking, and negative Miller capacitance to achieve a voltage gain of 50 dB, a bandwidth of 9.4 GHz, and a sensitivity of 4.6 mV/sub pp/ for a bit-error rate of 10/sup -12/ while consuming 150 mW. A driver employs T-coil peaking and negative impedance conversion to achieve operation at 10 Gb/s while delivering a current of 100 mA to 25-/spl Omega/ lasers or a voltage swing of 2 V/sub pp/ to 50-/spl Omega/ modulators with a power dissipation of 675 mW. Fabricated in 0.18-/spl mu/m CMOS technology, both prototypes operate with a 1.8-V supply.     

Ultra low power 2.4-GHz 0.35-/spl mu/m CMOS dual-modulus prescaler design

This letter presents the design and implementation of a dual-modulus (64/65) prescaler based upon the phase-switching technique. Low power consumption is achieved by using one dynamic flip-flop in the full-speed divide-by-four circuit and no power-hungry synchronizing circuits to tackle the glitch problem. The proposed design is fabricated using 0.35-/spl mu/m standard CMOS process and is measured to operate from 2.08-2.66GHz with power dissipation of less than 1mW.     

A 10-Gb/s CDR/DEMUX with LC delay line VCO in 0.18-/spl mu/m CMOS

A monolithic 10-Gb/s clock/data recovery and 1:2 demultiplexer are implemented in 0.18-/spl mu/m CMOS. The quadrature LC delay line oscillator has a tuning range of 125 MHz and a 60-MHz/V sensitivity to power supply pulling. The circuit meets SONET OC-192 jitter specifications with a measured jitter of 8 ps p-p when performing error-free recovery of PRBS 2/sup 31/-1 data. Clock and data recovery (CDR) is achieved at 10 Gb/s, demonstrating the feasibility of a half-rate early/late PD (with tri-state) based CDR on 0.18-/spl mu/m CMOS. The 1.9/spl times/1.5 mm/sup 2/ IC (not including output buffers) consumes 285 mW from a 1.8-V supply.     

A 10.7-MHz sixth-order SC ladder filter in 0.35-/spl mu/m CMOS technology

A sixth-order 10.7-MHz bandpass switched-capacitor filter based on a double terminated ladder filter is presented. The filter uses a multipath operational transconductance amplifier (OTA) that presents both better accuracy and higher slew rate than previously reported Class-A OTA topologies. Design techniques based on charge cancellation and slower clocks are used to reduce the overall capacitance from 782 down to 219 unity capacitors. The filter's center frequency and bandwidth are 10.7 MHz and 400 kHz, respectively, and a passband ripple of 1 dB in the entire passband. The quality factor of the resonators used as filter terminations is around 32. The measured (filter + buffer) third-intermodulation (IM3) distortion is less than -40 dB for a two-tone input signal of +3-dBm power level each. The signal-to-noise ratio is roughly 58 dB while the IM3 is -45 dB; the power consumption for the standalone filter is 42 mW. The chip was fabricated in a 0.35-/spl mu/m CMOS process; filter's area is 0.84 mm/sup 2/.     

Dual-modulus 127/128 FOM enhanced prescaler design in 0.35-/spl mu/m CMOS technology

The dual-modulus prescaler is a critical block in CMOS systems like high-speed frequency synthesizers. However, the design of high-moduli, high-speed, and low-power dual-modulus prescalers remains a challenge. To face the challenge, this paper introduces the idea of using transmission gates and pseudo-PMOS logic to realize the dual-modulus prescaler. The topology of the prescaler proposed is different from prior designs primarily in two ways: 1) it uses transmission gates in the critical path and 2) the D flip-flops (DFFs) used in the synchronous counter comprise pseudo-PMOS inverters and ratioed latches. A pseudo-PMOS logic-based DFF is introduced and used in the proposed prescaler design. Based on the proposed topology, a dual-modulus divide-by-127/128 prescaler is implemented in 0.35-/spl mu/m CMOS technology. It consumes 4.8 mW from a 3-V supply. The measured phase noise is -143.4 dBc/Hz at 600 kHz. The silicon area required is only 0.06 mm/sup 2/. There are no flip flops or logic gates in the critical path. This topology is suitable for high-speed and high-moduli prescaler designs. It reduces: 1) design complexity; 2) power consumption; and 3) input loading. Measurement results are provided. An improvement in the figure of merit is shown.     

A 0.3-μm CMOS 8-Gb/s 4-PAM serial link transceiver

An 8-Gb/s 0.3-μm CMOS transceiver uses multilevel signaling (4-PAM) and transmit preshaping in combination with receive equalization to reduce intersymbol interference due to channel low-pass effects. High on-chip frequencies are avoided by multiplexing and demultiplexing the data directly at the pads. Timing recovery takes advantage of a novel frequency acquisition scheme and a linear phase-locked loop that achieves a loop bandwidth of 35 MHz, phase margin of 50°, and capture range of 20 MHz without a frequency acquisition aid. The transmitted 8 Gb/s data are successfully detected by the receiver after a 10-m coaxial cable. The 2×2 mm² chip consumes 1.1 W at 8 Gb/s with a 3-V supply     

A 10-Gb/s receiver with series equalizer and on-chip ISI monitor in 0.11-/spl mu/m CMOS

A 10-Gb/s receiver is presented that consists of an equalizer, an intersymbol interference (ISI) monitor, and a clock and data recovery (CDR) unit. The equalizer uses the Cherry-Hooper topology to achieve high-bandwidth with small area and low power consumption, without using on-chip inductors. The ISI monitor measures the channel response including the wire and the equalizer on the fly by calculating the correlation between the error in the input signal and the past decision data. A switched capacitor correlator enables a compact and low power implementation of the ISI monitor. The receiver test chip was fabricated by using a standard 0.11-/spl mu/m CMOS technology. The receiver active area is 0.8 mm/sup 2/ and it consumes 133 mW with a 1.2-V power supply. The equalizer compensates for high-frequency losses ranging from 0 dB to 20 dB with a bit error rate of less than 10/sup -12/. The areas and power consumptions are 47 /spl mu/m /spl times/ 85 /spl mu/m and 13.2 mW for the equalizer, and 145 /spl mu/m /spl times/ 80 /spl mu/m and 10 mW for the ISI monitor.     

A divide-by-16.5 circuit for 10-gb ethernet transceiver in 0.13-/spl mu/m CMOS

A divide-by-16.5 frequency divider, providing read- and write-clocks for an elastic buffer or a gearbox between 10.3125-Gb/s and quad 3.125-Gb/s transceivers in 10-G Ethernet application, is presented. The high-speed and noninteger division is designed by cascading high-speed divide-by-3 followed by divide-by-5.5 which uses double-edge-triggered flip-flops. The divide-by-3 circuit receives and generates 5.15625-GHz and 1.71875-GHz differential clocks with a 50% duty cycle, respectively. Based on current-mode logics (CMLs), the proposed divide-by-16.5 scheme is implemented in a 0.13-/spl mu/m CMOS technology to achieve over 5-GHz operation while consuming 18 mW from a 1.2-V supply.     

A 2.4-GHz dual-mode 0.18-/spl mu/m CMOS transceiver for Bluetooth and 802.11b

High-level integration of the Bluetooth and 802.11b WLAN radio systems in the 2.4-GHz ISM band is demonstrated in scaled CMOS. A dual-mode RF transceiver IC implements all transmit and receive functions including the low-noise amplifier (LNA), 0-dBm power amplifier, up/down mixers, synthesizers, channel filtering, and limiting/automatic gain control for both standards in a single chip without doubling the required silicon area to reduce the combined system cost. This is achieved by sharing the frequency up/down conversion circuits in the RF section and performing the required baseband channel filtering and gain functions with just one set of reconfigurable channel filter and amplifier for both modes. A chip implemented in 0.18-/spl mu/m CMOS occupies 4/spl times/4 mm/sup 2/ including pad and consumes 60 and 40 mA for RX and TX modes, respectively. The dual-mode receiver exhibits -80-dBm sensitivity at 0.1% BER in Bluetooth mode and at 12-dB SNR in WLAN mode.     

Highly efficient xDSL line drivers in 0.35-/spl mu/m CMOS using a self-oscillating power amplifier

The design of two highly efficient line drivers in a digital 0.35-/spl mu/m, 3.3-V technology are presented. The self-oscillating power amplifier (SOPA) architecture has been developed in order to obtain a high efficiency for systems with a high crest factor like discrete multitone modulated xDSL modems. The SOPA architecture is an unclocked switching-type line driver. By using self-oscillation and noise-shaping, a high signal linearity can be obtained for low over-switching ratios. By coupling two SOPA line drivers with a signal transformer, the two limit cycle oscillations are pulled toward synchronization. This gives an important mean switching frequency suppression toward the line. The need for an extra filter dealing with the mean switching frequency is in that way heavily relaxed. A zeroth-order SOPA and a third-order SOPA are prototyped. The zeroth-order line driver meets ADSL-Lite specifications with a missing tone power ratio (MTPR) of 41 dB for an 800-kHz bandwidth. The maximum efficiency is 41%. The third-order version meets ADSL and VDSL specifications with an MTPR of 56 dB and an 8.6-MHz bandwidth. An efficiency of 47% was measured for an ADSL signal with a crest factor >5.     

A CMOS multichannel 10-Gb/s transceiver

We describe a CMOS multichannel transceiver that transmits and receives 10 Gb/s per channel over balanced copper media. The transceiver consists of two identical 10-Gb/s modules. Each module operates off a single 1.2-V supply and has a single 5-GHz phase-locked loop to supply a reference clock to two transmitter (Tx) channels and two receiver (Rx) channels. To track the input-signal phase, the Rx channel has a clock recovery unit (CRU), which uses a phase-interpolator-based timing generator and digital loop filter. The CRU can adjust the recovered clock phase with a resolution of 1.56 ps. Two sets of two-channel transceiver units were fabricated in 0.11-/spl mu/m CMOS on a single test chip. The transceiver unit size was 1.6 mm /spl times/ 2.6 mm. The Rx sensitivity was 120-mVp-p differential with a 70-ps phase margin for a common-mode voltage ranging from 0.6 to 1.0 V. The evaluated jitter tolerance curve met the OC-192 specification.