Chip-scale packaging of power devices and its application inintegrated power electronics modules

A power electronics packaging technology utilizing chip-scale packaged (CSP) power devices to build three-dimensional (3-D) integrated power electronics modules (IPEMs) is presented in this paper. The chip-scale packaging structure, termed die dimensional ball grid array (D²BGA), eliminates wire bonds by using stacked solder joints to interconnect power chips. D²BGA package consists of a power chip, inner solder caps, high-lead solder balls, and molding resin. It has the same lateral dimensions as the starting power chip, which makes high-density packaging and module miniaturization possible. This package enables the power chip to combine excellent thermal transfer, high current handling capability, improved electrical characteristics, and ultralow profile packaging. Electrical tests show that the V_CE(sat) and on-resistance of the D²BGA high speed insulated-gate-bipolar transistors (IGBTs) are improved by 20% and 30% respectively by eliminating the device wirebonds and other external interconnections, such as the leadframe. In this paper, we present the design, reliability, and processing issues of D²BGA package, and the implementation of these chip-scale packaged power devices in building 30 kW half-bridge power converter modules. The electrical and reliability test results of the packaged devices and the power modules are reported     

光电器件激光焊接封装的建模与分析

介绍了激光焊原理和有限元分析过程,建立了激光二极管封装组件的3-D有限元模型,利用Ansys有限元分析程序对激光二极管在不同焊接条件下激光焊封装的温度场进行了计算模拟,仿真分析了激光锤作用下激光二极管封装尾纤的焊后偏移（PWS）。在增加功率和脉冲时间的条件下,激光锤引起的焊后偏移量也相应的增加,但是在校正量相同的情况下,增加脉冲时间比增加功率对材料的热应力影响区要大。高功率低脉冲的焊接参数是完成焊接封装的首选参数。     

An innovative technique for packaging power electronic buildingblocks using metal posts interconnected parallel plate structures

Power electronics building blocks (PEBBs) are envisioned as integrated power modules consisting of power semiconductor devices, power integrated circuits, sensors, and protection circuits for a wide range of power electronics applications, such as inverters for motor drives and converters for power processing equipment. At the Center for Power Electronics Systems, we developed a topology for a basic building block-a two-switch two-diode half-bridge converter in totem-pole configuration with built-in gate-driver and protection circuitry, fiber-optic receiver/transmitter interface, and soft-switching capability. Based on the topology, a series of prototype modules, with 600 V, 3.3 kW rating, were fabricated using an innovative packaging technique developed for the program-metal posts interconnected parallel plate structure (MPIPPS). This new packaging technique uses direct attachment of bulk copper, not wire-bonding of fine aluminum wires, for interconnecting power devices. Electrical performance data of the packaged devices show that an air-cooled 15 kW inverter, operating from 400 V dc bus with 20 kHz switching frequency can be constructed by integrating three prototype modules, which is almost double what could be achieved with commercially packaged devices of the same rating     

Wavelength-tunable laser module using low-temperature cofired ceramic substrates

We realized a prototype series of the 1550-nm band wavelength-tunable laser module. The edge-emitting Fabry-Perot diode laser operates in the short external cavity configuration and is tuned by a silicon surface micromachined Fabry-Peacuterot interferometer device. Low-temperature cofired ceramic (LTCC) substrate technology was used in the module packaging to enable the passive alignment of the photonic components. Low conductor resistance and dielectric loss, multilayer structures with fine-line capability, compatibility with hermetic sealing, and the ability to integrate passive electrical components (resistors, capacitors, and inductors) into the substrate make LTCC a useful technology for telecommunication applications. In addition, the fair match of the thermal expansion coefficient to optoelectronic chips reduces packaging-induced thermomechanical stresses. The precision three-dimensional (3-D) structures, such as cavities, holes, and channels manufactured in the ceramic parts, ease the packaging process via the passive assembly. The wavelength tuning range of the realized modules ranged from 8 to 19 nm and single-mode fiber-coupled output power was between 100 and 570 muW. The hybrid arrangement uses standard laser chips and, therefore, potentially provides a cost-effective and easily configurable solution for last-mile fiber optic communications     

三维（3—D）封装技术

3-D多芯片组件（MCM）是未来微电子封装的发展趋势。本文介绍了超大规模集成（VLSI）用的3-D封装技术的最新进展,详细报导了垂直互连技术,概括讨论了选择3-D叠层技术的一些关键问题,并对3-D封装和2-D封装及分立器件进行了对比。     

Three-dimensional flip-chip on flex packaging for power electronicsapplications

We have extended the concept of flip-chip technology, which is widely used in IC packaging, to the packaging of three-dimensional (3-D) integrated power electronics modules (IPEMs). We call this new approach flip-chip on flex IPEM (FCOF-IPEM), because the power devices are flip-chip bonded to a flexible substrate with control circuits. We have developed a novel triple-stacked solder bump metallurgy for improved and reliable device interconnections. In this multilayer structure, we have carefully selected packaging materials that distribute the thermo-mechanical stresses caused by mismatching coefficients of thermal expansion (CTEs) among silicon chips and substrates. We have demonstrated the feasibility of this packaging approach by constructing modules with two insulated gate bipolar transistors (IGBTs), two diodes, and a simple gate driver circuit. Fabricated FCOF-IPEMs have been successfully tested at power levels up to 10 kW. This paper presents the materials and reliability issues in the package design along with electrical, mechanical, and thermal test results for a packaged IPEM     

3-D Data Storage, Power Delivery, and RF/Optical Transceiver—Case Studies of 3-D Integration From System Design Perspectives

Three-dimensional (3-D) integration of systems by vertically stacking and interconnecting multiple materials, technologies, and functional components offers a wide range of benefits, including speed, bandwidth and density increase, power reduction, small form factor, packaging reduction, yield and reliability increase, flexible heterogeneous integration with multifunctionality, and overall cost reduction. A new spectrum of opportunities and challenges arises for integrated system designers, which warrants rethinking and innovations from system design perspectives. By selecting three representative cases, i.e., solid-state data storage, power delivery, and hybrid radio-frequency/optical transceiver for distributed sensor networks, this paper intends to exemplify the potentials of exploiting the benefits of 3-D integration technology from system perspectives.      

Three-Dimensional Packaging Technology for Stacked DRAM With 3-Gb/s Data Transfer

A 3-D packaging technology is developed for stacked dynamic random access memory (DRAM) with through-silicon vias (TSVs). Eight different dry etchers were evaluated for deep Si etching. Highly doped poly-Si TSVs were used for vertical traces inside silicon and interconnection between DRAM chips to realize a DRAM-compatible process. Through optimization of process conditions and layout design, a fast poly-Si filling has been obtained. The entire packaging was carried out at the wafer level by using smart chip connection with feedthrough interposer (FTI) technology. A new bump and wiring structure for the FTI has also been developed for fine-pitch and low-cost bonding. Normal operation during DRAM read/write was confirmed on a 512-Mb DRAM with TSVs, with an I/F chip as a memory controller. Simulation and measurement of the transfer function of the FTI wiring showed a 3-Gb/s/pin data transfer capability.     

A compact three-dimensional packaging technique usingsuper-fine-pitch coaxial connector arrays for on-board satelliteequipment

A compact three-dimensional (3-D) inter-module microwave packaging technique has been developed that drastically reduces the volume of on-board satellite equipment of phased-array beam control (PBC). A super-fine-pitch coaxial connector (SCC) array has been successfully implemented with this 3-D structure along with very flat, superior-performance ceramic MMIC packages and combiner packages. Two types of SCC have been developed-a lead-to-jack array and a plug-to-plug array-both of which have a 2-mm pin pitch. Through application of this 3-D packaging technique to S-band 61-beam 32-radiator PBC equipment, an ultra-small packaging unit was developed that houses a 32×64 interconnection in a 2600-cc chassis. This technique promises to make possible compact, light-weight on-board PBC equipment that is especially suitable for use in satellite transponders     

Trends of power semiconductor wafer level packaging

A review of recent advances in power wafer level electronic packaging is presented based on the development of power device integration. The paper covers in more detail how advances in both semiconductor content and power advanced wafer level package design and materials have co-enabled significant advances in power device capability during recent years. Extrapolating the same trends in representative areas for the remainder of the decade serves to highlight where further improvement in materials and techniques can drive continued enhancements in usability, efficiency, reliability and overall cost of power semiconductor solutions. Along with next generation wafer level power packaging development, the role of modeling is a key to assure successful package design. An overview of the power package modeling is presented. Challenges of wafer level power semiconductor packaging and modeling in both next generation design and assembly processes are presented and discussed.     

Heat dissipation assessment of through silicon via (TSV)-based 3D IC packaging for CMOS image sensing

The study aims at evaluation of the steady-state heat dissipation capability of a high-density through silicon via (TSV)-based three-dimensional (3D) IC packaging technology (briefly termed 3D TSV IC packaging) designed for CMOS image sensing under natural convection through finite element analysis (FEA) and thermal experiments. To enhance modeling and computational efficiency, an effective approach based on FEA incorporating a 3D unit-cell model is proposed for macroscopically and thermally simulating the heterogeneous TSV chips. The developed effective thermal conductivities are compared against those obtained from a rule-of-mixture technique. In addition, the proposed numerical models are validated by comparison with two experiments. Besides, the uncertainties in the input chip power from the specific power supply and in the measured chip junction temperature by the thermal test die are evaluated. Finally, a design guideline for improved thermal performance is provided through parametric thermal study.     

High-density 3-D packaging technology based on the sidewall interconnection method and its application for CCD micro-camera visual inspection system

High-density three-dimensional (3-D) packaging technology for a charge coupled device (CCD) micro-camera visual inspection system module has been developed by applying high-density interconnection stacked unit modules. The stacked unit modules have fine-pitch flip-chip interconnections within Cu-column-based solder bumps and high-aspect-ratio Cu sidewall footprints for vertical interconnections. Cu-column-based solder bump design and underfill encapsulation resin characteristics were optimized to reduce the strain in the bump so as to achieve fine-pitch flip-chip interconnection with high-reliability. High-aspect-ratio Cu sidewall footprints were realized by the Cu-filled stacked vias at the edge of the substrate. High-precision distribution of sidewall footprints was achieved by laminating the multiple stacked unit substrates simultaneously. The fabricated high-density 3-D packaging module has operated satisfactorily as the CCD imaging data transmission circuit. The technology was confirmed to be effective for incorporating many large scale integrated (LSI) devices of different sizes at far higher packaging density than it is possible to attain using conventional technology. This paper describes the high-density 3-D packaging technology which enables all of the CCD imaging data transmission circuit devices to be packaged into the restricted space of the CCD micro-camera visual inspection system interior.     

Thermal management of power electronics modules packaged by a stacked-plate technique

The research presented in this paper is part of a multidisciplinary research program of the Center for Power Electronics Systems at Virginia Tech. The program supported by the Office of Naval Research focuses on the development of innovative technologies for packaging power electronics building blocks. The primary objective of this research is to improve package performance and reliability through thermal management, i.e., reducing device temperatures for a given power level. The task of thermal management involves considering trade-offs in the electrical design, package layout and geometry, materials selection and processing, manufacturing feasibility, and production cost. Based on the electrical design of a simple building block, samples of packaged modules, rated at 600 V and 3.3 kW, were fabricated using a stacked-plate technique, termed metal posts interconnected parallel plate structure (MPIPPS). The MPIPPS technique allows the power devices to be interconnected between two direct-bond copper substrates via the use of metal posts. Thermal modeling results on the MPIPPS packaged modules indicate that the new packaging technique offers a superior thermal management means for packaging power electronics modules.     

A highly-compact packaging design for improving the thermal performance of multi-finger InGaP/GaAs collector-up HBTs

To satisfy the increasing demand for small power amplifiers in advanced cellular phones, we have investigated the thermal performance of multi-finger InGaP/GaAs collector-up HBTs with a heat-dissipation packaging configuration. The thermal interaction between collector fingers and the size effect on the maximum operation temperature within the transistor have been scrutinized. In addition, the thermal handling for a stable operation in the device has been optimized through the variation of finger pitches. The superior results show that the thickness of the heat-dissipation structure can be reduced by more than 35%, and the achieved thermal resistance can be effectively improved over 40%. Based on appropriate approaches from the 3-D numerical simulation for thickness-adjusting evaluation and the analytical analysis for finger-pitch optimization, a highly-compact packaging design is proposed for the miniaturization of collector-up HBTs in future mobile communication systems.     

大电流窄脉冲激光器驱动芯片设计

脉冲式半导体激光器的出光质量直接影响探测精度。针对激光探测系统小型化的需求,设计一款面积小、集成度高的激光器驱动芯片。该芯片使用新型3D堆叠式封装技术将栅极驱动管芯与功率场效应晶体管管芯集成,并在中间添加双面覆铜陶瓷基板实现两管芯互连。该封装形式既提高了芯片的散热能力,又增强了过流能力。首先对激光探测发射模块现状进行详细介绍,引出了激光器驱动芯片的设计思路与方法,并给出了具体的封装设计流程。对栅极驱动电路与版图进行设计,使用0.25 μm BCD工艺制造栅极驱动芯片。在完成激光器驱动芯片封装后,搭建外围电路进行测试,使该芯片驱动860 nm激光器,芯片供电电压为12 V时,输入电平为3.3 V、频率为10 kHz的PWM信号,芯片输出脉冲宽度为180 ns的窄脉冲,其上升、下降时间小于30 ns,峰值电流高达15 A,可以使激光器正常出光,满足探测需求。芯片具有超小面积,约为5 mm×5 mm,解决了传统激光器驱动电路采用多芯片模块造成探测系统内部空间拥挤的问题,为小型化提供新思路。     

3-D packaging methodologies for microsystems

Issues associated with the packaging of microsystems in plastic and three-dimensional (3-D) body styles are discussed. The integration of a microsystem incorporating a micromachined silicon membrane pump, into a 3-D plastic encapsulated vertical multichip module package (MCM-V) is described. Finite element techniques are used to analyze the encapsulation stress in the structure of the package. Cracks develop in the chip carrier due to thermomechanical stress. Based on the results of a finite element design study, the structures of the chip carriers are modified to reduce their risk of cracking. Alternative low stress 3-D packaging methodologies based on chip on board and plastic leadless chip carriers are discussed.     

The 3-D Computer

The 3-D Computer [1]–[4] is a unique implementation of a cellular array processor. We have developed two radically new technologies which enable massive numbers of communication channels both between silicon wafers and through them. A parallel processor (single instruction-multiple data stream cellular array processor) has been designed and built to demonstrate the potential of this technological approach. While the 3-D Computer which has been built and operated in a small scale implementation relative to the long-term aims of this technology, it is nevertheless an extremely powerful computer. The current feasibility demonstration 3-D Computer is a 32×32 array of processors partitioned over five wafers stacked one on top of another. The throughput of this current machine is >600 million operations per second (MOPS) with a 10 MHz clock, while the projected throughput of a full scale machine is >100 billion operations per second (BOPS), again with a 10 MHz clock. The extension of the level of circuit integration beyond that of VLSI and WSI, which is made possible by the 3-D technologies of wafer feedthroughs and microbridges, enable us to achieve these enormous throughputs in a very compact form and at very low power. The small size and low power attributes of the 3-D Computer result from the elimination of the chip level and board level packaging and the intraboard wiring required by conventional levels of circuit integration.     

The 3-D Computer

The 3-D Computer [1]–[4] is a unique implementation of a cellular array processor. We have developed two radically new technologies which enable massive numbers of communication channels both between silicon wafers and through them. A parallel processor (single instruction-multiple data stream cellular array processor) has been designed and built to demonstrate the potential of this technological approach. While the 3-D Computer which has been built and operated in a small scale implementation relative to the long-term aims of this technology, it is nevertheless an extremely powerful computer. The current feasibility demonstration 3-D Computer is a 32×32 array of processors partitioned over five wafers stacked one on top of another. The throughput of this current machine is >600 million operations per second (MOPS) with a 10 MHz clock, while the projected throughput of a full scale machine is >100 billion operations per second (BOPS), again with a 10 MHz clock. The extension of the level of circuit integration beyond that of VLSI and WSI, which is made possible by the 3-D technologies of wafer feedthroughs and microbridges, enable us to achieve these enormous throughputs in a very compact form and at very low power. The small size and low power attributes of the 3-D Computer result from the elimination of the chip level and board level packaging and the intraboard wiring required by conventional levels of circuit integration.     

后摩尔时代的封装技术

介绍了在高性能的互连和高速互连芯片(如微处理器)封装方面发挥其巨大优势的TSV互连和3D堆叠的三维封装技术。采用系统级封装(SiP)嵌入无源和有源元件的技术,有助于动态实现高度的3D-SiP尺寸缩减。将多层芯片嵌入在内核基板的腔体中;采用硅的后端工艺将无源元件集成到硅衬底上,与有源元件芯片、MEMS芯片一起形成一个混合集成的器件平台。在追求具有更高性能的未来器件的过程中,业界最为关注的是采用硅通孔(TSV)技术的3D封装、堆叠式封装以及类似在3D上具有优势的技术,并且正悄悄在技术和市场上取得实实在在的进步。随着这些创新技术在更高系统集成中的应用,为系统提供更多的附加功能和特性,推动封装技术进入后摩尔时代。