多芯片组件（MCM）技术

对日益广泛采用的多芯片组件（ＭＣＭ）技术的基本构成、基本类型、芯片安装／内连接、测试与诊断等作了较系统的介绍。     

多芯片组件（MCM）的可靠性

可靠性是目前阻碍多芯片组件技术推向市场的一大难题，文章简述了ＭＣＭ可靠性研究的范围、特点及研究方法和研究重点。     

多芯片组件（MCM）技术

概述了多芯片组件技术的发展,介绍了多芯片技术基本类型及组装方法、三维多芯片组件以及多芯片组件的发展和重点应用领域.     

多芯片组件（MCM）的封装技术

电子元器件（组件）的封装严重影响微电路的性能和可靠性,其成本约占IC器件的I／3,因此,封装的性能和成本对电子产品的竞争力影响很大,MCM封装是多芯片组件的重要组成部分,本文从构成MCM封装技术的材料选择,结构类型以及MCM封装的密封技术和冷却技术几个方面作一介绍。     

多芯片组件（MCM）测试方法的研究

本文论述多芯片组件(MCM)的测试问题。由于多芯片组件在技术上的特殊性,传统的IC、PCB测试方法已不能适应MCM的测试需求。本文分析了MCM测试中存在的问题,并且根据MCM测试的特殊要求,分析了几种测试方法。膜片(membrane)探针卡较适合于裸片的测试;衬底测试效果较理想的方法是探针测试及电子束测试;封装后的MCM测试可采用探针测试和边界扫描方法。     

多芯片组件（MCM）的封装技术

电子元器件的封装严重影响微电路的性能和可靠性,其成本约占ＩＣ器件的１／３,因此,封装的性能和成本对电子产品和竞争力影响很大。ＭＣＭ封装是多芯片组件的重要组成部分,本文从构成ＭＣＭ封装技术的材料选择、结构模型以及ＭＣＭ封装的密封技术和冷却技术几个方面进行详细介绍。     

浅谈多芯片组件（MCM）的可靠性技术

介绍了多芯片组件（MCM）可靠性的研究方法和关键技术，指出多芯片组件（MCM0可靠性研究应以失效物理评价方法为主。     

3D MCM组件产品热分析技术研究

三维多芯片组件(3D MCM-Three Dimension Multi-Chip Module)是近几年正在发展的一种电子封装技术。在3DMCM封装中,随着芯片封装密度的增加,对其热分析与热设计技术就显得越来越重要了。文章利用有限元方法,通过Ansys软件工具对某静态存储器组件(3DMCM模块)内部温度场进行了模拟仿真,并与实验数据进行了对比,获得了很好的分析效果,为3DMCM的可靠性设计提供了技术支持。     

基于MCM-D工艺的3D-MCM工艺技术研究

基于MCM-D薄膜工艺,开展了3D-MCM相关的无源元件内埋置、芯片减薄、芯片叠层组装、低弧度金丝键合、芯片凸点,以及板级叠层互连装配等工艺技术研究。通过埋置型基板、叠层芯片组装、板级叠层互连,实现了3D-MCM结构,制作出薄膜3D-MCM样品;探索出主要的工艺流程及关键工序控制方法,实现了薄膜3D-MCM封装。     

An Effective Multi-Chip BIST Scheme

This paper addresses the general problem of module level test ofassembled Multi-Chip Modules (MCMs) and specifically the performancetest of such modules. It presents a novel solution based-on built-in self-test (BIST). This solutionaugments the conventional single-chip BIST approach, which is used to produce individual good dies, to an effective multi-chip BIST solution. The multi-chip BIST puts the entire module in a self-test mode. The self-test mode not only provides effective detection of static and dynamic faults, but also identifies the failed elements, i.e., bad dies or substrate. The multi-chip self-test scheme is based on pseudo-random test generation and uses multi-signature evaluation. The hardware design ofmulti-chip and single-chip self-test blocks is combined under one common architecture called the Dual BIST Architecture. The paper introduces the Dual BIST Architecture and demonstrates a set of design configurations to implement it. The presented BIST solution provides a reliable static and dynamic test at the module as well as the bare die levels.     

Self-Timed Boundary-Scan Cells for Multi-Chip Module Test

This paper presents a self-timed scan-path architecture, to be used in a conventional synchronous environment, and with basic application in digital testing and interconnections checking in a Smart-Substrate MCM (T.A. García, A.J. Acosta, J.M. Mora, J. Ramos, and J.L. Huertas, Self-Timed Boundary-Scan Cells for Multi-Chip Module Test, Proceedings of IEEE VLSI Test Symposium, April 1998, pp. 92–97). With this approach, the potential advantages of self-timed asynchronous systems are explored for their practical use in a classical MCM testing application. Three different self-timed asynchronous boundary scan cells are proposed (Sense, Drive and Drive & Sense cells) that can be connected to form a self-timed scan-path. The main advantage is that no global test clock is needed, avoiding clock skew and synchronization faults in test mode, and hence, a more reliable test process is achieved. These cells have been designed and integrated in active substrates, building several boundary-scan configurations and being fully compatible with the ANSI/IEEE 1149.1 Standard. The experimental results, as well as their comparison with their synchronous counterparts, show the feasibility of the proposed self-timed approach for testing interconnections in a MCM.     

Multi-Chip Differential Space-Time Block Coding for DS-CDMA

In this letter, we propose a novel space-time coding scheme for fast time-variant direct-sequence code-division multiple access (DS-CDMA) channels. The proposed scheme employs multi-chip differential space-time block coding (MC-DSTBC) and robustness against fast fading is further improved by low-complexity decision-feedback differential detection (DF-DD). Both analytical and simulation results show in good agreement the excellent performance of the novel design in fast time-variant channels.     

多芯片封装技术及其应用

文章评述多芯片封装技术及目前的基本情况,这一技术在手机存储器的应用现状等。同时, 列举了当前主要的工艺特征与技术要点,从而说明多芯片封装的技术及其发展前景。     

多芯片SiC功率模块布局优化

传统的SiC模块常采用平面布局,各芯片的工作电路存在明显的不对称性,芯片间存在源极侧公共支路,支路上的耦合电感将导致严重的动态电流不均衡.首先对源极侧公共支路耦合电感对并联芯片间动态电流分布的影响进行了详细分析,建立了描述动态不均衡电流和源极侧公共支路耦合电感关系的解析模型,揭示了该电感对芯片动态均流的影响机理.随后,基于该模型提出了一种立体的多芯片并联圆周布局,该布局能够消除并联芯片间的电流耦合效应,并且提高了源极寄生电感的一致性.最后,仿真与实验结果表明,所提出的新型立体圆周布局下,并联芯片间的动态电流分布一致性显著提高.     

车载电子模块管脚处接触放电特性仿真分析

静电放电是车载电子模块失效的一个重要原因.该文总结了接触放电测试的要求,仿真分析了某车载电子模块PCB板管脚处的接触放电特性,得到的仿真结果对于PCB板静电放电抗扰度的设计和抑制措施的施加具有指导意义.     

COG类产品腐蚀模拟分析及解决方案

通过自制ITO模板模拟污染源,针对COG产品出现的腐蚀现象进行模拟,找到出现腐蚀的原因,并提出解决方案,以杜绝腐蚀的产生。