Design for Testability Techniques at the Behavioral and Register-Transfer Levels

Improving testability during the early stages of the design flow can have several benefits, including significantly improved fault coverage, reduced test hardware overheads, and reduced design iteration times. This paper presents an overview of high-level design methodologies that consider testability during the early (behavior and architecture) stages of the design flow, and their testability benefits. The topics reviewed include behavioral and RTL test synthesis approaches that generate easily testable implementations targeting ATPG (full and partial scan) and BIST methodologies, and techniques to use high-level information for ATPG.     

Redundancies and don't cares in sequential logic synthesis

The relationships between redundant logic and don't care conditions in combinational circuits are well known. Redundancies in a combinational circuit can be explicitly identified using test generation algorithms or implicitly eliminated by specifying don't cares for each gate in the combinational network and minimizing the gates, subject to the don't care conditions.In this article, we explore the relationships between redundant logic and don't care conditions in sequential circuits. Stuck-at faults in a sequential circuit may be testable in the combinational sense, but may be redundant because they do not alter the terminal behavior of a nonscan sequential machine. These sequential redundancies result in a faulty State Transition Graph (STG) that is equivalent to the STG of the true machine.We present a classification of redundant faults in sequential circuits composed of single or interacting finite state machines. For each of the different classes of redundancies, we define don't care sets which if optimally exploited will result in the implicit elimination of any such redundancies in a given circuit. We present systematic methods for the exploitation of sequential don't cares that correspond to sequences of vectors that never appear in cascaded or interacting sequential circuits. Using these don't care sets in an optimal sequential synthesis procedure of state minimization, state assignment, and combinational logic optimization results in fully testable lumped or interacting finite state machines. We present experimental results which indicate that medium-sized irredundant sequential circuits can be synthesized with no area overhead and within reasonable CPU times by exploiting these don't cares.     

A symbolic approach toward high-level variation-aware topology synthesis of Delta-Sigma modulators

This article presents a methodology for automated high-level variation-aware topology synthesis of ΔΣ (Delta-Sigma) modulators. The methodology targets an optimal high-level ΔΣ modulator topology in terms of statistical signal-to-noise ratio (SNR) variation. In the proposed methodology, a systematic symbolic formulation of statistical SNR variation is made so that variations of capacitors are directly translated to SNR variation. The symbolic formulation of statistical SNR variation is then taken as the cost function guiding the topology synthesis process. A ΔΣ modulator template topology, which compactly represents all possible modulator topologies, is used so that the solution space is complete. To facilitate the search for an optimal topology, a mixed-integer non-linearly constrained programming (MINLP) program is formulated. By solving the MINLP program, an optimal solution with least statistical SNR variation can be obtained. A few experiments have shown the solved optimal topologies have less SNR variations compared to traditional ones.     

Cost/Quality Trade-off in Synthesis for BIST

This paper details our allocation for Built-in Self Test (BIST) technique used by the core part of our Testability Allocation and Control System (TACOS) called IDAT. IDAT tool objective is to fulfill the designer requirements regarding selected design and testability attributes of a circuit data-path to be synthesized. A related tool is used to synthesize a test controller for the final testable circuit. The allocation process of BIST resources in the data-path is driven by two trade-off techniques performed in order to: (1) at the local level, select the optimal set of Functional Units (FUs) to be BISTed, using a new testability analysis method and (2) at the global level, for each selected FU of this set, choose either to allocate its BIST version (when available in a library) or to connect it to an internal Test Pattern Generator (TPG) and Test Results Checker (TRC). When necessary, a last step of the process is the allocation of scan chains used to test the remaining untested interconnections. Experiments show the results of our allocation for BIST technique on three benchmarks.     

Finite state machine synthesis with fault tolerant test function

According to a recent synthesis for testability proposal, a test function specified as a finite state machine with the same number of state variables as the given object machine, is incorporated into the state diagram prior to synthesis. Since a complete verification of the test machine is not practical, an often used heuristic sets and observes each state variable. The two machines share logic and a fault can result in partial or total loss of the test function. We show that the tests generated under the assumption that the entire test function is intact can become invalid. We propose a new method of synthesizing PLA-based finite state machines with fault tolerant test machines. Our approach eliminates testing of the test function. A constrained logic minimization phase insures that faults have predictable effect on the state diagram of the composite machine (object machine embedded with the test function). This allows effective use of the test function during test generation even in the presence of faults that effect both object and test machines. Only a combinational test generator is required for test generation. Each combinational vector is augmented by appropriate initialization and propagation sequences. Unlike prior approaches, ourO(log₂ n) length test sequence isguaranteed to detect any targeted crosspoint fault. Experimental results on the MCNC Logic Synthesis Workshop finite state machine benchmark set are given as evidence of practicality of the proposed approach.Supported by C&C Research Laboratories, NEC USA, during summer 1991.     

On the optimization of VLSI allocation in high-level synthesis

Allocation is one of main tasks in the high-level synthesis. It includes module , functional unit allocation, storage allocation and interconnection allocation. This paper models the allocation problem as cluster analysis and applies a new algorithm, neighbor state transition (NST) algorithm, for cluster optimization. It is proved that the algorithm produces an asymptotically global optimal solution with the upper bound on the cost function (1 O(1/n)2-ε)F*, When F" is the cost of the optimum solution, n is the problem size and e is a positive parameter arbitrarily close to zero. The numerical examples show that the NST algorithm produces better results compared to the other known methods.     

Improving circuit performance with multispeculative additive trees in high-level synthesis

The recent introduction of Variable Latency Functional Units (VLFUs) has broadened the design space of High-Level Synthesis (HLS). Nevertheless their use is restricted to only few operators in the datapaths because the number of cases to control grows exponentially. In this work an instance of VLFUs is described, and based on its structure, the average latency of tree structures is improved. Multispeculative Functional Units (MSFUs) are arithmetic Functional Units that operate using several predictors for the carry signal. In spite of utilizing more than a predictor, none or only one additional very short cycle is enough for producing the correct result in the majority of the cases. In this paper our proposal takes advantage of multispeculation in order to increase the performance of tree structures with a negligible area penalty. By judiciously introducing these structures into computation trees, it will only be necessary to predict the carry signals in certain selected nodes, thus minimizing the total number of predictions and the number of operations that can potentially mispredict. Hence, the average latency will be diminished and thus performance will be increased. Our experiments show that it is possible to improve 26% execution time. Furthermore, our flow outperforms previous approaches with Speculative FUs.     

Integrating operation scheduling and binding for functional unit power-gating in high-level synthesis

Power-gating-aware design has been an active area of research in the last decade, aiming at reducing power dissipation while meeting a desired system throughput. In this study, an algorithm integrating both scheduling and binding processes is developed with the functional unit (FU) power-gating technique, to achieve maximum leakage energy reduction under both performance and resource constraints. Firstly, the possible leakage energy reductions of all idle intervals are analyzed by evaluating the operation mobilities. Secondly, a split network indicating the leakage energy reduction in each idle interval is constructed, and a min-cost flow-based algorithm is conducted to this network to evaluate the total leakage energy saving from power-gating FUs; operations are scheduled to the clock cycles and bound to FUs with a maximization of leakage energy saving. Finally, proper FUs are clustered under power domain constraints to maximize the leakage energy saving while reducing the area and wirelength penalties for fine grain power-gating. Experimental results show the effectiveness of our proposed algorithms in saving leakage energy.     

Learning spatial hierarchies of high-level features in deep neural network

This paper addresses a new approach to learn perceptual grouping of the extracted features of the convolutional neural network (CNN) to represent the structure contained in the image. In CNN, the spatial hierarchies between the high-level features are not taken into account. To do so, the perceptual grouping of features is utilized. To consider the intra-relationship between feature maps, modified Guided Co-occurrence Block (mGCoB) is proposed. This block preserves the joint co-occurrence of two features in the spatial domain and it prevents the co-adaptation. Also, to preserve the interrelationship in each feature map, the principle of common region grouping is utilized which states that the features which are located in the same feature map tend to be grouped together. To consider it, an MFC block is proposed. To evaluate the proposed approach, it is applied to some known semantic segmentation and image classification datasets that achieve superior performance.     

New advances of high-level synthesis for efficient and reliable hardware design

The spectacular CMOS technology scaling will continue to evolve and dominate the semiconductor industry. This will lead to tens of billions of transistors integrated on a single chip by the year 2020. However, one significant problem is that the design productivity for complex designs has been lagging behind. In addition to several proposed techniques for dealing with the widening productivity gap, e.g., IP reuse and integration, virtual platform modeling, formal verification and others, high-level synthesis (HLS) has been touted as an important solution as it can significantly reduce the number of man-hours required for a design by raising the level of design abstraction. However, existing HLS solutions have limitations, and studies show that the design quality of HLS can be inferior compared to that of manual RTL design. In this paper, we will present a set of new techniques developed recently to drastically improve HLS solutions, which not only improve the traditional design metrics such as circuit performance and energy efficiency but also emerging metrics such as hardware security and robustness. We will also discuss how HLS can collaborate with other techniques to provide a holistic design methodology that can enable the delivery of high-quality designs with much less design cost and much faster time-to-market.     

国内第一条真空灭弧室自动检测线的建立

应用工业工程的方法,对灭弧室成品检验进行了作业流程分析,概述了灭弧室自动检测线的建立过程,描述了灭弧室成品检验进行工业自动化改造的应用效果,提高检测效率3倍以上,降低劳动强度80%。