Characterization of Self-Formed Ti-Rich Interface Layers in Cu(Ti)/Low-k Samples

In our previous studies, thin Ti-rich diffusion barrier layers were found to be formed at the interface between Cu(Ti) films and SiO₂/Si substrates after annealing at elevated temperatures. This technique was called self-formation of the diffusion barrier, and is attractive for fabrication of ultralarge-scale integrated (ULSI) interconnects. In the present study, we investigated the applicability of this technique to Cu(Ti) alloy films which were deposited on low dielectric constant (low-k) materials (SiO _x C _y ), SiCO, and SiCN dielectric layers, which are potential dielectric layers for future ULSI Si devices. The microstructures were analyzed by transmission electron microscopy (TEM) and secondary-ion mass spectrometry (SIMS), and correlated with the electrical properties of the Cu(Ti) films. It was concluded that the Ti-rich interface layers were formed in all the Cu(Ti)/dielectric-layer samples. The primary factor to control the composition of the self-formed Ti-rich interface layers was the C concentration in the dielectric layers rather than the enthalpy of formation of the Ti compounds (TiC, TiSi, and TiN). Crystalline TiC was formed on the dielectric layers with a C concentration higher than 17 at.%.     

Ti-Rich Barrier Layers Self-Formed on Porous Low-k Layers Using Cu(1?at.%?Ti) Alloy Films

To investigate the applicability of the technique of barrier self-formation using Cu(Ti) alloy films on porous low-k dielectric layers, Cu(1 at.% Ti) alloy films were deposited on porous SiOCH (low-k) dielectric layers in samples with and without ~6.5-nm-thick SiCN pore seals. Ti-rich barrier layers successfully self-formed on the porous low-k layer of both sample types after annealing in Ar for 2 h at 400°C to 600°C. The Ti-rich barrier layers consisted of amorphous Ti oxides and polycrystalline TiC for the samples without pore sealing, and amorphous TiN, TiC, and Ti oxides for the pore-sealed samples. The amorphous TiN originated from reaction of Ti atoms with the pore seal, and formed beneath the Cu alloy films. This may explain two peaks of Ti segregation at the interface that appeared in Rutherford backscattering spectroscopy (RBS) profiles, and suggests that the Ti-rich barrier layers self-formed by the reaction of Ti atoms with the pore seal and porous low-k layers separately. The total molar amount of Ti atoms segregated at the interface in the pore-sealed samples was larger than that in the samples without pore sealing, resulting in lower resistivity. On the other hand, resistivity of the Cu alloy films annealed on the porous low-k layers was lower than that annealed on the nonporous low-k layers. Coarser Cu columnar grains were observed in the Cu alloy films annealed on the porous low-k layers, although the molar amount of Ti atoms segregated at the interface was similar in both sample types after annealing. The cause could be faster reaction of the Ti atoms with the porous dielectric layers.     

Effects of Substrate Materials on Self-Formation of Ti-Rich Interface Layers in Cu(Ti) Alloy Films

In our previous studies, thin Ti-rich layers were found to uniformly cover SiO₂/Si substrate surfaces at the interface with Cu(Ti) alloy films after annealing at elevated temperature. These Ti-rich layers were also found to prevent intermixing between the Cu(Ti) alloy films and the substrate, resulting in a simple barrier formation technique, called “self-formation of the diffusion barrier,” which is attractive for fabrication of ultra-large scale integrated (ULSI) interconnect structures. In the present study, to understand the mechanism of self-formation of the Ti-rich barrier layers on the substrate surface, the effects of SiO₂/Si, SiN/SiO₂/Si and NaCl substrate materials on the interfacial microstructure were investigated. The microstructures were analyzed by transmission electron microscopy (TEM) and secondary ion mass spectrometry (SIMS), and correlated with the electrical properties of the Cu(Ti) interconnects. It was concluded that the chemical reaction of Ti with the substrate materials was essential for the self-formation of the Ti-rich layers.     

Fabrication of Cu(Ti) Alloy Interconnects with Self-Formation of Thin Barrier Metal Layers Using a High-Pressure Annealing Process

Copper interconnects with self-formed thin TiSi _x O _y barrier layers were successfully fabricated by sequentially depositing Cu(7 at.%Ti) alloys and pure Cu films on SiO₂-based substrates with 0.1-μm-wide trenches, and embedding the samples using a high-pressure annealing technique at 550°C and 195 MPa. Microstructural analyses revealed that the self-formed Ti-rich layers with thicknesses of about 5 nm were uniformly formed on the trench bottom and sidewall. In addition, these layers were thermally stable against Cu diffusion into the SiO₂-based interlayers. The present study suggests that the Cu-Ti alloy is one of the best candidates among possible interconnect and/or seed layer materials.     

Improving the open‐circuit voltage of Cu2ZnSnSe4 thin film solar cells via interface passivation

This study reports on substantial improvement of the open‐circuit voltage (V _oc) of Cu₂ZnSnSe₄ (CZTSe) thin film solar cells by applying a passivation strategy to both the top and bottom interfaces of the CZTSe absorber, which involves insertion of a thin dielectric layer between the CZTSe and the surrounding layers. The study also presents in‐depth material characterizations using transmission electron microscopy, energy dispersive X‐ray spectroscopy, low‐temperature photoluminescence, and secondary ion mass spectrometry, to reveal the effects of the interface passivation. To passivate the bottom Mo/CZTSe interface, a dielectric layer with patterned local contacts of dimensions down to ~100 nm was prepared using nanosphere lithography. With this, the V _oc, short‐circuit current, and fill factor (FF) were significantly enhanced due to reduction in carrier recombination at the bottom Mo/CZTSe interface. The top CZTSe/CdS interface was passivated by a thin dielectric layer which prevented inter‐diffusion of Cd and Cu at the top interface, thereby improving the junction quality. Application of the top passivation layers resulted in substantial improvement in V _oc and FF, thereby achieving the V _oc deficit of 0.542 V which is the record value among reported CZTSe solar cells. Copyright © 2017 John Wiley & Sons, Ltd.     

Formation of Ti diffusion barrier layers in Thin Cu(Ti) alloy films

In order to study a formation mechanism of thin Ti-rich layers formed on the surfaces of Cu(Ti) wires after annealing at elevated temperatures, the 300-nm-thick Cu(Ti) alloy films with Ti concentration of 1.3 at.% or 2.9 at.% were prepared on the SiO₂/Si substrates by a co-sputter deposition technique. The electrical resistivity and microstructural analysis of these alloy films were carried out before and after annealing at 400°C. The Ti-rich layers with thickness of ∼15 nm were observed to form uniformly both at the film surface and the substrate interfaces in the Cu(2.9at.%Ti) films after annealing (which we call the self-formation of the layers) using Rutherford backscattering spectrometry (RBS) and transmission electron microscopy (TEM). Both the resistivities and the microstructures of these Cu(Ti) films were found to depend strongly on the Ti concentrations. The resistivities of the films decreased upon annealing due to segregation of the supersaturated Ti solutes in the alloy films to both the top and bottom of the films. These Ti layers had excellent thermal stability and would be applicable to the self-formed diffusion barrier in Cu interconnects of highly integrated devices. The selection rules of the alloy elements for the barrier self-formation were proposed based on the present results.     

Effect of Annealing Ambient on the Self-Formation Mechanism of Diffusion Barrier Layers Used in Cu(Ti) Interconnects

Copper (titanium) [Cu(Ti)] films with low titanium (Ti) concentration were found to form thin Ti-rich barrier layers at the film/substrate interfaces after annealing, which is referred to as self-formation of the barrier layers. This Cu(Ti) alloy was one of the best candidates for interconnect materials used in next-generation ultra-large-scale integrated (ULSI) devices that require both very thin barrier layers and low-resistance interconnects. In the present paper, in order to investigate the influences of annealing ambient on resistivity and microstructure of the Cu alloys, the Cu(7.3at.%Ti) films were prepared on the SiO₂ substrates and annealed at 500°C in ultra-high vacuum (UHV) or argon (Ar) with a small amount of impurity oxygen. After annealing the film at 500°C in UHV, the resistivity was not reduced below 16 μΩ-cm. Intermetallic compounds of Cu₄Ti were observed to form in the films and believed to cause the high resistivity. However, after subsequently annealing in Ar, these compounds were found to decompose to form surface TiO _x and interfacial barrier layers, and the resistivity was reduced to 3.0 μΩ-cm. The present experiment suggested that oxygen reactive to titanium during annealing played an important role for both self-formation of the interfacial barrier layers and reduction of the interconnect resistivity.     

Interfacial Reactions of Sn-3.5Ag-<Emphasis Type="Italic">x</Emphasis>Zn Solders and Cu Substrate During Liquid-State Aging

The effects of Zn (1 wt.%, 3 wt.%, and 7 wt.%) additions to Sn-3.5Ag solder and various reaction times on the interfacial reactions between Sn-3.5Ag-xZn solders and Cu substrates a during liquid-state aging were investigated in this study. The composition and morphological evolution of interfacial intermetallic compounds (IMCs) changed significantly with the Zn concentration and reaction time. For the Sn-3.5Ag-1Zn/Cu couple, CuZn and Cu₆Sn₅ phases formed at the interface. With increasing aging time, the Cu₆Sn₅ IMC layer grew thicker, while the CuZn IMC layer drifted into the solder and decomposed gradually. Cu₅Zn₈ and Ag₅Zn₈ phases formed at the interfaces of Sn-3.5Ag-3Zn/Cu and Sn-3.5Ag-7Zn/Cu couples. With increasing reaction time, the Cu₅Zn₈ layer grew and Cu atoms diffused from the substrate to the solder, which transformed the Ag₅Zn₈ to (Cu,Ag)₅Zn₈. The Cu₆Sn₅ layer that formed between the Cu₅Zn₈ layer and Cu was much thinner at the Sn-3.5Ag-7Zn/Cu interface than at the Sn-3.5Ag-3Zn/Cu interface. Additionally, we measured the thickness of interfacial IMC layers and found that 3 wt.% Zn addition to the solder was the most effective for suppressing IMC growth at the interfaces.     

The effects of boron in the Cu(B)/Ti/SiO<Subscript>2</Subscript> system on the Cu-Ti reaction,resistivity, and diffusion barrier properties

The behavior of boron in Cu(4.8at.%B)/Ti/SiO₂ was investigated as a function of temperature, and its influences on the Cu-Ti interaction, resistivity, and diffusion barrier properties were also studied. The results showed the formation of a titanium boride layer at the Cu-Ti interface, after heating the Cu(B)/Ti/SiO₂ at 400°C and higher, effectively served as a barrier for the Cu and Ti diffusion, and significantly enhanced the Cu (111) texture. The resistivity dropped from 16.3 to 2.33 μΩ-cm after heating at 600°C, and continued to decrease up to 800°C. As a result, the Cu, in the form of B(O)_x/Cu/TiB₂/Ti(O)_x/SiO₂ multilayers, obtained by heating the Cu(B)/Ti/SiO₂, showed high thermal stability with low resistivity and, thus, can be used as interconnections in advanced integrated circuits. Since the Cu, in the form of B(O)_x/Cu/TiB₂/Ti(O)_x/SiO₂ multilayers, obtained by heating the Cu(B)/Ti/SiO₂, showed high thermal stability with low resistivity, it can be used as interconnections in advanced integrated circuits.     

Ultra-Thin Si<Subscript>1−<Emphasis Type="Italic">x</Emphasis></Subscript>Ge<Subscript><Emphasis Type="Italic">x</Emphasis></Subscript> Dislocation Blocking Layers for Ge/Strained Si CMOS Devices

We demonstrate ultra-thin (<150 nm) Si_1−x Ge _x dislocation blocking layers on Si substrates used for the fabrication of tensile-strained Si N channel metal oxide semiconductor (NMOS) and Ge P channel metal oxide semiconductor (PMOS) devices. These layers were grown using ultra high vacuum chemical vapor deposition (UHVCVD). The Ge mole fraction was varied in rapid, but distinct steps during the epitaxial layer growth. This results in several Si_1−x Ge _x interfaces in the epitaxially grown material with significant strain fields at these interfaces. The strain fields enable a dislocation blocking mechanism at the Si_1−x Ge _x interfaces on which we were able to deposit very smooth, atomically flat, tensile-strained Si and relaxed Ge layers for the fabrication of high mobility N and P channel metal oxide semiconductor (MOS) devices, respectively. Both N and P channel metal oxide semiconductor field effect transister (MOSFETs) were successfully fabricated using high-k dielectric and metal gates on these layers, demonstrating that this technique of using ultra-thin dislocation blocking layers might be ideal for incorporating high mobility channel materials in a conventional CMOS process.     

Air-Gaps for High-Performance On-Chip Interconnect Part II: Modeling, Fabrication, and Characterization

Air-gaps are the ultimate low-k material in microelectronics due to air having a low dielectric constant close to 1.0. The interconnect capacitance can further be reduced by extending the air-gaps into the interlayer dielectric region to reduce the fringing electric field. An electrostatic model (200 nm half-pitch interconnect with an aspect ratio of 2.0), was used to evaluate the dielectric properties of the air-gap structures. The incorporation of air-gaps into the intrametal dielectric region reduced the capacitance by 39% compared with SiO₂. Extending the air-gap 100 nm into the top and bottom interlayer SiO₂ region lowered the capacitance by 49%. The ability to fabricate air-gaps and ‹extended air-gaps’ was demonstrated, and the capacitance decrease was experimentally verified. Cu/air-gap and extended Cu/air-gap interconnect structures were fabricated using high-modulus tetracyclododecene (TD)-based sacrificial polymer. The aspect ratio of the air-gap was 1.8 and the air-gap was extended 80 nm and 100 nm into the top and bottom interlevel SiO₂ region, respectively. The measured effective dielectric constant (k _eff) of the Cu/air-gap and the extended Cu/air-gap structures with SiO₂ interlevel dielectric was 2.42 and 2.17, respectively. The effect of moisture uptake within the extended Cu/air-gap structure was investigated. As the relative humidity increased from 4% to 92%, the k _eff increased by 7%. Hexamethyldisilazane was used to remove adsorbed moisture and create a hydrophobic termination within the air-cavities, which lowered the effect of humidity on the k _eff. A dual Damascene air-gap and extended air-gap fabrication processes were proposed and the challenges of using a sacrificial polymer placeholder approach to form air-cavities are compared to other integration approaches of dual Damascene air-gap.     

Impedance Spectroscopy of Dielectric BaTi<Subscript>5</Subscript>O<Subscript>11</Subscript> Film Prepared by Laser Chemical Vapor Deposition Method

BaTi₅O₁₁ film was prepared on Pt/Ti/SiO₂/Si substrate by the laser chemical vapor deposition method. A single-phase BaTi₅O₁₁ film with ([`3] 22)/([`2] 23) (\overline{3} 22)/(\overline{2} 23) preferred orientation and columnar cross-section was obtained at high deposition rate (154.8 μm h⁻¹). The dielectric constant (ε _r) of the BaTi₅O₁₁ film was 21, measured at 300 K and 1 MHz. The electrical properties of the BaTi₅O₁₁ film were investigated by ac impedance spectroscopy from 300 K to 1073 K at 10² Hz to 10⁷ Hz. Plots of the real and imaginary parts of the impedance (Z′ and Z″) and electrical modulus (M′ and M″) in the above frequency and temperature range suggested the presence of two relaxation regimes, which were attributed to grain and grain boundary responses. The ac conductivity plots as a function of frequency showed three types of conduction process at elevated temperature. The frequency-independent plateau at low frequency was due to dc conductivity. The mid-frequency conductivity was due to grain boundaries, while the high-frequency conductivity was due to grains.     

Growth of lanthanum oxide films for application as a gate dielectric in CMOS technology

We have investigated properties of insulating lanthanum oxide (La₂O₃) films in connection with the replacement of silicon oxide (SiO₂) gate dielectrics in new generation of CMOS devices. The La₂O₃ layers were grown using metal organic chemical vapour deposition (MOCVD) at 500 °C. X-ray diffraction analysis revealed polycrystalline character of the films grown above 500 °C. The X-ray photoemission spectroscopy detected lanthanum carbonate as a principal impurity in the films and lanthanum silicate at the interface with silicon. Density of oxide charge, interface trap density, leakage currents and dielectric constant ( κ) were extracted from the C-V and I-V measurements. Electrical properties, in particular dielectric constant of the MOCVD grown La₂O₃ are discussed with regard to the film preparation conditions. The as grown film had κ11. Electrical measurements indicate possible presence of oxygen vacancies in oxide layer. The O₂-annealed La₂O₃ film had κ17.     

Thermal Stability Study of Cu(MoN<Subscript><Emphasis Type="Italic">x</Emphasis></Subscript>) Seed Layer on Barrierless Si

This study reports the good thermal stability of a sputtered Cu(MoN _x ) seed layer on a barrierless Si substrate. A Cu film with a small amount of MoN _x was deposited by reactive co-sputtering of Cu and Mo in an Ar/N₂ gas mixture. After annealing at 560°C for 1 h, no copper silicide formation was observed at the interface of Cu and Si. Leakage current and resistivity evaluations reveal the good thermal reliability of Cu with a dilute amount of MoN _x at temperatures up to 560°C, suggesting its potential application in advanced barrierless metallization. The thermal performance of Cu(MoN _x ) as a seed layer was evaluated when pure Cu is deposited on top. X-ray diffraction, focused ion beam microscopy, and transmission electron microscopy results confirm the presence of an ∼10-nm-thick reaction layer formed at the seed layer/Si interface after annealing at 630°C for 1 h. Although the exact composition and structure of this reaction layer could not be unambiguously identified due to trace amounts of Mo and N, this reaction layer protects Cu from a detrimental reaction with Si. The Cu(MoN _x ) seed layer is thus considered to act as a diffusion buffer with stability up to 630°C for the barrierless Si scheme. An electrical resistivity of 2.5 μΩ cm was obtained for the Cu/Cu(MoN _x ) scheme after annealing at 630°C.     

Electrical characteristics of Au/<Emphasis Type="Italic">n</Emphasis>-GaAs structures with thin and thick SiO<Subscript>2</Subscript> dielectric layer

The aim of this study, to explain effects of the SiO₂ insulator layer thickness on the electrical properties of Au/n-GaAs Shottky barrier diodes (SBDs). Thin (60 Å) and thick (250 Å) SiO₂ insulator layers were deposited on n-type GaAs substrates using the plasma enganced chemical vapour deposition technique. The current-voltage (I–V) and capacitance-voltage (C-V) characteristics have been carried out at room temperature. The main electrical parameters, such as ideality factor (n), zero-bias barrier height (? _Bo ), series resistance (R _s ), leakage current, and interface states (N _ss ) for Au/SiO₂/n-GaAs SBDs have been investigated. Surface morphologies of the SiO₂ dielectric layer was analyzed using atomic force microscopy. The results show that SiO₂ insulator layer thickness very affects the main electrical parameters. Au/n-GaAs SBDs with thick SiO₂ insulator layer have low leakage current level, small ideality factor, and low interface states. Thus, Au/n-GaAs SBDs with thick SiO₂ insulator layer shows better diode characteristics than other.     

Study of Interfacial Reactions Between Sn(Cu) Solders and Ni-Co Alloy Layers

The interfacial reactions between electroplated Ni-yCo alloy layers and Sn(Cu) solders at 250°C are studied. For pure Co layers, CoSn₃ is the only interfacial compound phase formed at the Sn(Cu)/Co interfaces regardless of the Cu concentration. Also, the addition of Cu to Sn(Cu) solders has no obvious influence on the CoSn₃ compound growth at the Sn(Cu)/Co interfaces. For Ni-63Co layers, (Co,Ni,Cu)Sn₃ is the only interfacial compound phase formed at the Sn(Cu)/Ni-63Co interfaces. Unlike in the pure Co layer cases, the Cu additives in the Sn(Cu) solders clearly suppress the growth rate of the interfacial (Co,Ni,Cu)Sn₃ compound layer. For Ni-20Co layers, the interfacial compound formation at the Sn(Cu)/Ni-20Co interfaces depends on the Cu content in the Sn(Cu) solders and the reflow time. In the case of high Cu content in the Sn(Cu) solders (Sn-0.7Cu and Sn-1.2Cu), an additional needle-like interfacial (Ni _x ,Co _y ,Cu_1−x−y )₃Sn₄ phase forms above the continuous (Ni _x ,Cu _y ,Co_1−x−y )Sn₂ compound layer. The Ni content in the Ni-yCo layer can indeed reduce the interfacial compound formation at the Sn(Cu)/Ni-yCo interfaces. With pure Sn solders, the thickness of the compound layer monotonically decreases with the Ni content in the Ni-yCo layer. As for reactions with the Sn(Cu) solders, as the compound thickness decreases, the Ni content in the Ni-yCo layers increases.     

Vertical Phase Separated Cesium Fluoride Doping Organic Electron Transport Layer: A Facile and Efficient “Bridge” Linked Heterojunction for Perovskite Solar Cells

In perovskite solar cells (PSCs), the interfaces of the halide perovskite/electron transport layer (ETL) and ETL/metal oxide electrode (MOE) always attract and trap free carriers via the surface electrostatic force, altering quasi‐Fermi level (E_Fq) splitting of contact interfaces, and significantly limit the charge extraction efficiency and intrinsic stability of devices. Herein, a graded “bridge” is first reported to link the MOE and perovskite interfaces by self vertical phase separation doping (PSD), diminishing the side effect of notorious ionic defects via both reinforced interface E_bi and the vacancies filling. Experimental and theoretical results prove that the inhomogeneous distribution of CsF in the bulk or surface of PC₆₁BM would not only form metal–oxygen (M–O) dipole on MOE, reinforcing the interface E_bi, but also create a graded energy bridge to alleviate the disadvantage of band offset raised by the enhanced interface E_bi, which significantly avoid the carrier accumulation and recombination at defective interfaces. Employing PSD, the power conversion efficiency of the devices approaches 21% with a high open‐circuit voltage (1.148 V) and delivers a high stability of 89% after aging 60 days in atmosphere without encapsulation, which is the highest efficiency of organic electron transport layers for n–i–p PSCs.     

Preparation and Ferroelectric Properties of Ho<Superscript>3+</Superscript>/Mo<Superscript>6+</Superscript> Cosubstituted Bi<Subscript>4</Subscript>Ti<Subscript>3</Subscript>O<Subscript>12</Subscript> Thin Films by Sol–Gel Method

We have prepared Ho³⁺/Mo⁶⁺ cosubstituted bismuth titanate [(Bi_3.6Ho_0.4)_3.99- Ti_2.985Mo_0.015O₁₂, BHTM] thin films on Pt/Ti/SiO₂/Si substrates using the sol–gel method. The crystal structure and morphology of the BHTM films were characterized. The BHTM samples show a single phase of Bi-layered Aurivillius structure and a dense microstructure. The dielectric constant and dielectric loss of the BHTM films were about 359 and 0.043, respectively, at a frequency of 1 MHz. The films exhibit 2P _r of 57.7 μC/cm² and 2E _c of 290.0 kV/cm at an applied field of 470 kV/cm, and have fatigue-free characteristics. They also showed good insulating behavior according to leakage current testing.     

Modeling the silicon–hafnia interface

We report first-principles calculations of the structure and electronic properties of several different silicon–hafnia interfaces. The structures have been obtained by growing HfO_x layers of different stoichiometry on Si(1 0 0) and by repeated annealing of the system using molecular dynamics. The interfaces are characterised via their electronic and geometric properties. Moreover, electronic transport through the interfaces has been calculated using finite-element-based Green's function methods. We find that oxygen always diffuses towards the interface to form a silicon dioxide layer. This results in the formation of dangling Hf bonds in the oxide, saturated by either Hf diffusion or formation of Hf–Si bonds. The generally poor performance of the interfaces suggests that it is important to stabilise the system with respect to oxygen lattice diffusion.     

Effect of Rapid Thermal Annealing on Sputtered CaCu<Subscript>3</Subscript>Ti<Subscript>4</Subscript>O<Subscript>12</Subscript> Thin Films

Calcium copper titanium oxide (CaCu₃Ti₄O₁₂, abbreviated to CCTO) films were deposited on Pt/Ti/SiO₂/Si substrates at room temperature (RT) by radiofrequency magnetron sputtering. As-deposited CCTO films were treated by rapid thermal annealing (RTA) at various temperatures and in various atmospheres. X-ray diffraction patterns and scanning electron microscope (SEM) images demonstrated that the crystalline structures and surface morphologies of CCTO thin films were sensitive to the annealing temperature and ambient atmosphere. Polycrystalline CCTO films could be obtained when the annealing temperature was 700°C in air, and the grain size increased signifi- cantly with annealing in O₂. The 0.8-μm CCTO thin film that was deposited at RT for 2 h and then annealed at 700°C in O₂ exhibited a high dielectric constant (ε′) of 410, a dielectric loss (tan δ) of 0.17 (at 10 kHz), and a leakage current density (J) of 1.28 × 10⁻⁵ A/cm² (at 25 kV/cm).