用减压化学气相沉积技术制备应变硅材料

利用减压化学气相沉积技术，制备出应变Si/弛豫Si0.9Ge0.1/渐变组分弛豫SiGe/Si衬底. 通过控制组分渐变SiGe过渡层的组分梯度和适当优化弛豫SiGe层的外延生长工艺，有效地降低了表面粗糙度和位错密度.与Ge组分突变相比，采用线性渐变组分后，应变硅材料表面粗糙度从3.07nm减小到0.75nm，位错密度约为5E4cm-2，表面应变硅层应变度约为0.45%.     

半导体锗纳米团簇和纳米层的生成与结构研究

我们在硅锗合金衬底上采用氧化等制膜方式生成零维和二维的纳米结构样品，用高精度椭偏仪(HPE)、卢瑟福背散射谱仪(RBS)和高分辨率扫描透射电子显微镜(HR-STEM)测量样品的纳米结构，并采用美国威思康新州立大学开发的Rump模拟软件对卢瑟福背散射谱(RBS)中的CHANNEL谱和RANDoM谱分别进行精细结构模拟，测量并计算出纳米氧化层与锗的纳米薄膜结构分布，并且反馈控制加工过程，优化硅锗半导体材料纳米结构样品的加工条件。我们测量出样品横断面锗纳米团簇和纳米层的PL发光谱。我们在硅锗合金的氧化层表面中首次发现纳米锗量子点组成的几个纳米厚的盖帽膜结构，我们首次提出的生成硅锗纳米结构的优化加工条件的氧化时间和氧化温度匹配公式的理论模型与实验结果拟合得很好。     

采用SiGe虚拟衬底高迁移率应变硅材料的制备和表征

研究了生长在弛豫Si0.79Ge0.21/梯度Si1-xGex/Si虚拟衬底上的应变硅材料的制备和表征,这一结构是由减压外延气相沉积系统制作的.根据双晶X射线衍射计算出固定组分SiGe层的Ge浓度和梯度组分SiGe层的梯度,并由二次离子质谱仪测量验证.由原子力显微术和喇曼光谱测试结果得到应变硅帽层的表面粗糙度均方根和应变度分别为2.36nm和0.83%;穿透位错密度约为4×104cm-2.此外,发现即使经受了高热开销过程,应变硅层的应变仍保持不变.分别在应变硅和无应变的体硅沟道上制作了nMOSFET器件,并对它们进行了测量.相对于同一流程的体硅MOSFET,室温下观测到应变硅器件中电子的低场迁移率显著增强,约为85%.     

采用SiGe虚拟衬底高迁移率应变硅材料的制备和表征

研究了生长在弛豫Si0.79Ge0.21/梯度Si1-xGex/Si虚拟衬底上的应变硅材料的制备和表征,这一结构是由减压外延气相沉积系统制作的.根据双晶X射线衍射计算出固定组分SiGe层的Ge浓度和梯度组分SiGe层的梯度,并由二次离子质谱仪测量验证.由原子力显微术和喇曼光谱测试结果得到应变硅帽层的表面粗糙度均方根和应变度分别为2.36nm和0.83%;穿透位错密度约为4×104cm-2.此外,发现即使经受了高热开销过程,应变硅层的应变仍保持不变.分别在应变硅和无应变的体硅沟道上制作了nMOSFET器件,并对它们进行了测量.相对于同一流程的体硅MOSFET,室温下观测到应变硅器件中电子的低场迁移率显著增强,约为85%.     

Double-diffused graded SiGe-base bipolar transistors

Self-aligned SiGe/Si bipolar transistors have been fabricated using a single-polysilicon, double-diffused process with the base in a graded SiGe layer to improve base transit time. To remain compatible with homojunction bipolar technology, undoped SiGe base and Si emitter layers were deposited by selective epitaxy at temperatures of 700-750°C in a commercial epitaxial reactor. Maximum cutoff frequencies of 40 and 50 GHz were observed for devices with collector-emitter breakdown voltages (BV_CEO) of 4.2 and 3.0 V, respectively. Preliminary results indicate that the addition of Ge to the base of these transistors did not degrade the long-term device reliability     

Fabrication of thick, high-quality strained SiGe layer on ultra-thin silicon-on-insulator and modeling of film strain

Fabrication of a thick strained SiGe layer on bulk silicon is hampered by the lattice mismatch and difference in the thermal expansion coefficients between Si and SiGe, and a high Ge content leads to severe strain in the SiGe film. When the thickness of the SiGe film is above a critical value (90 nm for 18% Ge), drastic deterioration of the film properties as well as dislocations will result. In comparison, a silicon-on-insulator (SOI) substrate with a thin top Si layer can mitigate the problems and so a thick SiGe layer with high Ge concentration can conceivably be synthesized. In the work reported here, a 110 nm thick high-quality strained Si_0.82Ge_0.18 layer was fabricated on an ultra-thin SOI substrate with a 30 nm top silicon layer using ultra-high vacuum chemical vapor deposition (UHVCVD). The thickness of the SiGe layer is larger than the critical thickness on bulk Si. Cross-sectional transmission electron microscopy (XTEM) reveals that the SiGe layer is dislocation-free and the atoms at the SiGe/Si interface are well aligned, even though X-ray diffraction (XRD) data indicate that the SiGe film is highly strained. The strain factors determined from the XRD and Raman results agree well.     

Vertically Stacked SiGe Nanowire Array Channel CMOS Transistors

We demonstrate, for the first time, the fabrication of vertically stacked SiGe nanowire (NW) arrays with a fully CMOS compatible technique. Our method uses the phenomenon of Ge condensation onto Si and the faster oxidation rate of SiGe than Si to realize the vertical stacking of NWs. Gate-all-around nand p-FETs, fabricated using these stacked NW arrays as the channel (L_gges0.35 mum), exhibit excellent device performance with high I_ON/I_OFF ratio (~10⁶), near ideal subthreshold slope (~62-75 mV/dec) and low drain induced barrier-lowering (~20 mV/V). The transconductance characteristics suggest quantum confinement of holes in the [Ge]-rich outer-surface of SiGe for p-FETs and confinement of electrons in the core Si with significantly less [Ge] for n-FETs. The presented device architecture can be a promising option to overcome the low drive current restriction of Si NW MOSFETs for a given planar estate     

应变Si1-xGex沟道PMOSFET空穴局域化研究

为充分利用应变 Si Ge材料相对于 Si较高的空穴迁移率 ,研究了 Si/Si Ge/Si PMOSFET中垂直结构和参数同沟道开启及空穴分布之间的依赖关系。在理论分析的基础上 ,以数值模拟为手段 ,研究了栅氧化层厚度、Si帽层厚度、Si Ge层 Ge组分及厚度、缓冲层厚度及衬底掺杂浓度对阈值电压、交越电压和空穴分布的影响与作用 ,特别强调了 δ掺杂的意义。模拟和分析表明 ,栅氧化层厚度、Si帽层厚度、Si Ge层 Ge组分、衬底掺杂浓度及 δ掺杂剂量是决定空穴分布的主要因素 ,而 Si Ge层厚度、缓冲层厚度和隔离层厚度对空穴分布并不敏感。最后总结了沟道反型及空穴分布随垂直结构及参数变化的一般规律 ,为优化器件设计提供了参考。     

Applications and processing of SiGe and SiGe:C for high-speed HBT devices

The continued growth of high-speed-digital data transmission and wireless communications technology has motivated increased integration levels for ICs serving these markets. Further, the increasing use of portable wireless communications tools requiring long battery lifetimes necessitates low power consumption by the semiconductor devices within these tools. The SiGe and SiGe:C materials systems provide solutions to both of these market needs in that they are fully monolithically integratible with Si BiCMOS technology. Also, the use of SiGe or SiGe:C HBTs for the high-frequency bipolar elements in the BiCMOS circuits results in greatly decreased power consumption when compared to Si BJT devices.Either a DFT (graded Ge content across the base) or a true HBT (constant Ge content across the base) bipolar transistor can be fabricated using SiGe or SiGe:C. Historically, the graded profile has been favored in the industry since the average Ge content in the pseudomorphic base is less than that of a true HBT and, therefore, the DFT is tolerant of higher thermal budget processing after deposition of the base. The inclusion of small amounts of C (e.g. <0.5%) in SiGe is effective in suppressing the diffusion of B such that very narrow extremely heavily doped base regions can be built. Thus the f_T and f_max of a SiGe:C HBT/DFT are capable of being much higher than that of a SiGe HBT/DFT.The growth of the base region can be accomplished by either nonselective mixed deposition or by selective epitaxy. The nonselective process has the advantage of reduced complexity, higher deposition rate and, therefore, higher productivity than the selective epitaxy process. The selective epi process, however, requires fewer changes to an existing fabrication sequence in order to accommodate SiGe or SiGe:C HBT/DFT devices into the BiCMOS circuit.     

Reduction of boron diffusion in silicon-germanium by fluorine implantation

This letter investigates the effect of a 185 keV, 2.3 /spl times/ 10/sup 15/ cm/sup -2/ F/sup +/ implant on boron transient enhanced diffusion (TED) and boron thermal diffusion in SiGe by characterizing the diffusion of a boron marker layer in samples with and without a 288 keV, 6 /spl times/ 10/sup 13/ cm/sup -2/ P/sup +/ implant. In samples implanted with F/sup +/ only, the fluorine suppresses boron thermal diffusion by 58%. In samples given both P/sup +/ and F/sup +/ implants, the fluorine completely eliminates boron transient enhanced diffusion caused by the P/sup +/ implant and also significantly reduces boron thermal diffusion. SIMS profiles after anneal show a fluorine concentration in the SiGe layer that is approximately 8 /spl times/ higher than after implant, indicating that fluorine accumulates in the SiGe layer during anneal. A comparison with fluorine profiles in comparable silicon samples also shows that the fluorine concentration after anneal is dramatically higher in SiGe samples than in Si samples. This accumulation of fluorine in the SiGe layer during anneal will have major benefits for boron diffusion suppression in devices like SiGe HBTs, where boron must be kept within the SiGe layer.     

Excimer Laser‐Assisted In Situ Phosphorus Doped Si(1‐x)Gex Epilayer Activation

This paper presents results from experiments on laser‐annealed SiGe‐selective epitaxial growth (LA‐SiGe‐SEG). The SiGe‐SEG technology is attractive for devices that require a low band gap and high mobility. However, it is difficult to make such devices because the SiGe and the highly doped region in the SiGe layer limit the thermal budget. This results in leakage and transient enhanced diffusion. To solve these problems, we grew in situ doped SiGe SEG film and annealed it on an XMR5121 high power XeCl excimer laser system. We successfully demonstrated this LA‐SiGe‐SEG technique with highly doped Ge and an ultra shallow junction on p‐type Si (100). Analyzing the doping profiles of phosphorus, Ge compositions, surface morphology, and electric characteristics, we confirmed that the LA‐SiGe‐SEG technology is suitable for fabricating high‐speed, low‐power devices.     

氧化对SOI基SiGe薄膜残余应变弛豫的影响

研究了氧化对外延在SOI衬底上的SiGe薄膜的残余应变弛豫过程的影响.通过对SiGe薄膜采用不同工艺的氧化,从而了解不同氧化条件对SOI基SiGe薄膜的应变弛豫过程的影响.氧化将会促使SiGe薄膜中的Ge原子扩散到SOI材料的顶层硅中.而SiGe薄膜的残余应变弛豫过程将会与Ge原子的扩散过程同时进行,通过对SiGe薄膜和SOI顶层硅中位错分布的分析发现:在氧化过程中,SiGe薄膜和SOI衬底之间存在一个应力传递的过程.     

硅锗合金氧化后生成的锗纳米结构的特性研究

我们将SiGe合金在干氧吹气环境下以不同的温度和不同的时值进行氧化处理，用卢摄福散射仪RBS和高精度椭偏仪HP-ESM测量样品，获得10～80nm厚的硅氧化层和1nm厚的富锗层．新发现快速氧化生成的氧化膜表面有1～2nm厚的锗层．分析了锗纳米结构对应的PL发光谱，注意到锗纳米层对应的541nm波长的尖锐的发光峰和不同尺寸的锗原子团对应的从550～720nm波长的发光带．从量子受限模型和局域密度泛函计算出发。合理地解释了实验的结果．     

Carrier Depth Profile of Si/SiGe/Si n-p-n HBT Structural Materials Characterized by Electrochemical Capacitance-Voltage Method

Si/SiGe/Si n-p-n HBT structural materials have been grown by gas source molecular beam epitaxy with disilane, solid Ge, diborane and phosphine as sources. The materials are of good structural properties. The effectiveness of Electrochemical Capacitance-Voltage (ECV) technique on profiling the shallow doped layers of nanometer dimensions has been demonstrated. Compared with spreading resistance probe, the ECV technique is relatively easy to get the carrier distribution profile, especially for the Si/SiGe/Si HBT structural materials with shallow (≤50nm) base regions (p-type SiGe layer, Ge content about 0.2). The results show that n-p-n structures can be obtained by in situ doping.     

Photonic effects during low-temperature ultraviolet-assisted oxidation of SiGe

The behavior of Ge atoms during dry oxidation of Si_0.8Ge_0.2 films at 300°C under 10 mbar of oxygen induced by vacuum-ultraviolet (VUV) illumination from an array of Xe₂* excimer lamps (λ=172 nm) has been studied. During VUV oxidation, samples are exposed to both a high concentration of ozone and atomic oxygen and a large flux of energetic photons. X-ray photoelectron spectroscopy (XPS) and Fourier-transform infrared (FTIR) spectroscopy investigations showed that the layers grown for shorter periods of time contain mostly SiO₂ with a few percent GeO₂. Most of the Ge atoms, initially present uniformly within the SiGe layer, were segregated and accumulated at the interface between the grown oxide and remaining SiGe. Angle-resolved XPS showed that the amount of GeO₂ within the grown oxide layer decreased for longer irradiation times and was located adjacent to the SiGe layer. When the grown SiO₂ layer reached a thickness around ～70 Å and the amount of Ge that had accumulated in the segregated layer more than doubled, a sharp increase in the Ge oxidation rate was observed. Continuing the oxidation for longer irradiation times resulted in the formation of a mixed oxide layer. The Ge segregation was not previously observed during other low-temperature oxidation treatments, including ozone-assisted oxidation, which provides the same oxidation species as VUV-assisted oxidation and similar growth rates. It is, therefore, concluded that a VUV photon-irradiation enhancement effect on Si and Ge interdiffusion has been introduced, possibly involving either Si-Si or Si-Ge bond softening or even breaking.     

Anomalous distribution of germanium implanted into a SOI dielectric layer after the annealing of radiation defects

The germanium-distribution profile is investigated in a Si/SiO₂/Si structure after the implantation of ⁷⁴Ge into SiO₂ dielectric layer, bonding with the Si device layer, and high-temperature annealing. The anomalously high transport and accumulation of ⁷⁴Ge atoms near the SiO₂/Si interface far from the bonded boundary is found. The observed ⁷⁴Ge distribution is beyond the framework of the existing model of diffusion of Ge in Si and SiO₂ after postimplantation annealing. A modified model of diffusion of Ge atoms near the Si/SiO₂ interface qualitatively explaining the observed features is proposed.     

Study of single- and dual-channel designs for high-performance strained-Si-SiGe n-MOSFETs

Results comparing strained-Si-SiGe n-channel MOSFET performance of single-and dual-surface channel devices fabricated using 15% Ge content SiGe virtual substrates are presented. Device fabrication used high thermal budget processes and virtual substrates were not polished. Mobility enhancement factors exceeding 1.6 are demonstrated for both single-and dual-channel device architectures compared with bulk-Si control devices. Single-channel devices exhibit improved gate oxide quality, and larger mobility enhancements, at higher vertical effective fields compared with the dual-channel strain-compensated devices. The compromised performance enhancements of the dual-channel devices are attributed to greater interface roughness and increased Ge diffusion resulting from the Si/sub 0.7/Ge/sub 0.3/ buried channel layer.     

Si1-xGex/Si应变材料的生长及热稳定性研究

利用分子束外延（MBE）技术生长了Ge组份为0.1-0.46的Si1-xGex外延层。X射线衍射线测试表明，SiGe/Si异质结材料具有良好的结晶质量和陡峭界面，其它参数与可准确控制。通过X射线双晶衍射摆曲线方法，研究了经700℃、800℃和900℃退火后应变SiGe/Si异质结材料的热稳定性。结果表明，随着退火温度的提高，应变层垂直应变逐渐减小，并发生了应变弛豫，导致晶体质量退化；且Ge组分越小，Si1-xGex应变结构的热稳定性越好；室温下长时间存放的应变材料性能稳定。     

Ultrathin body SiGe-on-insulator pMOSFETs with high-mobility SiGe surface channels

A novel concept and a fabrication technique of strained SiGe-on-insulator (SGOI) pMOSFET are proposed and demonstrated. This device has an ultrathin strained SiGe channel layer, which is directly sandwiched by gate oxide and buried oxide layers. The mobility enhancement of 2.3 times higher than the universal mobility of conventional universal Si pMOSFETs was obtained for a pMOSFET with 19-nm-thick Si/sub 0.58/Ge/sub 0.42/ channel layer, which is formed by high-temperature oxidation of a Si/sub 0.9/Ge/sub 0.1/ layer grown on a Si-on-insulator (SOI) substrate. A fully depleted SGOI MOSFET with this simple single-layer body structure is promising for scaled SOI p-MOSFET with high current drive.