Valence Band Offset Measurements on Thin Silicon-on-Insulator MOSFETs

The effect of quantum confinement in thin silicon-on-insulator double-gate MOSFETs has been directly determined from subthreshold current measurements for the first time. By comparing temperature-dependent subthreshold characteristics of p-type devices with different silicon layer thicknesses, the offset in the valence band edge induced by spatial carrier confinement in these very thin silicon layers was measured electrically. Changes in the band structure are important for future CMOS devices such as FinFETs.     

Evaluation of lateral diffusion factor in silicon from subthresholdcurrent in short-channel vertical SIT test structure

A measurement method for the evaluation of the lateral diffusion factor of deep implanted regions in lightly doped material is proposed. The method is based on measurements of the subthreshold current versus drain voltage in vertical static induction transistor (SIT) devices. The subthreshold current is very sensitive to SIT channel width and hence to lateral diffusion of the gate regions, as shown by two-dimensional numerical analysis. Experimental results obtained for test structures fabricated with different boron doses and the same drive-in treatment indicate a lateral diffusion factor of 64% for a typical drive-in process     

A calibrated model for the subthreshold operation of a short channel MOSFET including surface states

Describes a simple two-dimensional subthreshold model for short channel MOSFET's. The effects of surface state density are also included in the model. A regional charge density approximation was used in the solution of Poisson's equation and an analytical solution of the continuity equation in two dimensions was derived. Excessive computations are avoided in the present model; this was made possible by the use of a valid regional charge approximation. The model was experimentally verified by performing measurements on short channel devices. The model was calibrated from measurements on a long channel device which was present on the same silicon chip. Results are presented for the subthreshold leakage current as a function of substrate bias, polysilicon gate length, diffusion depth and surface state density.     

Double gate-MOSFET subthreshold circuit for ultralow power applications

In this paper, we propose MOSFETs that are suitable for subthreshold digital circuit operations. The MOSFET subthreshold circuit would use subthreshold leakage current as the operating current to achieve ultralow power consumption when speed is not of utmost importance. We derive the theoretical limit of delay and energy consumption in MOSFET subthreshold circuit, and show that devices that have an ideal subthreshold slope are optimal for subthreshold operations due to the smaller gate capacitance, as well as the higher current. The analysis suggests that a double gate (DG)-MOSFET is promising for subthreshold operations due to its near-ideal subthreshold slope. The results of our investigation into the optimal device characteristics for DG-MOSFET subthreshold operation show that devices with longer channel length (compared to minimum gate length) can be used for robust subthreshold operation without any loss of performance. In addition, it is shown that the source and drain structure of DG-MOSFET can be simplified for subthreshold operations since source and drain need not be raised to reduce the parasitic resistance.     

Analytical modeling of the subthreshold current in short-channel MOSFET's

In this paper an analytical model for subthreshold current for both long-channel and short-channel MOSFET's is presented. The analytical electrostatic potential derived from the explicit solution of a two-dimensional Poisson's equation in the depletion region under the gate for uniform doping is used. The case for nonuniform doping can easily be incorporated and will be published later. The results are compared to a numerical solution obtained by using MINIMOS, for similar device structures. An analytical expression for the channel current is obtained as a function of drain, gate, substrate voltages, and device parameters for devices in the subthreshold region. The short-channel current equation reduces to the classical long-channel equation as the channel length increases.     

Analysis of the subthreshold current of pocket or halo-implanted nMOSFETs

In this work, we analyzed the subthreshold current (I/sub D/) of pocket implanted MOSFETs using extensive device simulations and experimental data. We present an analytical model for the subthreshold current applicable for any type of FET and show that the subthreshold current of nMOSFETs, which is mainly due to diffusion, is determined by the internal two-dimensional hole distribution across the device. This hole distribution is affected by the electric potential of the gate and the doping concentration in the channel. The results obtained allow accurate modelling of the subthreshold current of future generation MOS devices.     

Full-chip subthreshold leakage power prediction and reduction techniques for sub-0.18-/spl mu/m CMOS

The driving force for the semiconductor industry growth has been the elegant scaling nature of CMOS technology. In future CMOS technology generations, supply and threshold voltages will have to continually scale to sustain performance increase, control switching power dissipation, and maintain reliability. These continual scaling requirements on supply and threshold voltages pose several technology and circuit design challenges. With threshold voltage scaling, subthreshold leakage power is expected to become a significant portion of the total power in future CMOS systems. Therefore, it becomes crucial to predict and reduce subthreshold leakage power of such systems. In the first part of this paper, we present a subthreshold leakage power prediction model that takes into account within-die threshold voltage variation. Statistical measurements of 32-bit microprocessors in 0.18-/spl mu/m CMOS confirm that the mean error of the model is 4%. In the second part of this paper, we present the use of stacked devices to reduce system subthreshold leakage power without reducing system performance. A model to predict the scaling nature of this stack effect and verification of the model through statistical device measurements in 0.18-/spl mu/m and 0.13-/spl mu/m are presented. Measurements also demonstrate reduction in threshold voltage variation for stacked devices compared to nonstack devices. Comparison of the stack effect to the use of high threshold voltage or longer channel length devices for subthreshold leakage reduction is also discussed.     

Influence of polysilicon-gate depletion on the subthreshold behavior of submicron MOSFETs

Ion implantation, followed by annealing process, often leads to nonuniform doping and considerable depletion effect in the polysilicon gate of submicron MOS devices. Such an effect can alter notably the subthreshold characteristics and invalidate the conventional subthreshold current model. This paper studies the polysilicon-gate depletion effects on the subthreshold behavior based on results obtained from two-dimensional device simulation. An empirical expression is also suggested to describe the subthreshold current including the depletion effect.     

Pentacene-based organic thin-film transistors

Organic thin-film transistors using the fused-ring polycyclic aromatic hydrocarbon pentacene as the active electronic material have shown mobility as large as 0.7 cm²/V-s and on/off current ratio larger than 10⁸; both values are comparable to hydrogenated amorphous silicon devices. On the other hand, these and most other organic TFT's have an undesirably large subthreshold slope. We show here that the large subthreshold slope typically observed is not an intrinsic property of the organic semiconducting material and that devices with subthreshold slope similar to amorphous silicon devices are possible     

Analysis of bias stress on unpassivated hydrogenated amorphoussilicon thin-film transistors

Both the subthreshold slope and the threshold voltage in inverted-staggered amorphous silicon thin-film transistors (a-Si:H TFTs) are vulnerable to metastable changes in the density of states (DOS) due to Fermi level displacement. In previous work, we have used passivated and unpassivated TFTs to distinguish between the effects of bulk states and interface states at the top passivating nitride interface. Here we report the results of experimental measurements and two-dimensional (2-D) simulations on unpassivated TFTs. Since there are no top interface states, all the observed changes are due solely to the bulk DOS. The subthreshold current activation energies in a-Si:H TFTs are compared for n-channel nonpassivated TFTs before and after bias stress. The experimental results agree well with the 2-D simulations, confirming that the dependence of subthreshold current activation energy on gate bias reveals the distribution of the DOS in energy but cannot resolve the magnitude of features in the DOS. This type of analysis is not accurate for TFTs with a top passivating nitride, since the activation energies in such devices are affected by the interfere states     

Hot-carrier reliability in double-implanted lightly doped drain devices for advanced DRAMs

Hot-electron degradation in short-channel (0.50 mu m and 0.83 mu m) double-implanted lightly doped drain (DI-LDD) devices was characterised using DC stress tests. Compared to lightly doped drain (LDD) devices of the same effective channel length L/sub eff/, the measurements indicate that channel hot-electron injection is more prevalent in devices with the p/sup +/-pocket implant due to a higher peak channel electric field. Degradation is more severe in both the drain current and transconductance. However, an improvement in short-channel effects was seen in DI-LDD devices over LDD devices. For the same L/sub eff/, the punch-through voltage was higher and the subthreshold swing lower for the DI-LDD devices.<>     

Subthreshold slope in thin-film SOI MOSFETs

The subthreshold conduction regime in thick- and thin-film SOI MOSFETs is studied. Using the depletion approximation, a one-dimensional analytical expression for the subthreshold slope is derived, and equivalence with a simple capacitive network is proven. The model accounts for the influence of the back interface properties on the subthreshold swing in the thin-film regime. The coupling between front and back surface potential and the influence of the backside conduction on the front interface characteristics are accounted for. The case of double gate control is studied in more detail. Experimental verification of the model with measured subthreshold slopes in thin-form MOSFET devices is given     

On the transient operation of partially depleted SOI NMOSFET's

The transient operation of partially depleted (PD) Silicon-On-Insulator (SOI) NMOSFET's is investigated, based on two-dimensional numerical simulations. The studied devices have a gate length of 0.2 μm and a floating body. They are designed for a supply voltage of 2 V. In the case of gate transient, we show that the body voltage is more influenced by the capacitive coupling with the gate electrode than the impact ionization current. Further, we demonstrate, for the first time, that the anomalous subthreshold slope, that exists in a DC static transfer I-V curve, does not exist in fast transient mode because the minimum time constant for body charging by impact ionization current is on the order of 3 ns in such devices     

Modeling and experimental simulation of the low-frequency transfer inefficiency in bucket-brigade devices

The work presented in this paper extends the available theory and it also presents a model for the low-frequency charge transfer in MOS bucket-brigade devices (BBD's). Our new theory which characterizes the low-frequency component of transfer inefficiency in terms of the subthreshold current is frequency independent and it incorporates both channel-length and barrier-height modulations. This model was verified experimentally on simulated BBD's. After proving both theoretically and experimentally that the low-frequency transfer inefficiency of BBD devices is due to subthreshold current, we successfully used this knowledge to design an improved BBD device. This improved device includes only one extra ion-implantation step relative to the original BBD device. An ion implant is used in part of the BBD channel.     

边缘注入对H型栅SOI pMOSFETs亚阈值泄漏电流的影响

就不同边缘注入剂量对H型栅SOI pMOSFETs亚阈值泄漏电流的影响进行了研究。实验结果表明不足的边缘注入将会产生边缘背栅寄生晶体管,并且在高的背栅压下会产生明显的泄漏电流。分析表明尽管H型栅结构的器件在源和漏之间没有直接的边缘泄漏通路,但是在有源扩展区部分,由于LOCOS技术引起的硅膜减薄和剂量损失仍就促使了边缘背栅阈值电压的降低。     

An analytical two-dimensional model for silicon MESFETs

A model that predicts small-geometry effects in Si MESFETs has been developed. It is based on a two-dimensional (2-D) analytical solution of Poisson's equation in the subthreshold regime that applies to the junction-isolated structure typical of silicon devices. The model is in excellent agreement with numerical simulations from the PISCES 2-D device analysis program. The analytical model provides the physical basis for a subthreshold current model for small-geometry MESFETs. A scaling scheme for MESFETs, derived from the analytical model, that predicts a minimum-acceptable gate length of 0.15 μm for these devices is proposed     

Subthreshold surface potential and drain current models for short-channel pocket-implanted MOSFETs

An analytical subthreshold surface potential model for short-channel pocket-implanted (double-halo) MOSFET is presented. The effect of the depletion layers around the source and drain junctions on channel depletion layer depth, which is very important for short-channel devices, is included. Using this surface potential, a drift-diffusion based analytical subthreshold drain current model for short-channel pocket-implanted MOSFETs is also proposed. A physically-based empirical modification of the channel conduction layer thickness that was originally proposed for relatively long-channel conventional device is made for such short-channel double-halo devices. Very good agreement for both the surface potential and drain current is observed between the model calculation and the prediction made by the 2-D numerical device simulation using Dessis.     

Accurate Array-Based Measurement for Subthreshold-Current of MOS Transistors

A MOS transistor-array structure for accurate subthreshold current characterization is presented. Two architectural improvements called LCS and PES, and measured data treatment called MCC are utilized. The LCS, leakage current cut-off switch, reduces unwanted leakage current of the non-target devices which masks the target leakage current. The PES, potential equalizing supply, further reduces the masking current by setting source and drain terminals of the LCS equal. The MCC, masking current cancellation, improves measurement accuracy by subtracting remaining masking current. The proposed circuit structure and the procedure virtually eliminate usual constraint on the number of transistors that can be present in an array. The array structure also offers greater flexibility in choosing a row-column aspect ratio and allows different types of MOS transistors to be interweaved. Experimental array design consisting of 1023 low threshold voltage devices demonstrated accurate measurement of subthreshold leakage current with precision of a few picoamperes.      

Quantum-mechanical effects in nanometer scale MuGFETs

Solving the Poisson and Schrödinger equations self-consistently in two dimensions reveals quantum-mechanical effects that influence the electron concentration, the threshold voltage and the subthreshold slope of MuGFETs. The average electron concentration needed to reach the threshold voltage depends on the gate configuration and on the device geometry. The dependence of the energy of the subbands on the different gate configurations is studied, and the relation between threshold voltage and the lowest subband energy is investigated. Due to a dynamic threshold voltage effect, the drain current is lower in the quantum-based drain current model than in classical simulations. This dynamic increase of threshold voltage is due to an increase of the subband energy with the electron concentration. This effect degrades the subthreshold slope. It is observed in non-symmetrical devices (FinFET, tri-gate), but not in symmetrical structures (GAA). This gives symmetrical devices like GAA nanowires an intrinsic advantage compared to the other types of devices.     

Stacked pentacene layer organic thin-film transistors with improvedcharacteristics

Using two layers of pentacene deposited at different substrate temperatures as the active material, we have fabricated photolithographically defined organic thin-film transistors (OTFTs) with improved field-effect mobility and subthreshold slope. These devices use photolithographically defined gold source and drain electrodes and octadecyltrichlorosilane-treated silicon dioxide gate dielectric. The devices have field-effect mobility as large as 1.5 cm²/V-s, on/off current ratio larger than 10⁸, near zero threshold voltage, and subthreshold slope less than 1.6 V per decade. To our knowledge, this is the largest field-effect mobility and smallest subthreshold slope yet reported for any organic transistor, and the first time both of these important characteristics have been obtained for a single device