Observation of electron velocity overshoot in sub-100-nm-channel MOSFET's in Silicon

n-channel MOSFET's with channel lengths from 75 nm to 5 µm were fabricated in Si using combined X-ray and optical lithographies, and were characterized at 300, 77, and 4.2 K. Average channel electron velocities υewere extracted according to the equationupsilon_{e}=g_{mi}/C_{ox}, where gmiis the intrinsic transconductance and Coxis the capacitance of the gate oxide. We found that at 4.2 K the average electron velocity of a 75-nm-channel MOSFET is 1.7 × 10⁷cm/s, which is 1.8 times higher than the inversion layer saturation velocity reported in the literature, and 1.3 times higher than the saturation velocity in bulk Si at 4.2 K. As channel length increases, the average electron velocity drops sharply below the saturation velocity in bulk Si. These experimental results strongly suggest velocity overshoot in a 75-nm-channel MOSFET.     

Current equations for velocity overshoot

A generalized current equation is presented for the operation of submicron devices by supplementing the drift and diffusion currents with gradient, rate and relaxation currents. The equation includes the most important features of velocity overshoot.     

Gate-field-induced carrier heating in Si MOSFET's

We have used Si MOSFET's to study the variation of the channel Hall mobility and noise temperature with the gate voltage. From the Hall mobility measurements, a new empirical expression is found to describe the mobility degradation with gate voltage over a wide range of transverse electric field. By measuring the thermal noise, it is found that the channel carriers appear to be heated by the gate electric field and that the excess noise temperature varies quadratically with gate field.     

Drain current enhancement due to velocity overshoot effects and itsanalytic modeling

The drain current enhancement due to the velocity overshoot effects is found to be due to the electron velocity enhancement at the source end. Based on this observation, a new analytic model is proposed and verified by two-dimensional (2-D) simulations and experiments. From the results of the verifications, we conclude that our model predicts the drain current enhancement due to the velocity overshoot effects reasonably well. The effects of the device parameters, such as gate oxide thickness and channel doping concentration, on the drain current enhancement ran be readily found in our model     

High field hole velocity and velocity overshoot in siliconinversion layers

We report measurements of the drift velocity of holes in silicon inversion layers. The saturation velocity of holes at 300 K is found to be strongly dependent on the effective vertical field. No hole velocity overshoot was observed down to 0.16 μm channel length at room temperature. At 77 K, hole velocity saturation is much less pronounced, and a 10% higher average velocity is observed for 0.16 μm channel length as compared to 0.36 μm channel length     

Observation of velocity overshoot in silicon inversion layers

Employing a test structure, velocity overshoot in silicon inversion layers is observed at room temperature. For channel lengths longer than 0.3 μm, the velocity/field relation follows the well-known behavior with no channel length dependence. The first indication of velocity overshoot is seen at a channel length of 0.22 μm, while at L=0.12 μm, drift velocities up to 35% larger than the long-channel value are measured     

Implications of velocity overshoot in heterojunction transit-time diodes

The influence of transient transport in heterojunction transittime is discussed. It is argued that overshoot effects can be important in such devices, in which case the presence of the overshoot will significantly impact device design. Appropriately designed structures are predicted to be superior to their homojunction counterparts, particularly at millimetre wavelengths.     

An investigation of steady-state velocity overshoot in silicon

Electron dynamics in silicon is investigated by means of improved momentum- and energy-balance equations including particle diffusion and heat flux. The resulting system of partial differential equations is numerically solved in a variety of field configurations including strong discontinuities, in order to enhance velocity overshoot effects. It is found that diffusion, usually neglected in previous studies, plays a major role, and considerably modifies the features of the velocity vs distance curve, leading to an increase of the carrier drift velocity in the low-field region, i.e. before experiencing the effect of the strong field. In addition, it is found that, in order to take full advantage of velocity overshoot effects in MOSFET's, a structure must be designed having the strongest possible field at the source-end of the channel, where carrier density is controlled by the gate.     

Verification of saturation velocity lowering in MOSFET's inversionlayer

With reduction of the MOSFET's channel length L, the drain saturation current of MOSFET's is determined by the saturation velocity v_sat in the inversion layer. Hence, the modeling of v_sat becomes very important. In this paper, v_sat in the inversion layer has been examined by using simulation experiment. New parameter values for v_sat model in the inversion layer are proposed. In order to verify the v_sat model, the impurity profiles of MOSFET's are calibrated to fit the threshold voltage V_th-L characteristics. Then, we validate new v_sat model by comparing the experiments of I_D-V_D characteristics of 0.35-μm CMOS with the simulations using the energy transport model (ETM)     

Short-channel effects in MOSFET's

In this letter we present electrical measurements of threshold voltage on matched transistor pairs which show a channel shortening effect due to the presence of dislocations or metallic precipitates in the device. Such effects could present a limitation on the yield and performance of MOS integrated circuits employing short-channel devices.     

Collector signal delay in the presence of velocity overshoot

It is pointed out that the well-known expression equating the collector signal delay to one-half of the transit time through the base-collector depletion region is incorrect in the presence of a nonconstant carrier velocity, as occurs in the case of velocity overshoot. The correct expression yields a smaller signal delay than the conventional estimate for typical situations, further emphasizing the benefit of velocity overshoot in bipolar devices     

Numerical simulation of GaAs MESFETS including velocity overshoot

An effective procedure considering the velocity overshoot effect in numerical simulation of GaAs MESFETs is presented. The results of the corresponding routine SEMICO II are compared with results of Monte-Carlo simulations and with results of the routine SEMICO I without overshoot.Implanted MESFETs have been simulated with and without including the overshoot effect, and from these data equivalent circuits have been derived. From circuit calculations of E/D inverter ring oscillators it is concluded that the velocity overshoot effect leads to a twofold decrease of the gate propagation delay time for 0.25 μm gate length.     

Miniaturization of Si MOSFET's at 77 K

Micrometer and submicrometer dimension Si MOSFET's have been studied at liquid nitrogen temperature. The emphasis of the study has been on the changes in the minimum channel length required for long-channel behavior Lmindue to cooling. It is found that there is a reduction in Lminwhich is quite considerable in MOSFET's with low-channel doping. We have shown that this effect is due to a shorter lateral depletion width, and therefore longer effective channel length at low temperatures. A drastic decrease in punchthrough current has also been observed.     

Two-dimensional analytical modeling of threshold voltages of short-channel MOSFET's

We present an analytical model of the threshold voltage of a short-channel MOSFET based on an explicit solution of two-dimensional Poisson's equation in the depletion region under the gate. This model predicts an exponential dependence on channel length (L), a linear dependence on drain voltage (VD), and an inverse dependence on oxide capacitance (εox/tox). An attractive feature of this model is that it provides an analytical closed-form expression for the threshold voltage as a function of material and device parameters (tox, VD, L, substrate bias, and substrate doping concentration) without making premature approximations. Also, this expression reduces to the corresponding expression for long-channel devices.     

Single electron switching events in nanometer-scale Si MOSFET's

High-resolution ac measurements of drain conductance at low temperatures have been made on silicon MOSFET's with channels as narrow as 0.1 µm. These devices show discrete switching events in the channel resistance associated with individual electrons being captured and emitted from single interface traps. The voltage and temperature dependence of this switching gives detailed information on the characteristics of the trap and its distance from the interface. This switching is a component of low-frequency noise in MOSFET's and may be an important limit to the performance of small transistors.     

Ballistic transport and velocity overshoot in semiconductors: Part I—Uniform field effects

The relationship between ballistic electron transport and velocity overshoot, in semiconductor materials, is clarified. By considering the behavior of electrons in a uniform electric field, we show that while ballistic transport can coexist with velocity overshoot, it is not necessary for overshoot. Furthermore, we show that ballistic transport will not lead to overshoot unless one of the two classic mechanisms for overshoot is also operative.     

Edge effects in narrow-width MOSFET's

New results on edge effects in narrow-width MOSFETs as a function of the gate bias are presented. It was found that the value of the effective channel width, the current through the edge region, and the absolute value of the parasitic parallel conductance all increased with gate bias. These parameters were extracted from the experimental measurements by new techniques, which are described     

1.5 nm direct-tunneling gate oxide Si MOSFET's

In this paper, normal operation of a MOSFET with an ultra-thin direct-tunneling gate oxide is reported for the first time. These high current drive n-MOSFET's were fabricated with a 1.5 nm direct-tunneling gate oxide. They operate well at gate lengths of around 0.1 μm, because the gate leakage current falls in proportional to the gate length, while the drain current increases in inverse proportion. A current drive of more than 1.0 mA/μm and a transconductance of more than 1,000 mS/mm were obtained at a gate length of 0.09 μm at room temperature. These are the highest values ever obtained with Si MOSFET's at room temperature. Further, hot-carrier reliability is shown to improve as the thickness of the gate oxide is reduced, even in the 1.5 nm case. This work clarifies that excellent performance-a transconductance of over 1,000 mS/mm at room temperature-can be obtained with Si MOSFET's if a high-capacitance gate insulator is used     

High-field transport of inversion-layer electrons and holesincluding velocity overshoot

In this paper, we experimentally address the effect of a wide range of parameters on the high-field transport of inversion-layer electrons and holes. The studied parameters include substrate doping level, surface micro-roughness, vertical field strength, nitridation of the gate oxide, and device channel length. We employ special test structures built on Silicon-On-Insulator (SOI) and bulk wafers to accurately measure the high-field drift velocity of inversion-layer carriers. Our findings point to electron velocity overshoot at room temperature, dependence of electron and hole saturation velocities on nitridation of the gate oxide, dependence of the high-field drift velocity on the effective vertical field, and relative insensitivity of electron and hole mobility and saturation velocity to moderate surface roughness     

Monolithic integration of Si MOSFET's and GaAs MESFET's

Integration of Si MOSFET's and GaAs MESFET's on a monolithic GaAs/Si (MGS) substrate has been demonstrated. The GaAs MESFET's have transconductance of 150 mS/mm for a gate length of 1 µm, and the Si MOSFET's have transconductance of 19 mS/mm for a gate length of 5 µm and an oxide thickness of 800 Å. These characteristics are comparable to those for devices fabricated on separate GaAs and Si substrates.