Dependence of the work-function difference between the polysilicon gate and silicon substrate on the doping level in polysilicon

We correlate the work-function difference φps⁰between the polysilicon gate and the silicon substrate in an MOS system with the doping level and carrier concentration in polysilicon. Polysilicon was doped by ion implantation with arsenic and phosphorus. The doping level was varied from 10¹⁹to 10²⁰cm^-3. Hall measurements were used to determine the carrier concentration in polysilicon at a given doping level. The Hall mobility and resistivity as a function of doping level were also obtained. The work function difference φps⁰was determined by capacitance-voltage measurements on polysilicon-SiO2-Si capacitors with different oxide thicknesses. When plotted against the doping level, the work-function difference had a maximum at a dopant concentration of ≈ 5 × 10¹⁹cm^-3, which corresponds to an electron concentration of 1.5 × 10¹⁹cm^-3. At higher doping levels the value of φps⁰decreases. The results can not be fully understood in terms of the Si band structure.     

Heavy doping effects in p-n-p bipolar transistors

This paper presents the heavy doping effects on the injection current characteristics in p-n-p transistors with a heavily doped but thin base region. The results of the present study indicate that 1) at room temperature the hole current injected into heavily doped base is insensitive to the impurity compensation effect, 2) a linear relationship between the base sheet resistance and the collector-current density is observed when the base doping density is under 1 × 10¹⁹cm^-3. This relationship becomes supralinear as the doping density further increases. As a result, useful current gain exists in thin base transistors even when the base doping is greater than 1 × 10¹⁹cm^-3. From the collector-current-base sheet-resistance relationship and the base doping profile, the effective intrinsic carrier density as a function of the doping density is evaluated and found to increase 8.7 times over that of pure silicon, when the average doping density is 5 × 10¹⁹cm^-3(maximum doping density 1 × 10²⁰cm^-3). 3) The collector current and the current gain of the transistors become less sensitive to the temperature as the base doping density increases. We had observed a current gain up to 30 at 77 K for transistors with the maximum base doping density in the 10¹⁸cm^-3range. The transistors with lower base doping suffer much more degradation in current gain when the temperature is lowered to 77 K.     

Counting of deep-level traps using a charge-coupled device

Quantization in dark current generation has been observed for the first time through the use of a virtual-phase charge-coupled device. Two sites for bulk silicon dark current have been identified with capture cross sections of 1.8 × 10^-15cm²and 5.4 × 10^-16cm², and concentrations of 1.3 × 10⁹cm^-3and 1.5 × 10⁸cm^-3, respectively.     

Effect of doping profile variations on the performance of the permeable base transistor

The cutoff frequency ftand maximum frequency of oscillation fmaxof the permeable-base transistor have been calculated for devices with a fixed geometry and different doping profiles to determine the profile that gave the highest value off_{max}The effect of different static velocity-field curves for GaAs and InP, and associated diffusion-field dependencies on device performance have also been examined. The results of the simulations show that the saturated velocity for GaAs PBT's has a major impact on performance. The uniformly doped device, Ndof 4 × 10¹⁶cm^-3, has a higherf_{max}when the saturated velocity is larger, but the effect of the low field mobility is small. The InP device has a slightly higherf_{max}than the corresponding GaAs devices at this doping level. The 20-10-4 × 10¹⁶cm^-3devices have the highestf_{max}of all the GaAs devices investigated.     

Leakage current characteristics of offset-gate-structure polycrystalline-Silicon MOSFET's

Leakage current characteristics of offset-gate-structure polycrystalline-silicon (poly-Si) MOSFET's are studied as a function of dopant concentration Noffin offset-gate regions. Leakage current markedly decreases from 1 × 10^-9to 2 × 10^-11A at VD= 10 V as Noffis varied from 1 × 10¹⁸to 1 × 10¹⁷cm^-3. A maximum ON/OFF current ratio of 10⁸is obtained at 1 × 10¹⁷cm^-3. Calculations based on a quasi-two-dimensional model indicate that the reduction of leakage current is attributable to a decrease of the maximum lateral electric field strength in the drain depletion region. An analysis of the leakage current characteristics in terms of carrier emission from grain-boundary traps implies that thermonic emission accompanied by thermally assisted tunneling could be the dominant mechanism in determining leakage current.     

Incoherent annealing of implanted layers in GaAs

Incoherent light from filament lamps focused by elliptical mirrors has been used to activate implanted layers in GaAs. 4 × 10¹⁴Si⁺cm^-2and 2 × 10¹⁴Zn⁺cm^-2implants were annealed with Si3N4deposited by CVD at 400°C providing a surface protective layer. By taking advantage of the focusing properties of elliptical mirrors, most of the emitted light could be concentrated onto the GaAs to give annealing times × 1 sec. Differential Hall measurements show peak carrier concentrations of 6.5 × 10¹⁸cm^-3and 50% activation for the n+ layers. The Zn implants were completely activated and doped to ∼ 2 × 10¹⁹cm^-3. These results, together with the short annealing times, suggest the present approach to be an attractive alternative to both laser and conventional thermal annealing.     

Measurement of heavy doping parameters in silicon by electron-beam-induced current

Limits on the magnitude of bandgap narrowing and Auger recombination in heavily phosphorus-diffused silicon layers ∼ 10²⁰cm^-3have been measured by electron-beam-induced current. It is determined that the slope of the bandgap narrowing versus doping must be nearly zero above 3 × 10¹⁹cm^-3to be consistent with previous data at lower doping levels. It is also shown that the low-level minority-carrier lifetime in these layers is consistent only with an Auger recombination coefficientC_{N} < 0.4 times 10^{-31}cm⁶/s.     

Low-resistance ohmic contacts to p-type GaAs using Zn/Pd/Au metallization

We have fabricated the low resistance ohmic contacts to p-type GaAs. Specific contact resistances as low as 7 × 10^-7Ω.cm²have been obtained for contacts prepared by heat treating Zn/Pd/Au metallizations deposited on p-type epitaxial GaAs layers with an acceptor concentration of 1.5 × 10¹⁹cm^-3. These contacts are reproducible, simple to fabricate, exhibit excellent adhesion, and have a uniformly smooth surface morphology.     

Optical microprobe response of GaAs diodes

GaAs p-n junction photocurrent response is obtained from an optical microprobe with a dynamic range of at least three decades and a light-spot diameter of about 1.3 µm. The results are found to correlate well with the appropriate theoretical response which includes surface recombination and assumed infinite absorption coefficient. Minority-carrier diffusion lengths computed from the data are typically 3.5 and 0.7 µm for holes in n-type material doped 10¹⁷and 1.4×10¹⁸cm^-3and 1 µm for electrons in >10¹⁸cm^-3doped p-type material. Estimates of carrier lifetimes are made and the deviation of surface recombination velocity between devices is demonstrated.     

Switching and memory effects in amorphous chalcogenide thin films

The performance of threshold- and memory-switching devices is discussed. The threshold devices were prepared by vacuum deposition from the Ge-As-Te-Si system and exhibited threshold voltages over a wide range from less than 2.0 V to greater than 50 V. Lifetimes of the order of 10⁶-10⁸switching operations before failure were obtained and the operation of the threshold device with a capacitative load was demonstrated. Memory-switching devices were prepared from the Ge-As-Te system. The bistable operation is discussed and it is concluded that the bistable impedance states are due to the presence, or absence, of a crystalline filament between the electrodes. Typical pulse levels required to produce the transition between the impedance states were 2 × 10^-2A for 5 × 10^-3s and 5 × 10^-2A for 5 × 10^-6s. The devices possess fairly stable characteristics and currently have lifetimes of 10²- 10³operations before failure; this is expected to improve with device development.     

GaAs LSA V-band oscillators

GaAs devices verify practical LSA mode operation at V-band frequencies (50-75 GHz). The limitations on power and efficiency are characterized including the dependence of efficiency on electron concentration. The maximum CW power level is 62 mW with an efficiency of 2.2 percent at 64 GHz. The peak power and efficiency is 137 mW and 3.71 percent at 64 GHz for 5 percent duty, pulsed operation. A maximum in the CW efficiency occurs at an n/f ratio of 1.1 × 10⁵s . cm^-3corresponding to a doping of 6.6 × 10¹⁵cm^-3for a frequency of 60 GHz. Device design curves are presented for CW operation subject to Copeland's LSA mode criteria and to a maximum allowed sample temperature rise. Details of a vane circuit are presented which provide V-band resonances and a proper RF environment for LSA-related operation.     

High efficiency CW transferred-electron oscillator with optimized doping profile

This study is aimed at helping to design X-band CW transferred-electron oscillators with higher performance. Temperature rise in devices operating in the accumulation layer mode is analyzed both with heat sink negative and heat sink positive. Efficiencies and output powers in both polarities are calculated and compared. The calculation shows efficiency in CW operation is drastically improved by quantitatively controlling the doping profile to account for the temperature profile and further governed by carrier concentration times layer thickness (n × l) product and diode size. For the heat sink negative, output power over 800 mW is predicted from a single-mesa conventional structure, using a wafer with an n × l product of 2.0 × 10¹²cm^-2and doping profile increasing, toward the substrate (away from the heat sink), by 30-35 percent across the active layer. For the heat sink positive, an almost flat profile is suitable and output power over 1.5 W is predicted for a diode with a doping increase of 10 percent across the active layer toward the substrate. The calculations are substantiated experimentally by diodes with n × l products of 1.5-2.3 × 10¹²cm^-2and doping increases of 20-70 percent across the active layer toward the substrate heat sink negative operation.     

Transit time and charge storage measurements in heavily doped emitters

We report results of a first direct measurement of the minority-carrier transit time in a transparent heavily doped emitter layer. The value was obtained by a high-frequency conductance method recently developed and used for low-doped Si. The transit time coupled with the steady-state current enables the determination of the quasi-static charge stored in the emitter and the quasi-static emitter capacitance. Using a transport model, we estimated, from the measured transit time, the value for the minority-carrier diffusion coefficient and mobility. The measurements were done using a heavily doped emitter of the Si p+-n-p bipolar transistor. The new result indicates that the position-averaged minority-carrier diffusion coefficients may be much smaller than the corresponding majority-carrier values for emitters having a concentration ranging from about 3 × 10¹⁹cm^-3to 10²⁰cm^-3.     

A method for determining energy gap narrowing in highly doped semiconductors

A general experimental method for the determination of the phenomenological energy gap narrowingDeltaE_{G}in regions of semiconductor devices that have high concentrations of donor or acceptor impurity atoms is presented. The theoretical grounds for the method are discussed in detail, including the strong influence of Fermi-Dirac statistics on minority-carrier recombination in heavily doped regions. The method requires measurements only of the temperature dependence of de current; therefore it is very accurate. The values ofDeltaE_{G}deduced from the method are insensitive to the mechanisms controlling recombination and to the value of minority-carrier mobility in the heavily doped region; they are also independent of the value of nithe intrinsic carrier density, at a specific temperature. The values for the Si:As emitters of transistors and diodes were measured in the majority-carrier concentration range from 4 × 10¹⁸cm^-3to 2 × 10²⁰cm^-3.     

High infrared responsivity Indium-doped silicon detector material compensated by neutron transmutation

The use of the neutron transmutation for producing precisely compensated, extrinsic idium-doped, silicon detector material of high infrared responsivity is reported. Highly indium-doped silicon crystals containing (1 to 3) × 10¹⁷cm^-3indium concentrations and residual acceptors in the low 10¹²cm^-3have been grown by float-zone doping. The high purity obtained by this growth technique enables very low net donor compensation densities to be achieved by neutron irradiation in a reactor. Transmuted phosphorus concentrations ranging from (1 to 20) × 10¹²cm^-3have been investigated and compensation densities,N_{D} - N_{A}, as low as 2 × 10¹²cm^-3have been achieved in irradiated samples after suitable damage annealing. Residual radioactivity due to transmuted indium isotopes approaches negligibly low levels for the neutron fluences required with high purity float-zone Si:In material. Significant improvements in infrared detector performance have been demonstrated with neutron compensated indium-doped silicon. Peak responsivities up to 100 A/W at 50 K and 10³-V/cm detector bias have been measured, corresponding to dc photoconductive gains in the 30 to 40 range and mobility-lifetime products > 10^-3cm²/V. Additional studies indicate that the detector responsivity, which is adversely affected by high-temperature CCD fabrication processes, can be restored significantly by phosphorus gettering techniques.     

Optimum doping profile for minimum ohmic resistance and high-breakdown voltage

The optimum doping profile of a lightly doped layer that introduces the minimum series resistance and sustains a given junction breakdown voltage is derived. The theory applies to a one-dimensional Schottky diode and qualitatively to the collector or drain doping profiles of transistors. The minimum series resistance is found to be about 3.7 × 10^-9Vmin{B}max{2.6}Ω.cm²for an n silicon layer. The optimum doping profile can be closely approximated by a conventional uniformly doped n-n⁺structure.     

A study of the trench surface inversion problem in the trench CMOS technology

This paper presents the results obtained in the study of the trench surface inversion problem for the CMOS technology using trench isolation. Special emphasis is put on the n-well CMOS technology where the inversion problem is most severe. Potential distribution along the trench surface is simulated using the SUPREM and GEMINI programs for different bias conditions, as well as for different impurity doping profiles and fixed charge densities (Qss). The results showed that Qssalong the trench surface has to be maintained at 5 × 10¹⁰cm^-2if the substrate doping concentration remains at 6 × 10¹⁴cm^-3. Higher substrate doping, lower n-well bias, and more negative substrate bias will help prevent trench surface inversion. p-well CMOS is more suitable for trench isolation due to the higher doping concentration inside the p-well. Experimental data showed that trench isolation gives no improvement in latch-up susceptibility when the trench surface is inverted.     

Channeling depth distributions of Be and Si in GaAs as a function of implantation energy and fluence

Be and Si are commonly employed p- and n-type respectively dopants, implanted in GaAs. Channeled implantation produces deeper and sharper profiles than standard random implants. To employ channeling, we need to know how the profile shape, depth, and doping density vary with implantation energy and fluence, and what maximum density can be achieved. This work shows how channeling profiles in the direction of GaAs vary with energy and fluence for room temperature channeling. Data are shown for fluences of 3 × 10¹², 3 × 10¹³, and 3 × 10¹⁴cm^-2and energies of 40, 75, 150, and 300 keV. The deep channeling profile saturates for 150 keV Be just below a fluence of 3 × 10¹⁴cm^-2and a density of about 4 × 10¹⁷cm^-3can be achieved at depths of about 1 to 3 µm for energies from 75 to 300 keV. The maximum density for 150 keV Si for room temperature channeling is about 4 × 10¹⁶cm^-3and occurs at depths from 1 to 4 µm in the energy range from 40 to 300 keV.     

A new conduction model for polycrystalline silicon films

A new quantitative electrical model is introduced to solve earlier modeling inadequacies in polycrystalline silicon films. An analytical J-V expression is developed in normalized closed form, which includes the thermionic field emission through a space-charge potential barrier and through a grain-boundary scattering potential barrier and the thermionic emission over these barriers. The modeling validity has been verified experimentally for films with grain sizes of 230 to 1220 Å, doping concentrations from 1 × 10¹⁶to 8 × 10¹⁹cm^-3and over a temperature range from -176° to 144°C.     

The influence of bulk traps on the charge-transfer inefficiency of bulk charge-coupled devices

One of the possible causes of a finite charge-transfer inefficiency in bulk charge-coupled devices (BCCD's) is the presence of bulk traps in the n-type silicon layer through which the charge packets are transferred. To determine the relative importance of the contribution of traps, we measured charge transfer inefficiency as a function of temperature. In most of the devices investigated, this measurement results in two broad peaks due to the presence of traps at 0.25 and 0.54 eV below the conduction band edge. The concentration of these traps varied from batch to batch between values of 5 × 10¹⁰cm^-3and 1 × 10¹²cm^-3.