Design of wide-band optical heterodyne balanced mixer receivers

The optical heterodyne balanced mixer, or dual-detector receiver, offers significant advantages over a single detector receiver. Balanced mixer receivers are particularly attractive for use in optical heterodyne communication systems because they conserve local oscillator power and cancel excess intensity noise present in the local oscillator. Simple circuit models that illustrate the noise performance, small signal gain, and bandwidth of a balanced mixer receiver are developed. A figure-of-merit for receiver noise performance is also derived. An example design of a gigahertz bandwidth optical heterodyne balanced mixer receiver and the techniques used to characterize near-quantum-limited receiver performance are discussed.     

Monolithic balanced p-i-n/HBT photoreceiver for coherent optical heterodyne communications

Two InGaAs p-i-n photodetectors connected in a balanced configuration have been monolithically integrated with a transimpedance preamplifier made from InP-InGaAs heterojunction bipolar transistors (HBTs) to realize a balanced optoelectronic integrated circuit (OEIC) receiver. The receiver, with a bandwidth of 3 GHz and a common mode rejection of 25 dB, has a sensitivity of -49 dBm at a bit error rate of 10/sup 9/ under NRZ FSK reception at 200 Mb/s.<>     

Design of inductive p-i-n diode matching for optical receivers withincreased bit-rate operation

We have studied matching of a p-i-n photodiode (PD) with a single serial inductive element for broadband operation. The bit rate and rise time may be significantly improved, compared to a device without inductor for nonreturn-to-zero (NRZ) modulation. The matched device offers improved pulse equalization leading to increased receiver sensitivity, and reduces the need for an additional pulse-equalizing filter. The material is presented so that it can serve as a guideline of how the inductor can be included when choosing the thickness of the absorption layer and/or area for a p-i-n PD design, and ends with typical design examples     

Highly integrated InP HBT optical receivers

This paper presents two highly integrated receiver circuits fabricated in InP heterojunction bipolar transistor (HBT) technology operating at up to 2.5 and 7.5 Gb/s, respectively. The first IC is a generic digital receiver circuit with CMOS-compatible outputs. It integrates monolithically an automatic-gain-control amplifier, a digital clock and data recovery circuit, and a 1:8 demultiplexer, and consumes an extremely low 340 mW of power at 3.3 V, including output buffers. It can realize a full optical receiver when connected to a photo detector/preamplifier front end. The second circuit is a complete multirate optical receiver application-specific integrated circuit (ASIC) that integrates a photodiode, a transimpedance amplifier, a limiting amplifier, a digital clock and data recovery circuit, a 1:10 demultiplexer, and the asynchronous-transfer-mode-compatible word synchronization logic. It is the most functionally complex InP HBT optoelectronic integrated circuit reported to date. A custom package has also been developed for this ASIC     

Transit-time broad-banding of very high bandwidth monolithicp-i-n/HBT optical receivers

The authors show that phase shifts due to electron transit-times in the collector regions of heterojunction bipolar monolithic optical receivers lead to a widebanding of the frequency response or, at worst, circuit instability. Simple quantitative expressions are derived in order to analyze this effect. The dependence of widebanding on the open-loop transistor bias conditions is discussed     

Design considerations for p-i-n thyristor structures

An analysis of a high-voltage gate turn-off (GTO) thyristor structure with a double-layered n base (p-i-n structure) is presented. From integration of Poisson's equation, an expression for the forward-blocking voltage at the onset of avalanche breakdown is obtained. Simple design criteria are developed to calculate the optimal thickness and doping density of the n base of a conventional pnpn structure designed for a specific voltage-blocking capability. The same principle is applied to design for the doping densities and thicknesses of the high-resistivity region and the buffer layer of the p-i-n GTO structure. The forward-blocking voltage, as well as the on-state voltage (at a current density of 300 A cm^-2) is predicted for a wide range of base layer thicknesses and doping densities to illustrate the available tradeoff options. Lowest on-state power dissipation for high blocking voltages (>6000 V) is predicted for a doping level of 5×10¹² cm^-3 in the high-resistivity layer     

Optimization of the optical sensitivity of p-i-n FET receivers

The optimization of the input stage of a p-i-n FET receiver is discussed, with emphasis on the implications for an integrated InP/InGaAs p-i-n FET technology. In the early stages of development of this technology, it is necessary to keep the design simple, which implies that the device will consist of a single-stage, low-gain amplifier. Design criteria for such an amplifier are presented, and it is shown that the transimpedance configuration provides better sensitivity than a voltage amplifier, even when the gain of the amplifier is very small. It is also shown that the gate capacitance (i.e. width) of the input FET which optimizes the sensitivity is much smaller when the amplifier gain is low than it is in the high-gain limit     

锗硅HBT BiCMOS工艺中的p-i-n开关二极管设计

介绍了一种集成在BiCMOS工艺的p-i-n开关二极管的器件。它由在STI下面的n型赝埋层作为p-i-n的n区,锗硅npn异质结双极型晶体管的重掺杂外基区作为p-i-n的p区。同时新开发了穿过场氧的深接触孔工艺用于赝埋层的直接引出,并采用p-i-n注入用于对i区进行轻掺杂。借助半导体工艺与器件仿真软件,得到了有源区尺寸、赝埋层到有源区的距离、p-i-n注入条件等关键工艺参数对p-i-n性能的影响。最后优化设计的p-i-n二极管,其在2.4 GHz频率下的指标参数,如插入损耗为-0.56 dB,隔离度为-22.26 dB,击穿电压大于15 V,它达到了WiFi电路中的开关器件的性能要求。     

High-speed monolithic p-i-n/HBT and HPT/HBT photoreceiversimplemented with simple phototransistor structure

Monolithic photoreceivers, using the base-collector junction of an InP/InGaAs phototransistor structure for a p-i-n photodetector, have been fabricated for the first time. Bandwidths as high as 3 GHz and bit rates as high as 5 Gb/s, with sensitivities of -22.5 dBm and -21.5 dBm for light focused on the p-i-n or on the first stage transistor of the preamplifier, respectively, have been achieved. These results represent the highest operating speed demonstrated for any phototransistor-based receiver     

DC to 2.5 Gb/s×4 p-i-n/HBT optical receiver array with lowcrosstalk

A multichannel optical receiver with an In_0.53Ga_0.47As p-i-n photodetector array and a monolithic transimpedance amplifier array fabricated in AlGaAs/GaAs HBT (heterojunction bipolar transistor) technology were demonstrated. Both flip-chip rear-illuminated and wire-bonded front-illuminated detector configurations were implemented. The transimpedance was 65 dBΩ, and the 3-dB bandwidth was measured to be 2.3 GHz. By using series feedback, the transimpedance gain of each cell was matched to within 0.5 dB, and the entire array operated from a single 5-V supply. A low interchannel crosstalk of less than -40 dB was measured up to a data rate of 2 Gb/s     

An InP/InGaAs p-i-n/HBT monolithic transimpedance photoreceiver

A monolithically integrated 1-Gb/s p-i-n/HBT transimpedance photoreceiver is discussed. The optoelectronic integrated circuit (OEIC) was made from metalorganic vapor-phase epitaxy (MOVPE)-grown InP/InGaAs heterostructures and had a transimpedance of 1375 Ω, a sensitivity of -26.1 dBm, >25-dB dynamic range, and a 500-MHz bandwidth     

Duobinary transmission with p-i-n f.e.t. optical receivers

Duobinary transmission in a fibre optic system using a p-i-n f.e.t. high impedance receiver has been investigated theoretically and practically. For high bit rates the method gives a sensitivity improvement of 1.5 dB compared to a binary system operating at the same information rate.     

Eight-channel p-i-n/HBT monolithic receiver array at 2.5 Gb/s perchannel for WDM applications

We report a monolithic chip incorporating an eight channel p-i-n/HBT photoreceiver array designed for multichannel WDM applications. The p-i-n photodetectors are edge illuminated and centered at a 250 μm pitch for mating with either ribbon fiber connectors or waveguide demultiplexers. Each channel operates at 2.5 Gb/s with an electrical crosstalk of -20 dB between adjacent channels. The average sensitivity of each receiver in the array was measured to be (-20±1) dBm for a bit error rate of 10^-9 at a wavelength of 1.5 μm     

A wide-band tuning system for fully integrated satellite receivers

The building blocks for a low-power tuning system that reduces the phase noise of integrated VCO's are described. The multimodulus prescaler, the phase frequency detector, and the wide-band charge pump have been integrated in a standard bipolar technology with 9-GHz n-p-n transistors and 200-MHz p-n-p transistors. The maximum input frequency of the multimodulus prescaler is 3.2 GHz, the maximum reference frequency of the phase frequency detector is 380 MHz, and the 3-dB bandwidth of the charge pump is 41 MHz at a reference frequency of 300 MHz. The achieved performance enables the use of fully integrated VCO's with relatively high phase noise for reception of satellite digital signals     

ESD protection for 10 Gbit/s optical receivers

The ESD protection of high-speed RF ICs used in 10 Gbit/s optical receivers with InGaP heterojunction bipolar transistor (HBT) technology is presented. The frequency response of a 10 Gbit/s optical receiver with ESD protection is directly measured. The results indicate that the new ESD circuit can effectively protect input/output pins while with negligible loading effect.     

Analysis and design of wide-band SiGe HBT active mixers

The frequency response of SiGe HBT active mixers based on the Gilbert cell topology is analyzed theoretically. The time-varying operation of the active mixer is taken into account by applying conversion matrix analysis. The main bandwidth-limiting mechanisms experienced in SiGe HBT active mixers performing frequency conversion of wide-band signals is discussed. The analysis is verified by computer simulations using a realistic high-frequency large-signal SiGe HBT model. An active mixer design based on the Gilbert cell topology modified for wide-band operation using emitter degenerated transconductance stage and shunt feedback load stage is discussed. Experimental results are given for an active mixer implemented in a 0.8-/spl mu/m 35-GHz f/sub T/ SiGe HBT BiCMOS process.     

Very-high-speed InP/InGaAs HBT ICs for optical transmission systems

High-speed ICs for 20-40-Gbit/s time-division multiplexing (TDM) optical transmission systems have been designed and fabricated by using InP/InGaAs heterojunction-bipolar-transistor (HBT) technology. This paper describes four analog ICs and four digital ICs: a five-section cascode distributed amplifier with a gain of 9.5 dB and a bandwidth of 50 GHz, a three-section single-end-to-differential converter with a bandwidth of 40 GHz, a cascode differential amplifier with a gain of 10.5 dB and a bandwidth of 64 GHz, a preamplifier with a gain of 41.9 dBΩ and a bandwidth of 39 GHz, a modulator driver with an output voltage swing of 3.2 V peak-to-peak and rise and fall times of 16 and 15 ps, a 40-Gbit/s selector, a 20-Gbit/s D-type flip-flop, and a static frequency divider with an operating range of 2.0-44.0 GHz. All the ICs were measured with on-wafer RF probes     

A wide-band RF front-end for multiband multistandard high-linearity low-IF wireless receivers

A wide-band radio-frequency (RF) front-end is designed with a balanced combined low-noise amplifier and a switching mixer (a low-noise converter) in an RF Si-bipolar process with an f/sub T/ of 25 GHz. The circuit achieves 20-dB conversion gain, higher than -4.5-dBm RF-to-IF IIP/sub 3/ (+15.5-dBm OIP/sub 3/) and less than 3.8-dB double-side-band noise figure in 900-MHz (e.g., GSM) and 1.9-GHz (e.g., WCDMA) frequency bands. The -1-dB compression point is -20 dBm at 13-mA DC current consumption from a single 5-V supply. The local-oscillator leakage to the input is less than -56 dBm in the 900-MHz band and less than -63 dBm in the 1.9-GHz band. The -3-dB bandwidth of the amplifier is larger than 3 GHz and a wide-band matching at the input with -10 to -41-dB S/sub 11/ is achieved in the frequency bands of interest by applying a dual-loop wide-band active feedback. The die area is 0.69 /spl times/ 0.9 mm/sup 2/. The circuit is suitable for area-efficient multiband multistandard low-IF receivers.     

Design considerations for transceiver-limited elastic optical networks

The continuous increase of data traffic for present-day applications necessitates the development of Elastic Optical Networks (EONs). Significant advancements in efficient Routing and Spectrum Assignment (RSA) algorithms for EONs have been noticed in the recent past. These existing algorithms did not mention constraints on the number of transceivers per node in a network. However, for the planning of a realistic network, it is necessary to estimate the number of transceivers required at each node for the efficient operation of a network. Therefore, transceiver constraints should be taken into account while designing the RSA algorithms. In this paper, we present the impact of putting a limit to the number of transmitters and receivers available at each node of an EON. Moreover, the cost of a network heavily depends on the number of transceivers that each node in the network may offer. Hence, estimating the required number of transceivers per node in a network is vital to approximate the design cost of a network. Here, we present an Integer Linear Programming (ILP) formulation that includes the transceiver constraints and also develop a transceiver-aware heuristic algorithm for routing and spectrum assignment in EONs. Simulation results help us provide a proper design tool to estimate the number of transceivers per node in elastic optical networks.

     

ESD protection design considerations for InGaP/GaAs HBT RF power amplifiers

In order to design a robust electrostatic discharge (ESD) protected RF amplifier in InGaP/GaAs HBTs, a comprehensive assessment of device vulnerability to ESD events in both active transistors and passive components of the HBT technology is presented in this paper. The results include not only the intrinsic HBT's ESD robustness performance, but also its dependence on device layout, ballast resistor, and process. Acknowledging the ESD constraints imposed on InGaP/GaAs HBT technology, a 5.4-6.0-GHz power amplifier (PA) with a compact 2000 V/sub ESD/ (human body model) on-chip ESD protection circuit that has a low loading capacitance of less than 0.1 pF and that does not degrade RF and output power performance is developed for wireless local area network application. A diode triggered Darlington pair is implemented as the ESD protection circuit instead of the traditional diode string. Its operation principle, ESD protection performance, and PA performance are also illustrated in this paper.