基于基片集成波导的W波段基波注入锁定谐波振荡器

研制了一种基于基片集成波导的W波段平面注入锁定谐波振荡器.为了获得大的注入功率, 注入锁定谐波振荡器采用基波端口强耦合结构, 利用谐波提取技术的频率倍频作用, 自由振荡输出频率在90.2 GHz附近.当基波注入信号在45.08 GHz附近时, 锁定带宽大于120 MHz, 输出功率大于6.5 dBm.将该平面集成的注入锁定谐波振荡器与低频参考信号同步, 能够产生稳定的W波段低相噪信号.     

用于Ka波段锁相环的宽带注入锁定分频器

基于0.13 μm CMOS工艺,提出了一种用于Ka波段锁相环频率综合器的宽带注入锁定分频器。分析了传统注入锁定分频器的结构、自谐振频率和锁定范围。采用2位可变电容阵列和差分信号互补谐振腔直接注入方法,实现了宽带的注入锁定分频。仿真结果表明,当注入信号幅度V_p为0.6 V时,该注入锁定分频器在24.1~35.6 GHz频率范围内的锁定范围为38.5%。与VCO联合仿真,结果表明,该分频器能准确实现二分频,适用于Ka波段锁相环。     

基于基片集成波导的W波段基波注入锁定谐波振荡器

研制了一种基于基片集成波导的W波段平面注入锁定谐波振荡器.为了获得大的注入功率,注入锁定谐波振荡器采用基波端口强耦合结构,利用谐波提取技术的频率倍频作用,自由振荡输出频率在90.2 GHz附近.当基波注入信号在45.08 GHz附近时,锁定带宽大干120 MHz,输出功率大于6.5 dBm.将该平面集成的注入锁定谐波振荡器与低频参考信号同步,能够产生稳定的W波段低相噪信号.     

一种低相噪频率综合器设计

针对军事、工业、通信等许多领域对高精度、高分辨率、低相噪频率综合器的需求,分析了影响频率综合器相噪特性的主要因素,设计了一种窄带锁相环滤波器,用于两级小数分频锁相环级联组成的频率综合器之间进行降噪,使前级锁相环相噪特性对后级锁相环恶化相噪特性的影响得到很好的抑制,该窄带锁相环滤波器采用4个不同频率低相噪VCXO切换作为后级锁相环的鉴相频率,使频率综合器输出信号频率与整数边界的距离大于后级锁相环环路带宽且尽可能的远,有效抑制了频率综合器输出信号中整数边界杂散(IBS)功率,改善了频率综合器的相噪性能,对频率综合器输出622.08MHz(用于雷达)、1561.098MHz(用于北斗)信号的相位噪声分别为:-96dBc/Hz@100Hz,-105dBc/Hz@10kHz和-91dBc/Hz@100Hz,-100dBc/Hz@10kHz。     

频率源中低相噪VCO的研究与设计

在频率源芯片窄带应用时,输出信号有较好的积分均方根抖动性能(RMS jitter),需要压控振荡器(VCO)有较出色的相噪特性。通过分析VCO的结构特点,确定电感是影响片上VCO相位噪声的关键性因素,通过HFSS软件建模的方式,将高品质因素(Q)值的键合线电感引入到片上VCO设计中。采用0.18μm SiGe BiCMOS工艺,设计了整块频率源芯片,并着重优化了VCO输出信号的相位噪声。经过实测,在开环状态下,VCO输出信号为2.2GHz,在1 MHz频偏处的相位噪声为-136dBc/Hz;在环路带宽80kHz,芯片输出信号相噪2.2GHz时,整颗芯片输出信号的带内本底噪声为-220dBc/Hz,杂散为-70dBc,积分均方根抖动为207.666fs。     

基于超谐波注入锁定的低相噪QVCO的设计

对基于注入锁定的正交压控振荡器(QVCO)电路进行了研究和分析,设计了一个低相位噪声、低相位误差的QVCO电路,该电路由两个电感电容压控振荡器(LC VCO)在正交相位进行超谐波耦合,通过一个频率倍增器在交叉耦合对的共模信号点注入同步信号.通过对相位误差公式的推导,提出了降低相位误差的方法,由于该电路在共模点采用二倍频取样,抑制了尾电流的闪烁噪声,降低了相位噪声.电路基于TSMC 0.18 μm互补金属氧化物半导体(CMOS)工艺实现,测试结果表明,当谐振频率从4.5 GHz调谐到4.9 GHz时,在电源电压为1.8V时,电路消耗功率为13 mW,1 MHz频偏处的单边带(SSB)相位噪声为-129.95 dBc/Hz,与传统的QVCO相比,噪声性能得到了改善.     

单片UHF RFID阅读器中VCO及其预分频器设计

提出了一种应用于860～960 MHz UHF波段单片射频识别(RFID)阅读器的低相位噪声CMOS压控振荡器(VCO)及其预分频电路.VCO采用LC互补交叉耦合结构,利用对称滤波技术改善相位噪声性能,预分频电路采用注入锁定技术,用环形振荡结构获得了较宽的频率锁定范围.电路采用UMC 0.18 μm CMOS工艺实现,测试结果表明:VCO输出信号频率范围为1.283～2.557 GHz,预分频电路的频率锁定范围为66.35%,输出四相正交信号.芯片面积约为1 mm×1 mm,当PLL输出信号频率为895.5 MHz时,测得其相位噪声为-132.25 dBc/Hz@3 MHz,电源电压3.3 V时,电路消耗总电流为8 mA.     

六毫米波段注入锁定振荡器

本文描述一种六毫米波段注入锁定振荡器.该振荡器由耿管振荡器、环行器、锁相参考源组成,耿管振荡器采用背腔式稳频和谐振帽电路结构,输出端经环行器与高稳定度锁相源连接.注锁振荡器的输出功率大于60mW,振荡频率为46.1GHz,偏离载频10kHz处,单边带(SSB)相位噪声≤-71.7dBc/Hz,杂波≤-40dB.     

基于Rb原子频标电注入锁定的高频稳低相噪光电振荡器

为了进一步改善光电振荡器(OEO)输出信号频 率的长期稳定度和相位噪声,提出了一种基于 Rb原子频标电注入锁定的单环OEO。将Rb原子钟产生的高频稳正弦信号注入到单环OEO,通过 注入信号与自由振荡信号的频率牵引,OEO获得单一振荡模式。实验发现,随着注入功 率的 增大,锁定带宽变大,锁定信号的相位噪声变差;随着注入功率的下降,锁定带宽变小,锁 定信号的相位噪声得 到改善,趋近于注入源信号的相位噪声。当光纤长取10km时,获得 了中心频率10GHz、边模抑制比大 于60dB、相位噪声的指标为－76dBc/Hz@100Hz和－108dBc/Hz@10kHz的输出信号,其输 出信号的长期稳定度和准确度得到改善。实验结果与理论分析一致。     

宽带低相位噪声锁相环型频率合成器的CMOS实现

用0.25μm标准CMOS工艺实现了单次变频数字有线电视调谐器中的频率合成器.它集成了频率合成器中除LC调谐网络和有源滤波器外的其他模块.采用I2C控制三个波段的VCO相互切换,片内自动幅度控制电路和用于提升调谐电压的片外三阶有源滤波器,实现VCO的宽范围稳定输出.改进逻辑结构的双模16/17预分频器提高了电路工作速度.基于环路的行为级模型,对环路参数设计及环路性能评估进行了深入的讨论.流片测试结果表明,该频率合成器的锁定范围为75～830MHz,全波段内在偏离中心频率10kHz处的相位噪声可以达到-90.46dBc/Hz,100kHz处的相位噪声为-115dBc/Hz,参考频率附近杂散小于-90dBc.     

An Integrated 5–2.5-GHz Direct-Injection Locked Quadrature LC VCO

This letter presents an integrated direct-injection locked quadrature voltage controlled oscillator (VCO), consisted of a 5-GHz VCO integrated with injection locked LC frequency dividers for low-power quadrature generation. The circuit is implemented using a standard 0.18-mum CMOS process. The differential VCO is a full PMOS Colpitts oscillator, and the frequency divider is performed by adding an injection nMOS between the differential outputs of complementary cross-coupled np-core LC VCO. The measurement results show that at the supply voltage of 1.8-V, the master 5-GHz VCO is tunable from 4.73 to 5.74GHz, and the slave 2.5-GHz VCO is tunable from 2.36 to 2.87GHz. The measured phase noise of master VCO is -118.2dBc/Hz while the locked quadrature output phase noise is -124.4dBc/Hz at 1-MHz offset frequency, which is 6.2dB lower than the master VCO. The core power consumptions are 7.8 and 8.7mW at master and slave VCOs, respectively     

一种基于偏移源的频率合成技术分析

针对一种基于偏移源的频率合成技术,建立了锁相环(PLL)线性模型,对相位噪声和杂散信号性能进行分析。从分析结果看,在锁相环反馈支路中使用一个偏移源将压控振荡器(VCO)输出信号下混频至一个较低的中频,从而将锁相环的环路分频比大大降低,使改善后的锁相环噪底达到-135 dBc/Hz。介绍了偏移源和主环的关键合成技术,结合工程应用设计的基于偏移源的C频段频率合成器,相位噪声偏离载波10 kHz处≤-99 dBc/Hz,偏离载波100 kHz处≤-116 dBc/Hz,杂散小于-70 dBc。     

Low noise 5 GHz differential VCO using InGaP/GaAs HBT technology

The authors present the first InGaP/GaAs HBT differential VCOs with low phase noise performance. One is a cross coupled differential VCO, and the other is a Colpitts differential VCO. To achieve a fully integrated VCO, collector-base junction capacitance of HBT transistor is used for the frequency tuning varactor. The measured output frequency ranges of VCOs are 290 MHz and 190 MHz, and the phase noises at an offset frequency of 1 MHz are -118 dBc/Hz and -117 dBc/Hz respectively. The each VCO core dissipates 13.2 mW from a 3.5 V supply, and the output power is about -0.2 dBm. Concerned with cross coupled VCO, it shows the figure of merit of -179 dBc/Hz, which is the best result among the reported compound semiconductor FET and HBT VCOs.     

A 2.7–6.1 GHz CMOS local oscillator based on frequency multiplication by 3/2

Frequency multiplication by 3/2 is proposed as a means to expand the frequency generation capabilities of a single LC VCO. Fractional frequency multiplication is obtained by cascading a broadband injection locked modulo-two divider and a multiply-by-three circuit based on edge combining. The proposed solution is inductorless, thus very compact. It allows the generation of all frequencies from 2.7 to 6.1 GHz with a performance suitable for cellular standards. It shows a phase noise floor below ?150 dBc/Hz and a spurious level below ?35 dBc. The multiplier by 3/2 consumes 5 mA and the VCO draws 10 mA from a 1.2 V supply. The additional power consumption due to the multiplier trades with the small area penalty and the flexibility of this solution, compared to the use of multiple LC VCOs.     

A 6-GHz capacitively-coupled Colpitts CMOS quadrature voltage controlled oscillator

In this work a new low-noise low-power Colpitts quadrature voltage controlled oscillator (QVCO) made by coupling two identical current-switching differential Colpitts voltage controlled oscillators (VCO) is proposed; coupling of the VCOs is done using some capacitors in an “in-phase anti-phase” scheme. In this coupling configuration first harmonics (as well as higher harmonics) from each VCO are injected to the other VCO, as opposed to coupling schemes in which only even harmonics are injected. An analysis of the linearized circuit which confirms 90° phase difference between output signals of the proposed circuit is presented. Since no extra noise sources or power consumption are introduced to the core VCOs, the proposed QVCO achieves low phase noise performance and low power consumption. The proposed circuit is designed and simulated in a commercial 0.18 μm CMOS technology. The simulated phase noise of the proposed QVCO at 3 MHz offset frequency is ?138.3 dBc/Hz, at 6 GHz. The circuit dissipates 8.16 mW from a 1.8 V supply and its frequency can be tuned from 5.6 to 6.3 GHz.     

Phase noise in externally injection-locked oscillator arrays

Previous investigations of noise in mutually synchronized coupled-oscillator systems are extended to include the effects of phase noise introduced by externally injected signals. The analysis is developed for arbitrarily coupled arrays and an arbitrary collection of coherent injected signals, and is illustrated with the specific case of linear chains of nearest neighbor coupled oscillators either globally locked (locking signal applied to each array element) or with the locking signal applied to a single-array element. It is shown that the general behavior is qualitatively similar to a single injection-locked oscillator, with the output noise tracking the injected noise near the carrier, and returning to the free-running array noise far from the carrier, with intermediate behavior significantly influenced by the number of array elements and injection strength. The theory is validated using a five-element GaAs MESFET oscillator array operating at S-band     

Steered coupled-cavity-backed Hertzian dipole array

This paper presents the operating characteristics of a coupled-cavity-backed Hertzian dipole resonator array excited with mutually injection-locked voltage-controlled oscillators (VCOs). It is demonstrated that microwave spatial power-combined inter-injection locking through mutual coupling of individual antenna oscillators can be obtained with an auxiliary coupling network formed by a cavity iris configuration introduced within a reduced-height waveguide arrangement. As a result, strong mutual-coupling control can be realized and exploited in conjunction with self-injection-locked oscillators in order to achieve direct phase modulation of the locked oscillators. Beam scanning up to 10° off the broadside through locked VCO phase modification has been demonstrated in a three-element array occupying a space of only 0.6 λ₀×0.027 λ_o at 998 MHz     

一种双带宽UHF主从耦合式LC VCO

为了满足无线通信系统应用需要,设计了一种主从耦合式LC压控振荡器(VCO).基于0.18 μm CMOS标准工艺,由一个5 GHz主VCO和两个起分频作用的从VCO组成,其中主VCO选用PMOS考毕兹差分振荡结构,在两个互补交叉耦合的从VCO的输出端之间设置有注入式NMOS器件以达到分频的目的.仿真及硬件电路实验结果表明,在1.8 V低电源电压下,5 GHz主VCO的调谐范围为4.68～5.76 GHz,2.5 GHz从VCO的调谐范围为2.32～2.84 GHz;在1 MHz的偏频下,5 GHz主VCO的相位噪声为118.2 dBc/Hz,2.5 GHz从VCO的相位噪声为124.4 dBc/Hz.另外,主从VCO的功耗分别为6.8 mW和7.9 mW,因此特别适用于低功耗、超高频短距离无线通信系统中.     

A Q-band low phase noise monolithic AlGaN/GaN HEMT VCO

A Q-band 40-GHz GaN monolithic microwave integrated circuit voltage controlled oscillator (VCO) based on AlGaN/GaN high electron mobility transistor technology has been demonstrated. The GaN VCO delivered an output power of +25dBm with phase noise of -92dBc/Hz at 100-KHz offset, and -120dBc/Hz at 1-MHz offset. To the best of our knowledge, this represents the state-of-the-art for GaN VCOs in terms of frequency, output power, and phase noise performance. This work demonstrates the potential for the use of GaN technology for high frequency, high power, and low phase noise frequency sources for military and commercial applications.     

Design and Scaling of W-Band SiGe BiCMOS VCOs

This paper discusses the design of 77-106 GHz Colpitts VCOs fabricated in two generations of SiGe BiCMOS technology, with MOS and HBT varactors, and with integrated inductors. Based on a study of the optimal biasing conditions for minimum phase noise, it is shown that VCOs can be used to monitor the mm-wave noise performance of SiGe HBTs. Measurements show a 106 GHz VCO operating from 2.5 V with phase noise of -101.3 dBc/Hz at 1 MHz offset, which delivers +2.5 dBm of differential output power at 25degC, with operation verified up to 125degC. A BiCMOS VCO with a differential MOS-HBT cascode output buffer using 130 nm MOSFETs delivers +10.5 dBm of output power at 87 GHz.