基于深度置信网络的互联网流量预测方法

对未来网络流量负荷的预测有助于运营商精确预估网络使用情况,优化网络资源,提高用户满意度。本文提出了基于深度置信网络(DBN)的三种不同架构的网络流量预测模型来预测未来1小时的互联网流量,首先,介绍了DBN的网络结构;然后构建了三种不同架构的DBN拓扑结构,最后通过实验对比,发现隐藏层的神经元数量对更深层次的网络至关重要,该模型被证明是一种有效的预测模型。本文所采用的方法在模拟流量数据模式和随机要素的同时,提供了准确的网络流量预测,使测试数据集的均方根误差(RMSE)值为0.028。     

Implementation of multipoint connections in an ATM switching network

This paper presents the problems in the implementation of multipoint connections at switching level using the example of an ATM switching network. By choosing the proper routeing mechanism and the appropriate architecture of the switching element, a switching network can gradually be adapted to an increasing share of multipoint traffic. The first section describes the problems with the handling of multipoint connections within a multiple stage connection oriented switching network. In particular this refers to the routeing of the cells through the switching network. Several alternatives on this issue are discussed. Both, the selected approach based on a differentiated self-routeing mechanism and the corresponding cell format are introduced. In the second part of this article several switch architectures are compared in respect of their multipoint capability. It is demonstrated that at present the most promising solution are switching elements based on the principle of central buffering. A single chip solution using this concept is employed in the presented switching network.     

ATM performance evaluation under transparencies of a distributedsystem environment (DSE)

Management architectures as well as protocols for accessing managed entities and exchanging management information are well developed in standards. On the other hand developments in open distributed processing (ODP) are of recognized importance for network and service management. Their generic features fit well into the geographically extended, multiple vendor and heterogeneous environment of communication networks. As a third ongoing development asynchronous transfer mode (ATM) broadband integrated services digital networks (B-ISDN) offer challenging problems for resource allocation, network performance and quality of service (QoS) evaluation in real time. The paper shows how performance monitoring and evaluation for ATM networks can greatly profit from the features of a distributed system environment (DSE). The extreme flexibility offered by the ATM principle requires a rich and reusable set of servers accomplishing coordinated performance evaluation tests. DSE transparencies are an excellent match to corresponding management applications (MA) requirements, so that tests can be performed in a distributed, flexible and adaptable way under a conceptually simple architecture. The paper draws extensively from a non-distributed counterpart, i.e. an existing sophisticated ATM test and analysis tool developed under the “Research for Advanced Communications in Europe” (RACE) program, R1083 PARASOL project     

FPGA-implementation of dynamic time delay neural network for power amplifier behavioral modeling

In this paper, we propose new architectures for FPGA-implementation of a dynamic neural network power amplifier behavioral modeling. The real-valued time-delay neural network (RVTDNN) and the backpropagation (BP) learning algorithm were implemented on FPGA using Xilinx system generator for DSP and the Virtex-6 FPGA ML605 evaluation kit. Different RVTDNN architectures are proposed for various values of the number of hidden neurons, the activation function resolution, and the fixed-point data format. These architectures are evaluated and compared in terms of modeling performances and resource utilization using 16-QAM modulated test signal.     

基于多维扩展特征与深度学习的微博短文本情感分析

该文提出了一种基于深度信念网络(DBN)和多维扩展特征的模型,实现对中文微博短文本的情感分类。为降低传统文本分类方法在处理微博短文时特征稀疏的影响,引入社交关系网络作为扩展特征,依据评论者和博主之间的社交关系,提取相关评论扩展原始微博,将扩展后的多维特征作为深度信念网络的输入。通过叠加多层玻尔兹曼机(RBM)构建DBN模型底层网络结构,多层玻尔兹曼机可以对原始输入抽象并获得数据的深层语义特征。在多个RBM层上叠加一层分类玻尔兹曼机(ClassRBM),实现最终情感分类。实验结果表明,通过调整模型参数和网络结构,构建的深度学习模型在情感分类中能够获得比SVM和NB等浅层分类系统更优的结果,另外,实验证明使用扩展多维特征方法可提高短文本情感分类的性能。     

A survey of hybrid optical data center network architectures

This paper presents a survey of data center network architectures that use both optical and packet switching components. Various proposed architectures and their corresponding network operation details are discussed. Electronic processing-based packet switch architectures and hybrid optical–electronic-based switch architectures are presented. These hybrid optical switch architectures use optical switching elements in addition to traditional electronic processing entities. The choice of components used for realizing functionality including the network interfaces, buffers, lookup elements and the switching fabrics have been analyzed. These component choices are summarized for different architectures. A qualitative comparison of the various architectures is also presented.     

One- and two-dimensional constant geometry fast cosine transformalgorithms and architectures

This paper presents general radix one- and two-dimensional (1-D and 2-D) constant geometry fast cosine transform algorithms and architectures suitable for VLSI, owing to their regular structures. A constant geometry algorithm is obtained by shuffling the rows and columns of each decomposed DCT matrix that corresponds to a butterfly stage. The 1-D algorithm is derived, and then, it is extended to the 2-D case. Based on the derived algorithms, the architectures with a flexible degree of parallelism are discussed     

Layering as Optimization Decomposition: A Mathematical Theory of Network Architectures

Network protocols in layered architectures have historically been obtained on an ad hoc basis, and many of the recent cross-layer designs are also conducted through piecemeal approaches. Network protocol stacks may instead be holistically analyzed and systematically designed as distributed solutions to some global optimization problems. This paper presents a survey of the recent efforts towards a systematic understanding of layering as optimization decomposition, where the overall communication network is modeled by a generalized network utility maximization problem, each layer corresponds to a decomposed subproblem, and the interfaces among layers are quantified as functions of the optimization variables coordinating the subproblems. There can be many alternative decompositions, leading to a choice of different layering architectures. This paper surveys the current status of horizontal decomposition into distributed computation, and vertical decomposition into functional modules such as congestion control, routing, scheduling, random access, power control, and channel coding. Key messages and methods arising from many recent works are summarized, and open issues discussed. Through case studies, it is illustrated how layering as Optimization Decomposition provides a common language to think about modularization in the face of complex, networked interactions, a unifying, top-down approach to design protocol stacks, and a mathematical theory of network architectures     

Digit-Serial Pipeline Sorter Architecture

This paper presents the VLSI architecture design of pipeline sorter which is suitable for the fast sorting of the continuous serial input data stream. By decomposing the Batcher’s merge-sort process into a network of compare-and-swap (C&S) operations, two different styles of pipeline architectures based on the feedback and feed-forward data shuffling modules can be first achieved. However, both architectures suffer the low hardware utilization due to the discrepancy of input sample rate and internal processing rate. Therefore, this paper further proposes a novel digit-serial pipeline sorter architecture by dividing the data into two sub-words. In addition, the most-significant half-word data are processed first in order to reduce the internal register overhead incurred in the C&S unit. Our experimental results show that about 50% saving of gate counts can be achieved by the digit-serial approach.     

Image processing using one-dimensional processor arrays

The first half of this paper presents the design rationale for CNAPS, a specialized one-dimensional (1-D) processor array developed by Adaptive Solutions Inc. In this context, we discuss the problem of Amdahl's law which severely constrains special-purpose architectures. We also discuss specific architectural decisions such as the kind of parallelism, the computational precision of the processors, on-chip versus off-chip processor memory, and-most importantly-the interprocessor communication architecture. We argue that, for our particular set of applications, a 1-D architecture gives the best “bang for the buck”, even when compared to the more traditional two-dimensional (2-D) architecture. The second half of this paper describes how several simple algorithms map to the CNAPS array. Our results show that the CNAPS 1-D array offers excellent performance over a range of IP algorithms. We also briefly look at the performance of CNAPS as a pattern recognition engine because many image processing and pattern recognition problems are intimately related     

对一台先进电子束曝光机制作掩模过程的分析

本文通过对一台先进电子束曝光机制作掩模过程的分析,阐明设计图经计算机辅助设计系统数字化后,生成PG格式数据,再由PG格式数据转换成电子束格式数据的处理;论述了光栅扫描的原理及特点;介绍了图形发生器的作用及电子束在控制系统作用下在基片上描绘图形的过程。     

Architectural approaches for the integration of the service plane and control plane in optical networks

This paper presents some instantiations of novel application-aware network architectures for emerging IT services and future Internet applications. It proposes and analyses network architectures where the Control and Service Planes are closely and seamlessly interacting with the applications. One instantiation, the Grid-GMPLS (G²MPLS, as defined by the Phosphorus project) is presented, which implements the Network Control Plane (NCP) architecture for the support of Grid Network Services (GNS). The GNS allows the provisioning of network and HPC/Grid resources in a single-step through a set of seamlessly integrated procedures. In a second example of instantiation, a quite popular application in signalling, i.e. the Session Initiation Protocol (SIP), is integrated with the Optical Burst Switched (OBS) network technology. The SIP-enabled OBS network can be used to manage application sessions and provide network and IT services according to application requirements. This paper investigates the requirements that these new integrated architectures impose on supporting network Control and Service Planes, and technologies, and discusses their possible implementations.     

采用局部二值模式与深度信念网络的人脸识别

针对人脸维度过高和人脸局部特征提取易忽略的问题,提出了一种将多尺度局部二值模式( LBP)算法与深度信念网络( DBN)算法相结合的人脸识别方法。首先采用多尺度LBP算法提取人脸纹理特征,进而将LBP提取的纹理特征作为深度信念网络的输入,最后通过逐层网络训练,得到网络的最优参数,并在ORL人脸库中进行测试,识别率可达95.2%,比使用Gabor小波和主成分分析(PCA)算法的人脸识别高2.6%,说明该算法具有很好的人脸识别能力。     

基于改进的DBN的WLAN指纹定位数据库构建算法

提出了一种基于改进的深度置信网络(Deep Belief Network,DBN)的 WLAN指纹定位数据库构建算 法。首先,从需要实地测量的参考点中选取一部分参考点测量位置坐标和接收信号强度,并 将其作为训练数据输入改进的 DBN,经过训练不断改善DBN的性能;然后,将其他剩余参考点的位置坐标输入训练好的DBN 中,将DBN的输出数据作 为这些参考点的接收信号强度,从而对指纹定位数据库进行构建;最后,将实测的部分参考 点的数据与基于DBN预测出的 剩余参考点的数据共同组成构建后的指纹定位数据库,并使用KNN和WKNN定位算法对构建效 果进行评价。实验结果表 明,在使用相同的数据集时,改进的DBN算法训练用时更短,对指纹库的构建效果更好。     

Economic comparisons of alternative fiber-based local access architectures using ATM components

This paper presents some engineering and economic comparisons of several fiber-based network architectures providing narrowband, and in some cases broadband, services in the subscriber loop. Specifically, comparisons are made between different bus and star configurations in the sub-feeder plant using asynchronous transfer mode (ATM) network components. The study reports in detail an engineering cost model used to determine the installed first cost of several access architectures, including several fiber-to-the-curb approaches which interface to the existing copper drop. The results show that these approaches can reduce the initial first cost of fiber installation, although other issues regarding network operations, maintenance, and evolution still need to be addressed.     

Partially Protected Caches to Reduce Failures Due to Soft Errors in Multimedia Applications

With advances in process technology, soft errors are becoming an increasingly critical design concern. Owing to their large area, high density, and low operating voltages, caches are worst hit by soft errors. Based on the observation that in multimedia applications, not all data require the same amount of protection from soft errors, we propose a partially protected cache (PPC) architecture, in which there are two caches, one protected and the other unprotected at the same level of memory hierarchy. We demonstrate that as compared to the existing unprotected cache architectures, PPC architectures can provide 47 times reduction in failure rate, at only 1% runtime and 3% power overheads. In addition, the failure rate reduction obtained by PPCs is very sensitive to the PPC cache configuration. Therefore, this observation provides an opportunity for further improvement of the solution by correctly parameterizing the PPC configurations. Consequently, we develop design space exploration (DSE) strategies to discover the best PPC configuration. Our DSE technique can reduce the exploration time by more than six times as compared to an exhaustive approach.      

Synthesis of area-efficient and high-throughput rate data formatconverters

This paper proposes two design methodologies for synthesis of area-efficient data format converters (DFCs) with high throughput rate. DFCs are grouped into various classes according to the specification of design parameters. The first design methodology is suitable for design of many representative classes of DFCs. The designs using this methodology are based on a two-dimensional (2-D) architecture. They have maximum throughput rate and are area-efficient. Various design examples are shown to demonstrate improved performance, flexibility and usefulness of this design methodology. For several representative problems, the area requirements of our designs are compared against those obtained by earlier design methodologies. For all the problems considered, this methodology leads to compact designs. The second design methodology employs an architecture using dual buffers. The simple and regular architecture using dual buffers leads to area-efficient DFCs. The design procedure using this methodology is simple and can reduce the design effort in many applications     

Coherent Doppler tomography for microwave imaging

A tomographic extension of the type of microwave Doppler imaging typified by synthetic aperture radar has recently been developed and shown experimentally to exhibit a high degree of spatial resolution. When CW irradiation is used, the sidelobes in the pointspread function are inherently high and tend to limit the dynamic range of the reconstructed images. The point-spread function of a system using CW irradiation and an aperture that completely surrounds the object has a central lobe of width of λ/5, but the first sidelobe is only 8 dB below the central peak. The limitation due to the high sidelobes can be partially overcome by using wide-band signals or bistatic diversity. One of the steps in reconstructing a coherent Doppler tomogram is to perform a two-dimensional Fourier transform. The ordinary two-dimensional discrete Fourier transform (DFT) produces points in the transform space on a Cartesian raster. In coherent Doppler tomography (CDT), however, the data are sampled on a polar raster. To diminish the computational burden associated with converting to the Cartesian raster and interpolating, we have developed an alternative algorithm which requires no interpolation and is based on interpreting the two-dimensional Fourier transform as a one-dimensional circular convolution integral. The quality of the images computed in this fashion compares favorably with that for the old method and the computational burden is greatly reduced.