An efficient tree architecture for modulo 2 n +1 multiplication

Modulo 2 ⁿ +1 multiplication plays an important role in the Fermat number transform and residue number systems; the diminished-1 representation of numbers has been found most suitable for representing the elements of the rings. Existing algorithms for modulo (2 ⁿ +1) multiplication either use recursive modulo (2 ⁿ +1) addition, or a regular binary multiplication integrated with the modulo reduction operation. Although most often adopted for largen, this latter approach requires conversions between the diminished-1 and binary representations. In this paper we propose a parallel fine-grained architecture, based on a Wallace tree, for modulo (2 ⁿ +1) multiplication which does not require any conversions; the use of a Wallace tree considerably improves the speed of the multiplier. This new architecture exhibits an extremely modular structure with associated VLSI implementation advantages. The critical path delay and the hardware requirements of the new multiplier are similar to that of a correspondingn×n bit binary multiplier.     

A simplified synthesis of transmission lines with a tree structure

The limiting factor for high-performance systems is being set by interconnection delay rather than transistor switching speed. The advances in circuits speed and density are placing increasing demands on the performance of interconnections, for example chip-to-chip interconnection on multichip modules. To address this extremely important and timely research area, we analyze in this paper the circuit property of a generic distributedRLC tree which models interconnections in high-speed IC chips. The presented result can be used to calculate the waveform and delay in anRLC tree. The result on theRLC tree is then extended to the case of a tree consisting of transmission lines. Based on an analytical approach a two-pole circuit approximation is presented to provide a closed form solution. The approximation reveals the relationship between circuit performance and the design parameters which is essential to IC layout designs. A simplified formula is derived to evaluate the performance of VLSI layout.     

On a case of symbiosis between systolic arrays

The paper studies the problem of efficiently computing the product of three n × n matrices using O(n²) elementary processors in O(n) time. The problem is relevant in image processing.After a critical analysis of extensions on well-known systolic arrays for matrix multiplication to solve the proposed problem, a systolic system is disclosed, which achieves the optimal VLSI-complexity AT² = O(n⁴).     

A VLSI structure forX(modm) operation

High-computing speed and modularity have made RNS-based arithmetic processors attractive for a long time, especially in signal processing, where additions and multiplications are very frequent. The VLSI technology renewed this interest because RNS-based circuits are becoming more feasible; however, intermodular operations degradate their performance and a great effort results on this topic. In this paper, we deal with the problem of performing the basic operationX(modm), that is the remainder of the integer divisionX/m, for large values of the integerX, following an approximating and correcting approach, which guarantees the correctness of the result. We also define a structure to computeX(modm) by means of few fast VLSI binary multipliers, which is exemplified for 32-bit long numbers, obtaining a total response time lower than 200 nsec. Furthermore, such a structure is evaluated in terms of VLSI complexity and area and time figuresA=?(n ² T _m ² ) andT=?(T _M ) for the parameterT _M in \([\log n,\sqrt n ]\) are derived. A simple positional-to-residue converter is finally presented, based on this structure; it improves some complexity results previously obtained by authors.     

Design of a Cellular Architecture for Fast Computation of the Skeleton

This paper presents a new algorithm to extract the skeleton and its Euclidean distance values from a binary image. The extracted skeleton reconstructs the objects in the image exactly. The algorithm runs in O(n) time for an image of size n × n. It involves simple local neighborhood operations for each pixel and hence it is quite amenable to VLSI implementation in a cellular architecture. Results of simulation of the algorithm in a sequential computer are presented. Results of implementation of a VLSI design in Xilinx FPGA are also presented and they confirm the speed and suitability of our method for real-time applications.     

Contributions to VLSI computational complexity theory from bounds on current density

The grid models of VLSI algorithms embody the common assumption that time delays on wires of length L are O(log L). We show that the hierarchical model of driver circuitry responsible for this result is restricted, in its application to asymptotic complexity determinations, by the physical upper bound on current density in the wires for any VLSI technology. Unlike other alternative models of wire delay concerned with resistive properties of the wires or transmission line effects, there are no practical technological fixes for current density limits. It is suggested that the appropriate model for physically realizable VLSI algorithms should contain asymptotic wire delays that are Q(L).     

An efficient tree architecture for modulo 2n+1 multiplication

Modulo 2 ⁿ +1 multiplication plays an important role in the Fermat number transform and residue number systems; the diminished-1 representation of numbers has been found most suitable for representing the elements of the rings. Existing algorithms for modulo (2 ⁿ +1) multiplication either use recursive modulo (2 ⁿ +1) addition, or a regular binary multiplication integrated with the modulo reduction operation. Although most often adopted for largen, this latter approach requires conversions between the diminished-1 and binary representations. In this paper we propose a parallel fine-grained architecture, based on a Wallace tree, for modulo (2 ⁿ +1) multiplication which does not require any conversions; the use of a Wallace tree considerably improves the speed of the multiplier. This new architecture exhibits an extremely modular structure with associated VLSI implementation advantages. The critical path delay and the hardware requirements of the new multiplier are similar to that of a correspondingn×n bit binary multiplier.     

Placing and maintaining a core node in wirelessad hoc networks

Wireless ad hoc networks are characterized by several performance metrics, such as bandwidth, transport, delay, power, etc. These networks are examined by constructing a tree network. A core node is usually chosen to be the median or center of the multicast tree network with a tendency to minimize a performance metric, such as delay or transport. In this paper, we present a new efficient strategy for constructing and maintaining a core node in a multicast tree for wireless ad hoc networks undergoing dynamic changes, based on local information. The new core (centdian) function is defined by a convex combination signifying total transport and delay metrics. We provide two bounds of O(d) and O(d+l) time for maintaining the centdian using local updates, where l is the hop count between the new center and the new centdian, and d is the diameter of the tree network. We also show an O(n log n) time solution for finding the centdian in the Euclidian complete network. Finally, an extensive simulation for the construction algorithm and the maintenance algorithm is presented along with an interesting observation. Copyright © 2009 John Wiley & Sons, Ltd.     

基于自组织特征映射特性的栅阵列排序算法

本文应用自组织特征映射神经网络的竞争学习和自组织特性,并根据栅阵列排序问题的性质来设定网络的竞争原则,建立了一个栅阵列排序算法.实验证明该算法可以求得十分接近全局最优解下限的布图结果.该算法的时间复杂度为O(np2In p),n为线网数,p为主栅列数.     

A technique for modelling p-n junction depletion capacitance of multiple doping regions in integrated circuits

The continuing advancements in integrated circuit technology have placed new burdons on the circuit design engineer, who must rely extensively upon computer simulation to correctly predict circuit behavior. One challenge is to develop better modelling techniques to more accurately deal with complex p-n junction structures often used in modern VLSI designs. This paper presents an easily implemented method for deriving parameters which accurately model the behavior of MOS VLSI structures containing complex p-n junction capacitance components. The methodology is applicable to both planar and laterally diffused junctions, whether formed by direct ion implantation or by diffusion from a finite or infinite source. The theories behind the equations used and results of the application of this new technique are discussed. A flow chart for a fitter program based on the new method is presented and described. The corresponding program written for the TI-59 scientific programmable calculator is available. Final model parameters are given and are shown to produce a numerical capacitance model which is accurate to within 2%.     

A multiplexer-based digital passive linear counter (PLINCO)

A ones adder is an important circuit block that is required in many varying applications. This work proposes a design that largely relies on passive transmission-gate multiplexers. Many variations are suggested that can inherently generate a thermometer coded output or one-hot encoded output. The proposed structure has area and power that increases with order n ² for a n number of inputs. A folding technique is then suggested that reduces the area/power to order n log(n). The folded passive linear counter also has a cell-based structure that aids in layout and makes it possible to be added to a digital standard cell library.     

Efficient statistical leakage analysis using deterministic cell leakage models

This paper presents an efficient approach to statistical leakage analysis (SLA) that can estimate the arbitrary n-sigma leakage currents of the VLSI system for the probability density function (PDF) of a lognormal distribution. Unlike existing SLA approaches, the proposed method uses deterministic cell leakage models and gate-level deterministic leakage analysis, and thus, provides significantly reduced analysis complexity. Providing the n-sigma chip leakage current for the PDF of WM-based SLA with a computational complexity of O(N), where N is the number of cells in a chip, the proposed approach is a promising candidate for the analysis of recent technology (comprising billions of logic cells in a chip) to address the high-complexity of conventional approaches to SLA. Compared to conventional WM-based SLA, when the value of n was 5.1803, 3.6022, and 2.8191, the average absolute errors of n-sigma chip leakage current exhibited by the proposed approach were 5.08%, 4.73%, and 4.45%, respectively.     

A fast near optimum VLSI implementation of FFT using residue number systems

Many FFT processor designs have been proposed, most of which have been limited by hardware costs when a large number of points is to be processed.In recent years, VLSI technology modified design methodology and determined a general reduction of costs. The scope of this work is to present a fast near optimum VLSI architecture for solving an N-point FFT which exhibits T= ?(log log N) and AT² = ?(N²log²N log log N). Main features are: very high parallelism, proper communication parallelism, residue arithmetic, table look-up techniques and pipeline of data.Moreover, it will be shown that design performance does not depend on the input and output data representation (residue or weighted notation).     

An Extension of Kedlaya's Algorithm to Hyperelliptic Curves in Characteristic 2

We present an algorithm to compute the zeta function of an arbitrary hyperelliptic curve over a finite field F_q of characteristic 2, thereby extending the algorithm of Kedlaya for odd characteristic. Given a genus g hyperelliptic curve defined over F_qⁿ, the average-case time complexity is O(g^{4 + ε} n^{3 + ε}) and the average-case space complexity is O(g³ n³), whereas the worst-case time and space complexities are O(g^{5 + ε} n^{3 + ε}) and O(g⁴ n³), respectively.     

Exact solutions to the problem of wave diffraction from a Bragg grating with an apodized asymmetric, symmetric, or antisymmetric coupling factor

The coupling-wave model is applied to obtain an exact analytic solution to the problem of diffraction of a plane electromagnetic wave from a nonharmonic Bragg grating with a spatially modulated refractive index n(z) = n ₀ + Δn(z)cos(2πz/d + ?). Apodization for such gratings is described by continuous functions of the form n(z) = ±Δn/[1 ? n(z ? L/2)] (d, L, ?, and Δn = const are the period, length, phase, and amplitude of a grating, respectively) or piecewise-continuous symmetric and antisymmetric analogues constructed from these functions. Conditions ensuring suppression of oscillations in the reflection and transmission spectra of these gratings are found. It is shown that, when the coupling factor of a grating is antisymmetric, a narrow transparency band is observed within the forbidden transmission band located near a Bragg resonance. An analytic expression is obtained for the dependence of the width of the transparency band on the grating’s parameters. Gratings with an antisymmetric coupling factor can be used in narrowband frequency-selective Bragg transmission filters.     

Input Locality and Hardness Amplification

We establish new hardness amplification results for one-way functions in which each input bit influences only a small number of output bits (a.k.a. input-local functions). Our transformations differ from previous ones in that they approximately preserve input locality and at the same time retain the input size of the original function. Let f:{0,1} ⁿ →{0,1} ^m be a one-way function with input locality d, and suppose that f cannot be inverted in time $\exp(\tilde{O}(\sqrt{n}\cdot d))$ on an ε-fraction of inputs. Our main results can be summarized as follows:

• If f is injective then it is equally hard to invert f on a (1?ε)-fraction of inputs.
• If f is regular then there is a function g:{0,1} ⁿ →{0,1} ^m+O(n) that is d+O(log³ n) input local and is equally hard to invert on a (1?ε)-fraction of inputs.

A natural candidate for a function with small input locality and for which no sub-exponential time attacks are known is Goldreich’s one-way function. To make our results applicable to this function, we prove that when its input locality is set to be d=O(logn) certain variants of the function are (almost) regular with high probability. In some cases, our techniques are applicable even when the input locality is not small. We demonstrate this by extending our first main result to one-way functions of the “parity with noise” type.     

Computer-aided design of an n-MOS custom IC-“Subscriber Chip” of the 32-lines microprocessor based PAX (private automatic exchange) system

A 40-pin custom IC-“Subscriber Chip” of the subscriber module of the Intel 8085A microprocessor based PAX system (32P₄-32 lines and four parallel conversations) has been designed using CAD techniques. The chip design is based on the LOCOS n-MOS(E-D) process, 8 micron minimum feature size geometries, λ-based design rules and the cell based design approach.DIF-POL contact for the gate-source interconnection of the depletion load transistors has been made with the buried contacts. System routing has been done on two layers: metal and polysilicon/diffusion. Single metal layer has been used for power and ground routing having interdigitated structure.Chip has also been designed for its testability analysis based on the chip partioning approach. Two phases of the testing have been evolved and the test pattern generation sequences got fully integrated with the chip layout.Latest CAD techniques: Applicon AGS/860 VLSI Interactive Graphics Design System, MOS circuit simulation program MSINC and Design Rule Check program (DRC) have been used for the design and chip layout. The entire chip has been laid-out in the area of 3.35 × 3.35 mm² integrating around 500 components including test devices and structures for the evaluation of devices and process parameters. The Electromask pattern generation (PG) tape has been prepared for making chrome masks.A set of eight masks are to be used in the fabrication of the chip and encapsulated in 40 pin LSI package. The subscriber chip makes the PAX system design simple and reliable.     

Low-complexity bit-parallel systolic multipliers over GF(2)

This paper presents new time-dependent and time-independent multiplication algorithms over finite fields GF(2^m) by employing an interleaved conventional multiplication and a folded technique. The proposed algorithm allows efficient realization of the bit-parallel systolic multipliers. The results show that the proposed time-independent multiplier saves about 54% space complexity as compared to other related multipliers for polynomial and dual bases of GF(2^m). The proposed architectures include the features of regularity, modularity and local interconnection. Accordingly, it is well suited for VLSI implementation.     

Bistability and electrical activity of the vacancy-dioxygen complex in silicon

The methods of infrared absorption. Hall effect, and deep-level transient spectroscopy are used to study the complexes that consist of a vacancy and two oxygen atoms (the vacancy-dioxygen complexes, VO₂) in irradiated n-Si crystals with various levels of doping. The previously observed bistability of VO₂ is confirmed and evidence is provided for electrical activity of this defect in the metastable configuration VO*₂. It is established that the defect with this configuration features an acceptor level located at E _C ? 0.06 eV. It is shown that the absorption bands at 967 and 1023 cm^?1 are caused by the negatively charged VO*₂ state, while the bands peaking at 928 and 1004 cm^?1 correspond to the neutral charge state of the defect.