Design of a process-tolerant cell library for regular structuresusing symbolic layout and hierarchical compaction

A method to design cell libraries for macrocell layouts, which are constructed as an array of cells, is discussed. It is based on symbolic layout and a hierarchical compaction algorithm. This algorithm provides automatic terminal fitting and compacts cells in such a way that translated and mirrored cells are kept identical. The cells can be changed with a set of parameters by a macrocell generator. The compaction technique then guarantees that no design-rule errors occur for any combination of the parameter values. The method also allows easy adaptability to circuit techniques and layout rules. It can be applied to all regular hierarchical layout structures where constrained cells have to be designed. Once the library is established its cells can be used over and over again with different personality matrices for fast generation of correct layout     

层次版图连接关系提取

本文提出了一种新的层次版图连接关系提取算法,其利用投影法和版图倒序树(Inverse Layout Tree,简记为ILT)构建同一原始图形在不同层次单元之间的关联,并在基于边的扫描线算法的基础上利用组合器的方法建立版图数据的正确连接.此算法能够极好的保持版图中原有的层次,在此算法基础上进行的层次网表提取能够使层次LVS得到最大程度的支持;同时,算法具有很高的效率,只需占用很少的资源.目前,九天EDA系列工具中的层次版图验证工具已经采用此算法.     

A technology-independent approach to custom analog cell generation

STAT (schematic to artwork transistor), a set of software tools designed to generate full-custom layouts of analog cells from arbitrary schematic topologies in any IC technology, is described. The system enables the circuit designer to annotate the schematic with component matching and symmetry relationships. Software subroutines are then used to generate device artwork. The placement program implements algorithms in which groups of related components are placed first so that annotated layout constraints are preserved. A novel placement method is offered which recognizes that analog schematic topologies often reflect desirable layout configurations. A flexible multilayer cell-level router has been developed to complete the device interconnection. The STAT system functions in either a polygon or symbolic layout environment. The symbolic layout allows design-rule and technology changes to be made easily and is designed to interface with a commercial compaction program to produce the final layout     

A C-T filter compiler - from specifications to layout

This paper presents an analog Design Automation tool implemented within the Cadence Edge system, using the Cadence programming language Skill and other useful Cadence tools. Given standard filter specifications, the tool generates Continuous-Time filter blocks implementing the desired function. A numerical optimization technique is used to cancel response errors, introduced by the non-ideal circuit elements available for real filter realizations. Except for an operational amplifier which must be provided by the user, component layout is performed by dedicated module generators, and the final filter layout is assembled using the Cadence Edge place & route program. In the current version of the program, the only available filter topology is the MOSFET-C topology. However, an hierarchical, object oriented approach is adopted, in order to ensure reusability and extensibility of the tool. Each general aspect of a filter design is accessed through a uniform interface from the higher level of hierarchy, allowing dedicated procedures depending on the particular implementation to deal with the details, without affecting the workings of the tool at the higher level of hierarchy.     

基于SKILL语言的按比例自动缩放版图方法

使用程序自动缩放版图设计实现硬核的快速工艺移植。版图中对象位置和形状由点的序列构成,对各点乘以相同的缩放因子可以在不改变对象形状的前提下对任意形状对象进行缩放或位置搬移。基于此原理采用建立函数库的方法构建程序,使用递归算法处理层次化的版图并给出编程修改DRC错误的实例。在给出SKILL程序实现的基础上给出了一个完整的设计流程。实践结果显示设计时间缩短、硬核性能得到提高,面积缩小48％,门延时缩短40％。     

Fully integrated standard cell digital PLL

A fully integrated digital phase-locked loop (PLL) used as a clock multiplying circuit is designed. The PLL is made from standard cells found in almost any commercial standard cell library and therefore portable between processes in netlist format. Using a 0.35 μm standard complementary metal-oxide-semiconductor CMOS process and a 3.0 V supply voltage, the PLL is designed for a locking range of 170 to 360 MHz and occupies an on-chip area of 0.06 mm²     

3V/5V标准单元混合使用的芯片设计

讨论了 0 .9μm标准单元正向设计流程中当电路中存在 5 V和 3 V两种电压时芯片的设计方法 ,包括网表产生与验证 ,版图设计 ,电压转换单元的加入原则。     

Wavemaker in the design of GaAs MMICs

WaveMaker started out as a GaAs MMIC layout editing software package, to which was added a layout capture and schematic capture facility to enable the user to create netlist files in the Touchstone and Super Compact. The next step was to add the circuit simulator, and this has recently been completed with version 3.0 of WaveMaker.     

用Calibre工具对FFT芯片进行物理验证

FFT芯片在Astro工具中版图设计一旦完成,必须进行设计规则检查以确保版图设计的正确性。违反规则的版图设计将成为电路生产的隐患,因此,必须在sign-off之前检查出并改正。介绍了如何使用Mentor公司Calibre工具对Astro工具导出FFT芯片的GDSⅡ文件进行设计规则检查、天线规则检查、电学规则检查和版图与电路图一致性检查,并对检查中出现的问题提出相应的解决办法。     

Lossless Compression Algorithms for Hierarchical IC Layout

An important step in today's integrated circuit (IC) manufacturing is optical proximity correction (OPC). While OPC increases the fidelity of pattern transfer to the wafer, it also significantly increases IC layout file size. This has the undesirable side effect of increasing storage, processing, and I.O. times for subsequent steps of mask preparation. In this paper, we propose two techniques for compressing layout data, including OPC layout, while remaining compliant with existing industry standard formats such as OASIS and GDSII. Our approach is to eliminate redundancies in the representation of the geometrical data by finding repeating groups of geometries between multiple cells and within a cell. We refer to the former as ldquointercell subcell detection (InterSCD)rdquo and the latter as ldquointracell subcell detection (IntraSCD).rdquo We show both problems to be nondeterministic polynomial time hard (NP-hard), and propose two sets of heuristics to solve them. For OPC layout data, we also propose a fast compression method based on IntraSCD which utilizes the hierarchical information in the pre-OPC layout data. We show that the IntraSCD approach can also be effective in reconstructing hierarchy from flattened layout data. We demonstrate the results of our proposed algorithms on actual IC layouts for 90-nm, 130-nm, and 180-nm feature size circuit designs.     

垂直腔体面发射激光器等效电路模型在SPICE下的实现

介绍了一个基于速率方程的垂直腔体面发射激光器(VCSEL)的等效电路模型,该模型在电路模拟程序Pspice下得到了实现,其仿真结果与实验数据十分吻合。用C语言编写了一个可以自动生成VCSEL宏模型的网表自动生成器。     

锁相环小数N分频频率综合器中的Sigma-delta调制器设计

介绍了一种应用于小数N分频频率综合器的工作于20 MHz的Sigma-delta调制器的设计,采用3个一阶电路级联的MASH1-1-1结构的噪声整形电路。电路设计利用Verilog硬件描述语言进行描述,在modelSim SE 6.2b中通过了功能仿真,并在XUP Virtex-II Pro FPGA开发板上进行了验证,最终采用TSMC 0.13μm CMOS工艺,完成了电路版图并通过了DRC和LVS验证。芯片面积为180μm×160μm,平均功耗为1.059 6~1.070 4 mW。     

分级式设计规则检查的实用化研究

针对分级式设计规则检查的实用化所面临的一系列问题，如效率问题，伪错问题以及进一步优化等。分析限产生这些问题的原因和版图的结构特点，提出了上应的解决方案和改进措施。     

一个电路版图自动设计系统

本文描述一个电路版图的自动设计系统。它将具有高级设计描述的模块分解成规模较小、易处理的单元，通过对单元进行平面规划、合理安置和多次转换后，自动地产生这些单元版图的ＣＩＦ文件。这是一个完全自动地将高级设计描述的电路转换成电路几何描述的过程．     

一种中频接收电路的版图设计

利用Cadence版图设计工具采用B300工艺对一种中频接收电路芯片的版图设计实例,阐述了模拟集成电路版图的设计过程,论述了包括单元库建立、布局、布线、设计规则检查（DRC）和版图对照原理图检查（LVS）等在内的设计步骤以及进行每一步骤的具体方法,尤其对布局和布线这样的关键步骤进行了重点讨论。最后给出了完整的芯片版图。