Electrical reliability of highly reliable 256M-bit mobile DRAM with top-edge round STI and dual gate oxide

A novel CMOS fabrication process with a dual gate oxide (NDGO, thin oxide 5.0 nm, thick oxide 7.8 nm) and a shallow trench isolation (STI) top-edge rounded by a pad oxide undercut was developed for a 256M-bit mobile dynamic random access memory (DRAM) with V_D=1.8 V. We present a comprehensive study on the I–V characteristics and the long-term reliability of CMOSFET fabricated by NDGO process, and compared these characteristics with those of conventional single gate oxide transistors with a gate oxide thickness 5.0–7.5 nm. While thin oxide nMOSFET have a threshold voltage of nMOSFET (V_thn) of between 0.70 and 0.72 V and a saturation current (I_DSAT) of between 280 and 300 μA/μm, thick oxide nMOSFET have a V_thn of between 0.85 and 0.90 V and an I_DSAT of between 160 and 200 μA/μm in NDGO process due to a difference in the gate oxide thickness at similar boron doses. A 10 year lifetime of thick oxide cell transistors is projected for a V_g=8.9 V due to an electrical stress release at the STI top-edge round improved by the pad oxide undercut. The hot carrier lifetime and hot electron induced punchthrough also showed good characteristics. Consequently, this NDGO process is able to provide a reliable transistor performance for a 256M-bit mobile DRAM operating at low power.     

Evaluation of SiGe:C HBT intrinsic reliability using conventional and step stress methodologies

The reliability of SiGe:C HBT devices fabricated using the Freescale’s 0.35-μm RF-BICMOS process was evaluated using both conventional and step stress methodologies. This device technology was assessed to determine its capability for various power amplifier applications (e.g., WLAN, Bluetooth, and cellular phone), which are more demanding than conventional circuit designs. The step stress method was developed to allow a rapid evaluation of product reliability, as well as, a quick method to monitor product reliability. For all tests the collector current I_C and collector voltage V_C were kept constant throughout the test, and the current gain β (I_C/I_B) was continuously monitored. The nominal bias condition was V_C = 3.5-V and J_C = 50-kA/cm² (or 0.5-mA/μm²). The “failure criterion” for all reliability evaluations was −10% degradation in β from the initial value at the start of each stress test or interval. The median time to failure (MTTF) at a junction temperature (T_JCN) of 150 °C for the conventional stress test was 1.86E6-h, and the thermal activation energy was 1.33-eV. In contrast for the temperature step stress tests the combined results gave an MTTF at T_JCN = 150 °C of 5.2E6-h and a thermal activation energy of 1.44-eV. Considering the differences in the two test methods, these results are quite close to one another. The intrinsic reliability of this device at the nominal bias condition and T_JCN = 150 °C is more than adequate for a 5-year system life.     

Impact of gate oxide nitridation process on 1/f noise in 0.18 μm CMOS

The aim of this paper is to study the impact of the nitridation techniques on the 1/f noise performances of dual gate 0.18 μm CMOS transistors. Nitrogen is often introduced to prevent boron penetration in ultrathin oxides especially when BF₂ is used for the PMOS junction implantation, but as a result the MOS transistor exhibits higher 1/f noise because of the increased fixed trap density. We show how the nitridation process can be improved in terms of 1/f noise characteristics, in a fully integrated technology. Projections of the 1/f noise behaviour for different technologies are also shown, to emphasise how the 1/f noise becomes an issue when other downscaling properties are considered for analog/RF CMOS applications.     

A high performance pMOSFET with two-step recessed SiGe-S/D structure for 32 nm node and beyond

A novel SiGe-S/D structure for high performance pMOSFET called two-step recessed SiGe-source/drain (S/D) is developed with careful optimization of recessed SiGe-S/D structure. With this method, hole mobility, short channel effect and S/D resistance in pMOSFET are improved compared with conventional recessed SiGe-S/D structure. To enhance device performance such as drain current drivability, SiGe region has to be closer to channel region. Then, conventional deep SiGe-S/D region with carefully optimized shallow SiGe SDE region showed additional device performance improvement without SCE degradation. As a result, high performance 24 nm gate length pMOSFET was demonstrated with drive current of 451 μA/μm at V_dd of 0.9 V and I_off of 100 nA/μm (552 μA/μm at V_dd of 1.0 V). Furthermore, by combining with V_dd scaling, we indicate the extendability of two-step recessed SiGe-S/D structure down to 15 nm node generation.     

Effects of the electrical stress on the conduction characteristics of metal gate/MgO/InP stacks

The degradation dynamics and post-breakdown current–voltage (I–V) characteristics of magnesium oxide (MgO) layers grown on n and p-type indium phosphide (InP) substrates subjected to electrical stress were investigated. We show that the current–time (I–t) characteristics during degradation can be described by a power-law model I(t) = I₀t^−α, where I₀ and α are constants. It is reported that the leakage current associated with the soft breakdown (SBD) failure mode follows the typical voltage dependence I = aV^b, where a and b are constants, for both injection polarities but in a wider voltage range compared with the SiO₂/Si system. It is also shown that the hard breakdown (HBD) current is remarkably high, involving large ON–OFF fluctuations that resemble the phenomenon of resistive switching previously observed in a wide variety of metal oxides.     

Study of passivation defects by electroluminescence in AlGaN/GaN HEMTS on SiC

This paper presents a new method of passivation control by electroluminescence (EL) in 0.15 μm AlGaN/GaN HEMT. The electroluminescence signature in one finger HEMTs (W = 1 × 100 μm), and eight fingers ones (W = 8 × 125 μm), is modified by defects located at the passivation/semiconductor interface and is characterized by a light emission along the drain contact. This abnormal emission reveals some modification of the electric field distribution in the gate-drain space probably induced by traps located at the passivation/semiconductor interface. These traps contribute to the creation of a virtual gate in the gate-drain space.     

1.54 μm Near-infrared photoluminescent and electroluminescent properties of a new Erbium (III) organic complex

The crystal structure of Er(PM)₃(TP)₂ [PM = 1-phenyl-3-methyl-4-isobutyryl-5-pyrazolone, TP = triphenyl phosphine oxide] was reported and its photoluminescence properties were studied by UV–vis absorption, excited, and emission spectra. The Judd–ofelt theory was introduced to calculate the radiative transition rate and the radiative decay time of 3.65 ms for the ⁴I_13/2 → ⁴I_15/2 transition of Er³⁺ ion in this complex. The antenna-effect and phonon-assisted energy-transfer were introduced to discuss the intramolecular energy transfer from ligands to Er³⁺ ion. Based on this Er(III) complex as the emitter, the multilayer phosphorescent organic light emitting diode was fabricated with the structure of ITO/NPB 20 nm/Er(PM)₃(TP)₂ 50 nm/BCP 20 nm/AlQ 40 nm/LiF 1 nm/Al 120 nm, which shows the typical 1.54 μm near-infrared (NIR) emission from Er³⁺ ion with the maximum NIR irradiance of 0.21 μW/cm².     

Evaluation of displacement rate effect in shear test of Sn–3Ag–0.5Cu solder bump for flip chip application

An experimental investigation was combined with a non-linear finite element analysis using an elastic–viscoplastic constitutive model to study the effect of ball shear speed on the shear forces of flip chip solder bumps. A solder composition used in this study was Sn–3mass%Ag–0.5mass%Cu. A low cost bumping process has been employed using electroless Ni and immersion Au followed by solder paste stencil printing. A thin layer of intermetallic compound, (Ni_1−xCu_x)₃Sn₄, was formed by the reaction between the solder and electroless Ni with a thickness of about 1.4 μm, while some discontinuous (Cu_1−yNi_y)₆Sn₅ particles were also formed at the interface. The compositions of the resulting compounds were identified using energy dispersive spectrometer (EDS) and electron microprobe analysis (EPMA). Shear tests were carried out over a shear speed range from 20 to 400 μm/s at a shear ram height of 20 μm. The shear force was observed to linearly increase with shear speed and reach the maximum value at the fastest shear speed in both experimental and computational results. The optimum shear speeds for the shear test of solder bumped flip chip were recommended to be not exceeding 200 μm/s. The failure mechanisms were discussed in terms of von Mises stresses and plastic strain energy density distributions.     

High breakdown voltage Schottky rectifier fabricated on bulk n-GaN substrate

Vertical Schottky rectifiers have been fabricated on a free-standing n-GaN substrate. Circular Pt Schottky contacts with different diameters (50 μm, 150 μm and 300 μm) were prepared on the Ga-face and full backside ohmic contact was prepared on the N-face by using Ti/Al. The electron concentration of the substrate was as low as 7 × 10¹⁵ cm⁻³. Without epitaxial layer and edge termination scheme, the reverse breakdown voltages (V_B) as high as 630 V and 600 V were achieved for 50 μm and 150 μm diameter rectifiers, respectively. For larger diameter (300 μm) rectifiers, V_B dropped to 260 V. The forward turn-on voltage (V_F) for the 50 μm diameter rectifiers was 1.2 V at the current density of 100 A/cm², and the on-state resistance (R_on) was 2.2 mΩ cm², producing a figure-of-merit (V_B)²/R_on of 180 MW cm⁻². At 10 V bias, forward currents of 0.5 A and 0.8 A were obtained for 150 μm and 300 μm diameter rectifiers, respectively. The devices exhibited an ultrafast reverse recovery characteristics, with the reverse recovery time shorter than 20 ns.     

Integrating thick copper/Black Diamond™ layer in CMOS interconnect process for RF passive components

Thick copper (Cu)/Black Diamond™ (BD) layer up to 4 μm has successfully been integrated in CMOS interconnect process to improve the quality of on-chip RF passive components. It is shown that BD film is easy to crack when its thickness is up to 4 μm. However, by inserting one or few layers of dielectric material, BloK™, the stress in the entire dielectric film stack can be reduced. Although the reduction of the tensile stress of the stack is insignificant, the inserted BloK™ layer effectively prevents cracking from happening in the film stack. Spiral inductors have been integrated in developed Cu/BD (4 μm) top-metal-layer. Both Q value and resonate frequency of developed inductors are improved comparing to the inductors fabricated in previous top-metal-layer with 1 μm Cu/SiO₂ stack.     

Aging of the over-voltage protection elements caused by over-voltages

The aim of this work is examining the influence of the number of the activation––over-voltage pulses to the aging of over-voltage protection elements. Both non-linear (gas-filled surge arresters (GFSA), varistors, over-voltage diodes) and linear (capacitors––constituents of filters) over-voltage protection elements were tested. The instruments employed allow reliable measurements, 1000 consecutive activation were tested. The double-exponential current pulse (amplitude I₁^max=13 A, I₂^max=16 A, rise time T₁=8 μs, fall time T₂=20 μs) for non-linear elements and a double-exponential over-voltage pulse (rise time T₁=1.2 μs, fall time T₂=50 μs) of the amplitude U₁^max=320 V, U₂^max=480 V and U₃^max=640 V for capacitors were used. The experimental results show that the over-voltage diodes are the most reliable elements in view of characteristic modifications that are consequence of aging. However, it was observed that varistors, GFSA and capacitors undergo noticeable changes in characteristics.     

Organic thin film transistors with HfO2 high-k gate dielectric grown by anodic oxidation or deposited by sol–gel

We report here on pentacene based organic field effect transistors (OFETs) with a high-k HfO₂ gate oxide. HfO₂ layers were prepared by two different methods: anodic oxidation and sol–gel. A comparison of the two processes on the electrical properties of OFETs is given. Ultra thin nanoporous (20 nm) sol–gel deposited oxide films were obtained following an annealing at 450 °C. They lead to high mobility and stable devices (μ = 0.12 cm²/V s). On the other hand, devices with anodic HfO₂ revealed a little bit more leaky and show some hysteresis. Anodization, however, presents the advantage of being a fully room temperature process, compatible with plastic substrates. Stability and response to a bias stress are also reported.     

Fabrication of suspended thin film resonator for application of RF bandpass filter

Characteristics of AlN thin film and thin film resonator for RF bandpass filter have been studied. AlN thin films were deposited by RF magnetron sputter system. Deposition parameters such as N₂ contents, Ar and N₂ partial pressures, and the distance between metal target and substrate were found to affect the piezoelectric response. To fabricate the suspended thin film resonator (STFR) using the piezoelectric AlN thin film, the etching of AlN and the surface micromachining process were conducted. The thickness of AlN film and membrane for the STFR are 2 and 15 μm, respectively. This membrane was fabricated by SOI technology. The device with the dimension of 160 × 160 μm² has a resonant frequency of 1.653 GHz, a K_eff² of 2.4%, a bandwidth of 17 MHz, and a quality factor of 91.7. The device with the dimension of 200 × 200 μm² has a resonant frequency of 1.641 GHz, a K_eff² of 1.2%, and a bandwidth of 9 MHz, and a quality factor of 50.2.     

Improved electrical properties using SrTiO3/Y2O3 bilayer dielectrics for MIM capacitor applications

In this paper, we show that the capacitance–voltage linearity of MIM structures can be enhanced using SrTiO₃ (STO)/Y₂O₃ dielectric bilayers. The C(V) linearity is significantly improved by combining two dielectric materials with opposite permittivity-voltage responses. Three STO/Y₂O₃ stacks with different thicknesses were realized and compared to a 20 nm STO single layer structure. We observed that an increase in the Y₂O₃ thickness leads to an improvement in the voltage linearity, while maintaining an overall capacitance density greater than 10 fF/μm².     

Influence of the manufacturing process on the electrical properties of thin (<4 nm) Hafnium based high-k stacks observed with CAFM

In this work, the dependence of the electrical characteristics of some thin (<4 nm) HfO₂, HfSiO and HfO₂/SiO₂ stacks on their manufacturing process is studied at the nanoscale. Topography, current maps and current–voltage (I–V) characteristics have been collected by conductive atomic force microscope (CAFM), which show that their conductivity depends on some manufacturing parameters. Increasing the annealing temperature, physical thickness or Hafnium content makes the structure less conductive.     

Low and high temperature device reliability investigations of buried p-channel MOSFETs of a 0.17 μm technology

The hot carrier degradation of buried p-channel MOSFETs of a 0.17 μm technology is assessed in the temperature range between −40°C and 125°C. Within this temperature range, the degradation of the electrical parameter is investigated for different drain voltages and channel lengths (0.2–0.3 μm) in the gate voltage range between V_GS=0 V and V_GS=V_DS. The analysis of the experimental results is presented and the physical processes responsible for the observed degradation at different stress conditions are discussed by reviewing previous works. Based on hot carrier modelling and lifetime extrapolation to operating conditions the stressing voltage conditions are analysed. For the experimentally investigated temperature range the worst case stress condition is identified at low temperatures for gate voltage at the maximum of the gate current (I_Gmax). In the case of V_GS corresponding to I_Gmax two activation energies are determined for low and high temperatures. For temperatures above 125°C the worst case bias condition changes from V_GS=V_GS@I_Gmax to V_GS=V_DS.     

On the geometrical dependence of low-frequency noise in SiGe HBTs

We present an investigation of the dependence of low-frequency noise on device geometry in advanced npn silicon–germanium (SiGe) heterojunction bipolar transistors (HBTs). The devices examined in this work have fixed emitter width (W_E = 0.4 μm), but varying emitter length (0.5 μm  L_E  20.0 μm), and thus the ratio of the emitter perimeter (P_E) to the emitter area (A_E) varies widely, making it ideal for examining geometrical effects. The SPICE noise parameter A_F extracted from these devices decreases with increasing L_E. Furthermore, the low-frequency noise measured on SiGe HBTs with significantly different P_E/A_E ratios suggests a possibility that the fundamental noise source for the diffusion base current may be located at the emitter periphery. Transistors with different distances between the emitter edge and the shallow trench edge (XEC), and shallow trench edge to deep trench edge (XTC), are also investigated. The SiGe HBTs with a smaller value of XEC have higher low-frequency noise, but no significant difference is found in devices with varying XTC. Explanations of the observed noise behavior are suggested.     

Correlating gate sinking and electrical performance of pseudomorphic high electron mobility transistors

Ti interdiffusion from the Ti/Pt/Au gate into the AlGaAs Schottky barrier layer (SBL) of 0.25-μm GaAs Pseudomorphic High Electron Mobility Transistors (PHEMTs) has been studied using the accelerated life testing technique. Based on measurements and modeling, analytical expressions for quantitative correlation between the positive pinch-off voltage (V_P) shift as well as the saturation drain current (I_Dsat) decrease and the physical damage occurring during gate sinking has been developed. It is suggested that the main cause for device failure is the growth of the TiAs phase leading to the decrease in the SBL thickness. Additionally, it is suggested that V_P may be used as a better indicator for device degradation than I_Dsat since it is linearly proportional to the degrading physical characteristic – the Schottky barrier layer thickness.     

Modeling of the body current in a Bi-MOS hybrid-mode environment

The body current I_B of deep submicron lightly doped drain pMOSFETs has been investigated. Based on the experimental results, an analytical I_B model, applicable for devices operating in a Bi-MOS hybrid-mode environment, has been developed for the first time. The proposed model is able to effectively characterize the measured I_B results over a wide range of independently applied biases (gate, drain and body) and gate lengths (from 1 μm down to 0.25 μm). The possibility of minimizing or even eliminating the undesired I_B is also explored and discussed for the first time.     

MOCVD of ferroelectric thin films

A low-pressure chemical vapor deposition system for growing ferroelectric thin PZT films has been developed. It consists of a dispensing and vaporizing system for up to four liquid metal precursors and a cold wall reactor, where the reactions are carried out at pressures below 1 Torr and at temperatures between 330 and 500°C. The thickness of the deposited films ranged from 10 nm to 1 μm. The investigated films in this report are lead-titanate, PbTiO₃, and lead-zirconate-titanate, Pb(Zr,Ti)O₃.