Bipolar transistor selected P-channel flash memory cell technology

A novel BIpolar Transistor Selected (BITS) P-channel flash memory cell is proposed, where a bipolar transistor embedded in the source region of the cell amplifies cell-read-current and acts as a select transistor. With this cell, not only a very low 1.5 V non-word-line-boosting read operation, but also a sector-erase operation are successfully achieved with only a small cell-size increase over the conventional NOR cell. Moreover, this cell technology maintains all the advantages of the P-channel DIvided-bit-line NOR (DINOR) flash memory     

GaAs/AlGaAs dynamic random access memory cell

A single-transistor dynamic random access memory circuit using a GaAs/AlGaAs structure as the storage cell and modulation-doped field-effect transistors for memory accessing and output sensing has been developed. The functionality of the memory is demonstrated and a storage time of 5.4s is measured at room temperature.<>     

A dynamic three-state memory cell for high-density associativeprocessors

A dynamic associative processor cell is described. The cell stores three states (0, 1, and X) and performs read, match, and masked-write functions. Five MOS transistors are used, including two overlapping dual-gate structures available in MIT's CCD/CMOS technology. Dual-gate CCD transistors are used to reduce the charge-spooning current, which can discharge the storage node through the write transistors. The use of the cell in an associative processor is described, and experimental results are presented     

A novel dynamic memory cell with internal voltage gain

A 2T1D dynamic memory cell with two transistors (T) and a gated diode (D) is presented. A gated diode is a two terminal MOS device in which charge is stored when a voltage above the threshold voltage is applied between the gate and the source, and negligible charge is stored otherwise. The gated diode acts as a nonlinear capacitance for voltage boosting, where voltage for 1-data is boosted high and voltage for 0-data stays low, achieving significant voltage gain of the internal stored voltage, higher signal margin, higher current drive and low-voltage memory operation. Details about the gated diode structure, its signal amplification, the memory cell circuits and the array structure, some hardware and test results are presented, followed by comparison to other memory cells and future directions.     

Bipolar switching characteristics of low-power Geo resistive memory

We reported an ultra low-power resistive random access memory (RRAM) combining a low-cost Ni electrode and covalent-bond GeO_x dielectric. This cost-effective Ni/GeO_x/TaN RRAM device has very small set power of 2 μW, ultra-low reset power of 130 pW, greater than 1 order of magnitude resistance window, and stable retention at 85 °C. The current flow at low-resistance state is governed by Poole-Frenkel conduction with electrons hopping via defect traps, which is quite different from the filament conduction in metal-oxide RRAM.     

A new extension method of retention time for memory cell on dynamic random access memory

Demands have been placed on dynamic random access memory (DRAM) to not only increase memory capacity and data transfer speed but also to reduce operating and standby currents. When a system uses DRAM, the restricted data retention time necessitates a refresh operation because each bit of the DRAM is stored as an amount of electrical charge in a storage capacitor. Power consumption for the refresh operation increases in proportion to memory capacity. A new method is proposed to reduce the refresh power consumption dynamically, when full memory capacity is not required, by effectively extending the memory cell retention time. Conversion from 1 cell/bit to 2^N cells/bit reduces the variation of retention times among memory cells. The proposed method reduces the frequency of disturbance and power consumption by two orders of magnitude. Furthermore, the conversion itself can be realized very simply from the structure of the DRAM array circuit, while maintaining all conventional functions and operations in the full array access mode.     

A substrate-plate trench-capacitor (SPT) memory cell for dynamic RAM's

A (dynamic random-access memory) DRAM cell using a trench capacitor with a grounded substrate plate has been demonstrated, fabricated of functional fully decoded 64K arrays. The cell array is located inside the well and the trench capacitor extends from the planar surface through the well and epitaxial layer into the heavily doped substrate. The polysilicon inside the trench, connected to the source region of the transfer device, is used as the storage node and the bulk silicon surrounding the trench serves as the capacitor plate electrode. The cell features small area, high capacitance, small leakage current, low soft error rate, reduced surface topography, and a very stable capacitor-plate electrode. The arrays were fabricated in an advanced, 3.3-V, n-well epitaxial CMOS technology with a 15-nm gate insulator. The n- and p-channel transistors, exhibit transconductances of 120 and 650 mS/mm, respectively, at effective channel lengths of 6.0 /spl mu/m. Ring oscillators designed at this length have delays of 170 ps at 3.3 V.     

GaAs dynamic memory design

Subthreshold leakage loss is a serious problem for GaAs dynamic memory. Since the leakage current in a MESFET is several orders of magnitude higher than that in a MOSFET, it is difficult to retain the charge at dynamic nodes resulting in data storage errors, In order to solve this problem, a novel DRAM architecture is proposed. The design is based on a cell consisting of a MESFET switch and a metal-insulator-metal (MIM) planar capacitor as the storage element. The leakage current is reduced by a level-shift technique and a self-biased transistor is used to maintain the dynamic charge during the sense period. A high performance sense amplifier is used to detect small bit line voltage changes and refresh the stored data. A 1 Kb prototype, fabricated in a 1 μm nonself-aligned GaAs MESFET technology, exhibited a total read/write access time of the order of 3 ns     

A new dynamic random access memory cell using a bipolar MOS composite structure

A new dynamic random access memory (RAM) cell which incoperates an n-p-n bipolar junction transistor with an n-channel MOSFET in a composite structure, is proposed and investigated. In this novel cell called the BIMOS cell, the collector-base junction serves as a buried storage capacitor whereas the n-MOSFET as a transfer gate. The fabrication technology is simple and compatible with that of single-polysilicon CMOS IC's and a minimum cell size of 14.875F²with a minimum feature sizeFis realizable. The write, read, and standby operations of the cell are analyzed and simulated. An experimental cell is fabricated and characterized. Dynamic test is successfully performed. The investigation on the cell performance is also made. It has shown that large storage capacitance to bit-line capacitance ratio as well as fairly good packing density, soft-error immunity and leakage characteristics are expected. Furthermore, as compared to the conventional 1-transistor cell the new cell can be scaled down with less processing troubles and better performance improvements. Simple process and good scaled-down properties offer great potential for the proposed new cell to be used in the design of larger dynamic MOS RAM's.     

Bipolar resistive switching of chromium oxide for resistive random access memory

This study investigates the resistance switching characteristics of Cr₂O₃-based resistance random access memory (RRAM) with Pt/Cr₂O₃/TiN and Pt/Cr₂O₃/Pt structures. Only devices with Pt/Cr₂O₃/TiN structure exhibit bipolar switching behavior after the forming process because TiN was able to work as an effective oxygen reservoir but Pt was not. Oxygen migration between Cr₂O₃ and TiN was observed clearly before and after resistance switching from Auger electron spectroscopy (AES) analysis. Both low resistance state, ON state, and high resistance state, OFF state, of Pt/Cr₂O₃/TiN structures are stable and reproducible during a successive resistive switching. The resistance ratio of ON and OFF state is over 10², on top of that, the retention properties of both states are very stable after 10⁴ s with a voltage of −0.2 V.     

Analog dynamic random-access memory (ADRAM) unit cell implementedusing a CCD with feedback

A novel unit cell for analog, dynamic, random-access memory is described. The unit cell is implemented using a charge-coupled device (CCD) and features voltage-in/voltage-out operation with low power. The unit cell is essentially an algorithmic voltage sample-and-hold (S/H) circuit. It is sufficiently compact for imager frame memory application and may also find application in analog neural network circuits     

A vertically integrated dynamic RAM-cell: Buried bit line memory cell with floating transfer layer

A charge injection device has been realized in which charge can be injected on to an MOS-capacitor from a buried layer via an isolated transfer layer. The cell is positioned vertically between word and bit line. LOCOS (local oxidation) is used to isolate the cells and (deep) ion implantation to realize the buried bit line and transfer layer. This isolation prevents carriers from diffusing to neighbouring cells and hence preserves stored information. The device physics has been analysed using simulation programs and bipolar modelling. It is shown that this device can be used as a dynamic RAM-cell of extreme simplicity and potentially small cell size compared to conventional DRAM cells.     

A 256K dynamic random access memory

A 5 V 256K/spl times/1 bit NMOS dynamic RAM employing redundancy is described. Using 2.3 /spl mu/m design rules, the cell is laid out in a folded bit line configuration having a row pitch of 6.5 /spl mu/m and a sense-amplifier pitch of 18 /spl mu/m. Tantalum silicide/polysilicon is used as the second polysilicon level to reduce the row line time constant. A storage capacitance of 60 fF and the Hi-C cell structure provides this memory with high alpha-particle insensitivity. The die measures 4.66/spl times/11.65 mm, and fits into a standard 0.3 in wide 16-pin DIP. The memory operates with 256 refresh cycles with a 4 ms refresh time. Typical RE/CE access times are 105/45 ns with an active power dissipation of 250 MW. Typical standby power is less than 20 mW. The part is compatible with the present Western Electric 5 V 64K part.     

A 4K MOS dynamic random-access memory

Presents one version of a 4K dynamic MOS random-access memory utilizing a 3 device/bit cell with an area of less than 2 mil/SUP 2//b, which is fabricated using an n-channel silicon gate MOS technology. The chip requires only a single phase clock and internally generates the multiphase timing required. Other than the single high voltage clock, all inputs and the output are TTL compatible.     

A fault-tolerant 64K dynamic random-access memory

A 64K dynamic MOS RAM with features and performance fully compatible with current 16K RAM's has been designed and characterized. The memory cell is a one-transistor-one-capacitor structure, standard except for a polysilicon bit line. A dual-32K architecture, along with partial selection and stepped recovery, holds power and peak current values below those of 16K parts. Spare rows and columns, which can be substituted for defective elements by the laser opening of polysilicon links, enhance yield. Worst case column enable access time of the memory is 100 ns, row enable access time is 170 ns, and only 128 cycles within 4 ms are needed to refresh the device.     

Soft-error-immune switched-load-resistor memory cell

A soft-error-immune switched-load-resistor memory cell especially suitable for ultrahigh-speed bipolar RAM has been developed. The memory cell is composed of upward sidewall base contact structure (SICOS) transistors and shielded Schottky-barrier diodes (SBDs). Alpha-particle-induced noise charges generated in the p^--substrate are completely shielded by n⁺-buried layers of the transistors and the SBDs. Only the noise charges generated in the transistors or the SBDs active regions are gathered in the collectors of the memory cell. The maximum collected noise charge is reduced to a quarter of that of conventional memory cells using SICOS downward transistors and conventional SBDs. Experiments show that this reduction of the collected noise charge increases soft-error immunity to more than 10⁵ times that of conventional memory cells. This result using hot radiation sources does not directly correspond to the real soft-error rate in the field, but demonstrates the realization of an ultrahigh-speed soft-error-immune memory cell     

The twin-port memory cell

A novel full-CMOS six-transistor memory cell that provides uncontested and overlapped two-port read accesses to one-cell, and concurrent READ/WRITE operations to separate cells, has been designed and functional test circuits is fabricated. This twin-port cell is based on the traditional cross-coupled inverter, but with a versatile access scheme. Balanced differential access transistors have given way to independent and complementary access transistors attached to a common readout node in the cell. Independent N-port and P-port word lines control the NMOS and PMOS access devices routing stored data to N and P bit lines, respectively. Each port has the potential of accessing a cell without interference from activities at other port even if addressing the same cell. This cell, with a complementary single bit line and access transistor per port structure, is only 11% larger than a similarly constructed conventional six-transistor single-port CMOS cell.     

Smallest p-n-p-n memory cell

Although the p-n-p-n device is suitable for a 1-bit/cell static mamory, it has not yet been put to practical use because of its large cell size. By employing a sophisticated process involving single-crystal/poly-Si simultaneous growth on the same substrate, the smallest-sized vertical p-n-p-n device has been developed. Using this cell structure, a 12-bit scanner with 21.2-MHz transfer frequency, 16-µm pitch and 10-µmW/bit power dissipation has been fabricated. This cell structure is also applied to a static RAM with 22 × 27 = 594 µm²cell size. A high switching speed as well as a high packing density is predicted by this configuration.     

Kinetic inductance memory cell

A Josephson memory cell based on kinetic inductance is proposed and analyzed. The size of the cells can be as small as 1/100 that of conventional superconducting memory cells. However, the kinetic inductance memory cell cannot utilize magnetically coupled read and write circuitry. The authors propose a current injected read/write architecture     

An on-chip back-bias generator for MOS dynamic memory

An on-chip back-bias generator for 64K dynamic MOS RAM has been developed.The use of this generator achieves the goal of a single 5 V power supply part while preserving the advantages of substrate bias in n-channel MOS technology. These advantages include the elimination of substrate injection current from localized forward biasing of diodes, improved speed and power characteristics, and a larger differential data signal on the bit sense lines. The generator circuit avoids several pit-falls on on-chip V/SUB BB/ generation. The circuit pumps to a known regulated voltage. This avoids substrate drift with changes in substrate current resulting from changes in cycle time. This drift will change device characteristics and degrade storage levels. A unique two-level reference scheme avoids changes in substrate bias voltage that otherwise result from the shift in V/SUB BB/ between precharged and active memory states when memory duty cycle changes. The standby power used by the generator is only 0.74 mW.