A 10 MS/s 11-bit 0.19 mm $^{2}$ Algorithmic ADC With Improved Clocking Scheme

A 10 MS/s 11-bit algorithmic ADC with an active area of 0.19$~{hbox{mm}}^{2}$ is presented. Using an improved clocking scheme, this design overcomes the speed limit of algorithmic ADCs. The proposed ADC employs amplifier sharing, DC offset cancellation, and input memory effect suppression, resulting in reduced area and power, and high linearity. The ADC implemented in a 0.13$~mu{hbox{m}}$ thick gate-oxide CMOS process achieves 69 dB SFDR, 58 dB SNR, and 56 dB SNDR, while consuming 3.5 mA from a 3 V supply.      

A 1-GHz signal bandwidth 6-bit CMOS ADC with power-efficient averaging

A 2-GS/s 6-bit ADC with time-interleaving is demonstrated in 0.18-/spl mu/m one-poly six-metal CMOS. A triple-cross connection method is devised to improve the offset averaging efficiency. Circuit techniques, enabling a state-of-the-art figure-of-merit of 3.5 pJ per conversion step, are discussed. The peak DNL and INL are measured as 0.32 LSB and 0.5 LSB, respectively. The SNDR and SFDR have achieved 36 and 48dB, respectively, with 4 MHz input signal. Near Nyquist input frequencies, the SNDR and SFDR maintain above 30 and 35.5dB, respectively, up to 941 MHz. The complete ADC, including front-end track-and-hold amplifiers and clock buffers, consumes 310 mW from a 1.8-V supply while operating at 2-GHz conversion rate. The prototype ADC occupies an active chip area of 0.5 mm/sup 2/.     

A 10-bit 400-MS/s 160-mW 0.13-/spl mu/m CMOS dual-channel pipeline ADC without channel mismatch calibration

This paper describes a 10-bit 400-MS/s dual-channel analog-to-digital converter (ADC) insensitive to offset, gain, and sampling-time mismatches between channels. An adaptive closed-loop sampling technique based on a multi-stage amplifier eliminates the channel offset effectively. Multi-stage amplifiers with high DC gain reduce the gain mismatch between channels and guarantee a large signal swing at low supply voltages. A single clock-edge sampling scheme for clock-skew reduction minimizes the sampling-time mismatch. The proposed prototype ADC in a 0.13-/spl mu/m CMOS process occupies an active area of 4.2mm/sup 2/, dissipates 160mW from 1.2 V and 400 MS/s, and shows a signal-to-noise-and-distortion ratio of 54.8 dB with a 29-MHz sinusoidal input at 400 MS/s without any channel-mismatch calibration technique. The measured maximum offset and gain mismatches are less than 0.1% and 0.2%, respectively.     

A 1.2-V 12-b 120-MS/s SHA-Free Dual-Channel Nyquist ADC Based on Midcode Calibration

This paper describes a 12-b 120-MS/s dual-channel pipeline analog-to-digital converter (ADC) for high-speed video signal processing. A simple digital midcode calibration technique is proposed to eliminate an offset mismatch between two channels. The proposed sample-and-hold-amplifier-free architecture with correlated input sampling networks enables wideband signal sampling while effectively reducing a gain mismatch between channels. The prototype ADC implemented in a 0.13-$mu{hbox {m}}$ CMOS technology achieves a peak signal-to-noise-and-distortion ratio of 61.1 dB and a peak spurious-free dynamic range of 74.7 dB for input frequencies up to 60 MHz at 120 MS/s. The measured differential and integral nonlinearities are within $pm 0.30$ LSB and $pm 0.95$ LSB, respectively. The ADC occupies an active die area of $0.56~{hbox {mm}}^{2}$ and consumes 51.6 mW at a 1.2 V power supply.      

A mismatch-error minimized four-channel time-interleaved 11 b 150 MS/s pipelined SAR ADC

This work proposes a four-channel time-interleaved 11 b 150 MS/s pipelined SAR ADC based on various analog techniques to minimize mismatches between channels without any calibration scheme. The proposed ADC eliminates an input SHA to reduce offset mismatches, while the pipelined SAR architecture solves the problem of limited input bandwidth as observed in conventional SHA-free ADCs. In addition, a shared residue amplifier between four channels minimizes various mismatches caused by amplifiers in the first-stage MDACs. Two types of references for the residue amplifier and the SAR ADCs isolate the reference instability problem due to different functional requirements, while the shared residue amplifier uses only a single reference during the amplifying mode of each channel to reduce a gain mismatch. For high performance of the SAR ADC, high-frequency clocks with a controllable duty cycle are generated on chip without external, complicated, high-speed multi-phase clocks. The prototype 11 b ADC in a 0.13 μm CMOS shows a measured DNL and INL of 0.31 LSB and 1.18 LSB, respectively, with an SNDR of 59.3 dB and an SFDR of 67.7 dB at 100 MS/s, and an SNDR of 54.5 dB and an SFDR of 65.5 dB at 150 MS/s. The ADC with an active die area of 2.42 mm² consumes 46.8 mW at 1.2 V and 150 MS/s.     

A 455 nW 220 fJ/conversion-step 12 bits 2 kS/s SAR ADC for portable biopotential acquisition systems

An ultra-low power 12 bits 2 kS/s successive approximation register analog-to-digital converter(ADC) is presented.For power optimization,the voltage supply of the digital part is lowered,and the offset voltage of the latch is self-calibrated.Targeted for better linearity and lower noise,an improved digital-to-analog converter capacitor array layout strategy is presented,and a low kick-back noise latch is proposed.The chip was fabricated by using 0.18μm 1P6M CMOS technology.The ADC achieves 61.8 dB SNDR and dissipates 455 nW only,resulting in a figure of merit of 220 fJ/conversion-step.The ADC core occupies an active area of only 674×639μm~2.     

A 10-b 120-Msample/s time-interleaved analog-to-digital converter with digital background calibration

Digital calibration using adaptive signal processing corrects for offset mismatch, gain mismatch, and sample-time error between time-interleaved channels in a 10-b 120-Msample/s pipelined analog-to-digital converter (ADC). Offset mismatch between channels is overcome with a random chopper-based offset calibration. Gain mismatch and sample-time error are overcome with correlation-based algorithms, which drive the correlation between a signal and its chopped image or its chopped and delayed image to zero. Test results show that, with a 0.99-MHz sinusoidal input, the ADC achieves a peak signal-to-noise-and-distortion ratio (SNDR) of 56.8 dB, a peak integral nonlinearity of 0.88 least significant bit (LSB), and a peak differential nonlinearity of 0.44 LSB. For a 39.9-MHz sinusoidal input, the ADC achieves a peak SNDR of 50.2 dB. The active area is 5.2 mm/sup 2/, and the power dissipation is 234 mW from a 3.3-V supply.     

A 1.8-V 67-mW 10-bit 100-MS/s pipelined ADC using time-shifted CDS technique

A time-shifted correlated double sampling (CDS) technique is proposed in the design of a 10-bit 100-MS/s pipelined ADC. This technique significantly reduces the finite opamp gain error without compromising the conversion speed, allowing the active opamp blocks to be replaced by simple cascoded CMOS inverters. Both high-speed and low-power operation is achieved without compromising the accuracy requirement. An efficient common-mode voltage control is introduced for pseudodifferential architecture which can further reduce power consumption. Fabricated in a 0.18-/spl mu/m CMOS process, the prototype 10-bit pipelined ADC occupies 2.5 mm/sup 2/ of active die area. With 1-MHz input signal, it achieves 65-dB SFDR and 54-dB SNDR at 100MS/s. For 99-MHz input signal, the SFDR and SNDR are 63 and 51 dB, respectively. The total power consumption is 67 mW at 1.8-V supply, of which analog portion consumes 45 mW without any opamp current scaling down the pipeline.     

A 6-bit 600-MS/s 5.3-mW Asynchronous ADC in 0.13-μm CMOS

An asynchronous analog-to-digital converter (ADC) based on successive approximation is used to provide a high-speed (600-MS/s) and medium-resolution (6-bit) conversion. A high input bandwidth (>4 GHz) was achieved which allows its use in RF subsampling applications. By using asynchronous processing techniques, it avoids clocks at higher than the sample rate and speeds up a nonbinary successive approximation algorithm utilizing a series nonbinary capacitive ladder with digital radix calibration. The sample rate of 600 MS/s was achieved by time-interleaving two single ADCs, which were fabricated in a 0.13-mum standard digital CMOS process. The ADC achieves a peak SNDR of 34 dB, while only consuming an active area of 0.12mm² and having power consumption of 5.3 mW     

A 0.9-V 12-mW 5-MSPS algorithmic ADC with 77-dB SFDR

An ultra-low-voltage CMOS two-stage algorithm ADC featuring high SFDR and efficient background calibration is presented. The adopted low-voltage circuit technique achieves high-accuracy high-speed clocking without the use of clock boosting or bootstrapping. A resistor-based input sampling branch demonstrates high linearity and inherent low-voltage operation. The proposed background calibration accounts for capacitor mismatches and finite opamp gain error in the MDAC stages via a novel digital correlation scheme involving a two-channel ADC architecture. The prototype ADC, fabricated in a 0.18 /spl mu/m CMOS process, achieves 77-dB SFDR at 0.9 V and 5MSPS (30 MHz clocking) after calibration. The measured SNR, SNDR, DNL, and INL at 80 kHz input are 50 dB, 50 dB, 0.6 LSB, and 1.4 LSB, respectively. The total power consumption is 12 mW, and the active die area is 1.4 mm/sup 2/.     

A 10-bit 50-MS/s subsampling pipelined ADC based on SMDAC and opamp sharing

This paper describes a 10-bit,50-MS/s pipelined A/D converter(ADC) with proposed area- and power-efficient architecture.The conventional dedicated sample-hold-amplifier(SHA) is eliminated and the matching requirement between the first multiplying digital-to-analog converter(MDAC) and sub-ADC is also avoided by using the SHA merged with the first MDAC(SMDAC) architecture,which features low power and stabilization.Further reduction of power and area is achieved by sharing an opamp between two successive pi...     

A Background Sample-Time Error Calibration Technique Using Random Data for Wide-Band High-Resolution Time-Interleaved ADCs

Sample-time error among the channels of a time-interleaved analog-to-digital converter (ADC) is the main reason for significant degradation of the effective resolution of the high-speed time-interleaved ADC. A calibration technique for sample-time mismatches has been proposed and implemented at a low level of complexity. The calibration method uses random data and is especially suitable for ADCs used in digital data communication systems. An 800-MS/s four-channel, time-interleaved ADC system has been implemented to evaluate the performance of the technique. The experimental results show that the spurious-free dynamic range of the ADC system is improved to 58.1 dB at 350 MHz. The ADC system achieves a signal-to-noise and distortion ratio of 59.6 dB at 5 MHz and 50.1 dB at 350 MHz after calibration.     

A 3.3-V, 10-b, 25-MSample/s two-step ADC in 0.35-μm CMOS

This paper describes the design of a two-step analog-to-digital converter (ADC). By using techniques such as improved switching and offset compensated amplifiers, the high-speed two-step architecture can be expanded toward high resolution. The ADC presented here achieves 9 ENOB with a spurious-free dynamic range of more than 72 dB, at a sample rate of 25 MSample/s. The ADC is realized in a 0.35-μm mainstream CMOS process without options such as double poly. It measures 0.66 mm ² and dissipates 195 mW from a 3.3-V power supply     

A sub-sampling 4-bit 1.056-GS/s flash ADC with a novel track and hold amplifier for an IR-UWB receiver

A sub-sampling 4-bit 1.056-GS/s flash ADC with a novel track and hold amplifier(THA) in 0.13μm CMOS for an impulse radio ultra-wideband(IR-UWB) receiver is presented.The challenge is in implementing a sub-sampling ADC with ultra-high input signal that further exceeds the Nyquist frequency.This paper presents,to our knowledge for the second time,a sub-sampling ADC with input signals above 4 GHz operating at a sampling rate of 1.056 GHz.In this design,a novel THA is proposed to solve the degradation in amplitude and improve the linearity of signal with frequency increasing to giga Hz.A resistive averaging technique is carefully analyzed to relieve noise aliasing.A low-offset latch using a zero-static power dynamic offset cancellation technique is further optimized to realize the requirements of speed,power consumption and noise aliasing.The measurement results reveal that the spurious free dynamic range of the ADC is 30.1 dB even if the input signal is 4.2 GHz sampled at 1.056 GS/s.The core power of the ADC is 30 mW,excluding all of the buffers,and the active area is 0.6 mm~2.The ADC achieves a figure of merit of 3.75 pJ/conversion-step.     

A CMOS 15-bit 125-MS/s Time-Interleaved ADC With Digital Background Calibration

A 15-bit 125-MS/s two-channel time-interleaved pipelined ADC is fabricated in a 0.18 mum CMOS technology, and achieves 91.9 dB SFDR, 69.9 dB SNDR for a 9.99 MHz input. This ADC incorporates a single sample-and-hold amplifier which employs a precharged circuit configuration to mitigate performance requirements for its opamp. Digital background calibration is applied to maintain the conversion linearity of each A/D channel and also correct both gain and offset mismatches between the two channels. Excluding I/O buffers, the chip occupies an area of 4.3 times 4.3 mm² and dissipates 909 mW from a 1.8 V supply.     

A 3-mW 74-dB SNR 2-MHz continuous-time delta-sigma ADC with a tracking ADC quantizer in 0.13-/spl mu/m CMOS

A third-order continuous-time multibit (4 bit) /spl Delta//spl Sigma/ ADC for wireless applications is implemented in a 0.13-/spl mu/m CMOS process. It is shown that the power consumption can be considerably reduced by using a tracking ADC composed of three comparators with interpolation instead of using a 4-bit flash quantizer. Moreover, the usage of a tracking ADC opens the door to a new forward-looking dynamic element matching (DEM) technique, which helps to reduce the loop delay time and consequently improves the loop stability. The SNR is 74 dB over a bandwidth of 2 MHz. The ADC consumes 3 mW from a 1.5-V supply when clocked at 104 MHz. The active area is 0.3 mm/sup 2/.     

A 5-b 10-GSample/s a/D converter for 10-gb/s optical receivers

A 5-b flash A/D converter (ADC) is developed in an 0.18-/spl mu/m SiGe BiCMOS that supports sampling rates of 10 Gsample/s. The ADC is optimized to operate in digital equalizers for 10-Gb/s optical receivers, where the ADC has to deliver over three effective number of bits (ENOBs) at Nyquist. A fully differential flash ADC incorporating a wide-band track-and-hold amplifier (THA), a differential resistive ladder, an interpolation technique, and a high-speed comparator design is derived to resolve the aperture jitter and metastability error. The ADC achieves better than 4.1 effective bits for lower input frequencies and three effective bits for Nyquist input at 10 GS/s. The ADC dissipates about 3.6 W at the maximum clock rate of 10 GS/s while operating from dual -3.7/-3V supplies and occupies 3/spl times/3mm/sup 2/ of chip area.     

An 87 fJ/conversion-step 12 b 10 MS/s SAR ADC using a minimum number of unit capacitors

This work proposes a 12 b 10 MS/s 0.11 μm CMOS successive-approximation register ADC based on a C-R hybrid DAC for low-power sensor applications. The proposed C-R DAC employs a 2-step split-capacitor array of upper seven bits and lower five bits to optimize power consumption and chip area at the target speed and resolution. A V_CM-based switching method for the most significant bit and reference voltage segments from an insensitive R-string for the last two least significant bits minimize the number of unit capacitors required in the C-R hybrid DAC. The comparator accuracy is improved by an open-loop offset cancellation technique in the first-stage pre-amp. The prototype ADC in a 0.11 μm CMOS process demonstrates the measured differential nonlinearity and integral nonlinearity within 1.18 LSB and 1.42 LSB, respectively. The ADC shows a maximum signal-to-noise-and-distortion ratio of 63.9 dB and a maximum spurious-free dynamic range of 77.6 dB at 10 MS/s. The ADC with an active die area of 0.34 mm² consumes 1.1 mW at 1.0 V and 10 MS/s, corresponding to a figure-of-merit of 87 fJ/conversion-step.     

A 1.8-V 3.1 mW successive approximation ADC in system-on-chip

This paper describes a 10-bit 2.5 Msample/s successive approximation analog-to-digital converter (ADC) for SoC system. Based on conventional successive approximation ADC architecture a new and faster solution is used. The new solution consists of bootstrap switch, capacitors for sample-hold (S/H) circuit and DAC, using an offset cancellation method and there is no need for any active element. Together with an added bit and an offset compensation comparator the speed and accuracy is increased. The ADC exhibits higher 9 effective number of bits (ENOB) for sample rate to 2.5 Ms/s. The ADC consumes 3.1 mW from a 1.8 V supply and occupies about 0.25 mm². The measured SNR is 56.05 dB.     

一款结合数字校正技术的流水线ADC设计

基于65 nm CMOS工艺、1.2 V供电电压,设计了一款结合偏移双通道技术的流水线模数转换器(analog-to-digital convertor,ADC)。芯片的测试结果表明,该校正方法有效地消除和补偿了电容失配、级间增益误差和放大器谐波失真对流水线ADC综合性能的制约。流水线ADC在125 MS/s采样率、3 MHz正弦波输入信号的情况下,信噪失真比(signal-and-noise distortionratio,SNDR)从校正前的28 dB提高到61 dB,无杂散动态范围(spurious-free dynamic range,SFDR)从校正前的37 dB提高到62 dB。ADC芯片的功耗为72 mW,面积为1.56 mm2。偏移双通道数字校正技术在计算机软件上实现,数字电路在65 nm CMOS工艺、125 MHz时钟下估计得出的功耗为12 mW,面积为0.21 mm2。