Use of zone-melting recrystallization to fabricate a three-dimensional structure incorporating power bipolar and field-effect transistors

Three-dimensional (3-D) structures have been fabricated incorporating power bipolar transistors in a Si substrate and metal-oxide-semiconductor field-effect transistors (MOSFET's) in an overlying silicon-on-insulator (SOI) film that was zone-melting recrystallized with a graphite strip heater. Both N-P-N and P-N-P bipolar transistors were used. The N-P-N devices exhibited no significant change in transistor characteristics after zone-melting recrystallization (ZMR), while the P-N-P devices showed a substantial reduction in breakdown voltage. The MOSFET's exhibited electron mobilities comparable to those in similar devices fabricated in single-crystal Si wafers. The bipolar transistor yield is approximately 90 percent. The unusually high device quality and yield for 3-D structures obtained by the ZMR technique demonstrates the feasibility of fabricating monolithic structures incorporating both logic functions and relatively high-current high-voltage power switches.     

Modeling of high voltage devices for ESD event simulation in SPICE

An ESD (electro-static-discharge) compact modeling methodology using a macro-modeling approach is introduced in this work for high voltage Lateral Double-diffused MOS (LDMOS) devices and new high-voltage protection clamps. The distinct characteristics of high voltage devices during high current/fast transient events are modeled without introducing convergence problems in ESD simulations for complex high voltage mixed-signal applications. The LDMOS ESD model consists of a sub-circuit that is built on top of the standard high-voltage MOS model (MOS20). The high voltage clamps, consisting of thyristor-type devices, are modeled using advanced bipolar junction transistor models.     

A novel vertical SCR for ESD protection in 40 V HV bipolar process

A vertical Silicon Controlled Rectifier (VSCR) realized in a high-voltage (HV) 40 V bipolar process is proposed for electrostatic discharge (ESD) protection applications. In addition, a new method is proposed to alter the layout of the emitter regions of the parasitic vertical PNP (VPNP) bipolar transistor in the VSCR to optimize the trigger voltage and the area of the VSCR. The transmission line pulsing (TLP) measurement results show that the VSCR possesses enhanced ESD robustness compared to the conventional vertical PNP (VPNP) bipolar transistor. The new VSCR can adjust trigger voltage, holding voltage and failure current with changing the number of emitter regions. Compare to VPNP bipolar transistor, the VSCR is more suitable for 40 V bipolar process.     

A simplified low-voltage smart power technology

A novel self-isolated low-voltage smart power technology, based on a conventional polysilicon-gate VDMOS process, has been developed for applications where cost is a crucial factor. The low mask count (eight) and the optimization of the VDMOS power device are the main process characteristics. Besides, different devices (high-voltage PMOS, low-voltage CMOS, vertical and lateral n-p-n bipolar transistors, diodes, Zeners, and high-value isolated capacitors) are also fabricated, all MOS transistors being self-aligned to the gate     

Photon emission as a characterization tool for bipolar parasitics in FinFET technology

Parasitic bipolar effects are a well-known failure mechanism in integrated circuits. They trigger latching phenomena and are of particular interest for higher current applications and under leaky conditions. Photon emission microscopy (PEM) has proven to be a suitable tool to detect the occurrence of parasitic bipolar elements in MOSFETs, such as the parasitic bipolar junction transistor (BJT). Spectral PEM even allows for a more detailed characterization of the respective parasitic bipolar operation modes. In this work, we show that spectral PEM can also be used to characterize bipolar parasitics in modern p-type and n-type FinFETs. Additionally, this characterization method allows us to determine whether germanium enriched silicon was used to optimize device performance. We conclude by demonstrating that the FinFET devices under test show a very good suppression of parasitic bipolar effects.     

功率集成器件及其兼容技术的发展

功率集成器件在交流转直流(AC/DC)电源转换IC、高压栅驱动IC、LED驱动IC等领域均有着广泛的应用.介绍了典型的可集成功率高压器件,包括不同电压等级的横向双扩散金属氧化物半导体场效应晶体管(LDMOS)以及基于硅和SOI材料的横向绝缘栅双极型晶体管(LIGBT),此外还介绍了高低压器件集成的BCD工艺和其他的功率...     

Thermal stability and secondary breakdown in planar power MOSFET's

The destructive secondary-breakdown mechanism of high-voltage n-channel power MOSFET's is discussed. A model is proposed in which the secondary breakdown is caused primarily by the negative-resistance effects of a parasitic bipolar transistor structure. The model suggests that destructive breakdown can be suppressed by a new no-surface-breakdown structure fabricated on a p^-on p⁺epitaxial wafer. Power MOSFET's having this structure have been realized and are completely free from secondary breakdowns, as suggested by the model. In addition, experimental evidence for excellent thermal stability of the power MOSFET is given by infrared scanner measurements of the temperature rise in the chip compared with bipolar transistors. An n-channel planar power MOSFET with a 400-W power limitation at 220-V breakdown voltage and a maximum current of 12 A has been successfully fabricated.     

Second breakdown of vertical power MOSFET's

It is shown that a phenomenon of second breakdown similar to that in bipolar transistors can occur in vertical power MOSFET's. A model for the phenomenon of second breakdown involving the avalanche multiplication of the channel current, the parasitic bipolar transistor, and base resistance is proposed. After presenting the theory, this model is compared with experiments on four-terminal V-groove test devices in which the substrate can be accessed independently. Good agreement is achieved between calculated and measured boundaries of the safe operating area. The model should be applicable to DMOS devices as well.     

Avalanche behavior of power MOSFETs under different temperature conditions

The ability of high-voltage power MOSFETs to withstand avalanche events under different temperature conditions are studied by experiment and two-dimensional device simulation.The experiment is performed to investigate dynamic avalanche failure behavior of the domestic power MOSFETs which can occur at the rated maximum operation temperature range(-55 to 150℃).An advanced ISE TCAD two-dimensional mixed mode simulator with thermodynamic non-isothermal model is used to analyze the avalanche failure mechanism.The unclamped inductive switching measurement and simulation results show that the parasitic components and thermal effect inside the device will lead to the deterioration of the avalanche reliability of power MOSFETs with increasing temperature.The main failure mechanism is related to the parasitic bipolar transistor activity during the occurrence of the avalanche behavior.     

Analysis on the difference of the characteristic between high power IGBT modules and press pack IGBTs

The insulated gate bipolar transistor (IGBT) has been widely employed in such applications as alternate current motors and inverters for its lower driving power and lower on-state voltage. IGBT modules and press pack IGBTs are the most commonly used packaging for high-voltage and high-power-density applications. The difference in the packaging style and working conditions between IGBT modules and press pack IGBTs creates distinctions in, for instance, the thermal characteristics and reliability. Those distinctions lead to different applications and working conditions. In this paper, the development of IGBT devices has been reviewed, including the distinction of IGBT modules and press pack IGBTs in packaging style. Most importantly, the thermal and reliability characteristics have been compared in detail and the applications that are most suitable for IGBT modules and press pack IGBTs were outlined. The comparison of the thermal characteristics, reliability and applications provides guidance for users to take full advantage of the devices according to their requirements.     

A new high-power voltage-controlled differential negative resistance device—The lambda bipolar power transistor

A new high power voltage-controlled differential negative resistance device using the LAMBDA bipolar transistor structure, called the LAMBDA bipolar power transistor, is proposed and studied. The basic structure of this new device consists of the simultaneous integration of an interdigitated bipolar junction transistor and a merged metal-oxide-semiconductor field effect transistor. Two basic interconnection configurations of the integrated devices are also discussed. Several interesting applications based on the fabricated devices are also demonstrated. It is shown that the proposed device can be used as power signal generator and amplitude modulator using very simple circuits.     

Scaling in npn and pnp heterostructure bipolar transistors

Calculating the cutoff frequency f_T of bipolar transistors from the emitter-to-collector delay neglects the heavy influence of parasitic reactances on the frequency response of realistic transistors. A more complete equivalent circuit modelling reveals that the speed advantage of npn against pnp heterojunction bipolar transistors of common geometry, base width, and doping profile decreases as the transistor is scaled up in size. For power applications, the f_T of InP/GaInAs pnp devices may even surpass that of npn transistors     

Power integrated circuits—A brief overview

A brief overview of developments in power and high-voltage integrated circuits is presented. The technology can be classified into two types: 1) smart power devices that contain one or more common drain, vertical power transistors with control, and protective circuitry built on the same chip, and 2) high-voltage integrated circuits that combine lateral high-voltage with CMOS logic and analog bipolar circuits on the same chip. These technologies are being aimed at display drivers, telecommunications, motor drives, power supplies, and automotive electronics. A rapid growth in their application in the future can be expected.     

A rugged 650 V SOI-based high-voltage half-bridge IGBT gate driver IC for motor drive applications

This paper proposes a rugged high-voltage N-channel insulated gate bipolar transistor (IGBT) gate driver integrated circuit. The device integrates a high-side and a low-side output stages on a single chip, which is designed specifically for motor drive applications. High-voltage level shift technology enables the high-side stage of this device to operate up to 650 V. The logic inputs are complementary metal oxide semiconductor (CMOS)/transistor transistor logic compatible down to 3.3 V. Undervoltage protection functionality with hysteresis characteristic has also been integrated to enhance the device reliability. The device is fabricated in a 1.0 μm, 650 V high-voltage bipolar CMOS double-diffused metal oxide semiconductor (BCD) on silicon-on-insulator (SOI) process. Deep trench dielectric isolation technology is employed to provide complete electrical isolation with advantages such as reduced parasitic effects, excellent noise immunity and low leakage current. Experimental results show that the isolation voltage of this device can be up to approximately 779 V at 25°C, and the leakage current is only 5 nA at 650 V, which is 15% higher and 67% lower than the conventional ones. In addition, it delivers an excellent thermal stability and needs very low quiescent current and offers a high gate driver capability which is needed to adequately drive IGBTs that have large input capacitances.     

Current state-of-the-art and future prospects for power semiconductor devices in power transmission and distribution applications

Since the first commercially viable thyristors appeared in the early 1960s, there has been a dramatic increase in the switched power ratings and versatility of high-voltage power semiconductor devices. By the mid 1970s, thyristors with switched power ratings of several MVA were being applied in high voltage dc transmission systems and static VAr compensators. The introduction, in the 1980s, of controlled turn-off devices, such as the gate turn-off thyristor (GTO) and insulated gate bipolar transistor (IGBT), broadened the application of high-voltage power devices to hard-switched converters and, by the start of the 21st century, controllable silicon power devices were available with voltage ratings of 12?kV and switched power capabilities of up to 40?MVA. A review of the current state-of-the-art in silicon high-voltage power semiconductor technology covers gate-commutated thyristors (GCT, IGCT) and IGBT devices, including the injection-enhanced IGBT or IEGT. Despite these considerable achievements, there is now mounting evidence that silicon-based power semiconductors are reaching their limit, both in terms of voltage rating and of switched power capability. The introduction of wide-band-gap semiconductor materials such as silicon carbide offers the potential to break through the voltage-switching frequency limitations of silicon, with power-switching frequency products more than two orders of magnitude higher. An analysis of the current status and future prospects for silicon carbide power electronic devices is presented, together with a case study comparing a variety of silicon and silicon carbide solutions in a 10?kV hard-switched converter application. It is shown that an all-silicon carbide switch offers the best electrical performance and lowest cost solution, in spite of higher per unit area device costs.     

Scaling constraints imposed by self-heating in submicron SOIMOSFET's

The presence of a buried oxide layer in silicon causes enhanced self-heating in Silicon-On-Insulator (SOI) n-channel MOSFETs. The self-heating becomes more pronounced as device dimensions are reduced into the submicron regime because of increased electric field density and reduced silicon volume available for heat removal. Two-dimensional numerical simulations are used to show that self-heating manifests itself in the form of degraded drive current due to mobility reduction and premature breakdown. The heat flow equation was consistently solved with the classical semiconductor equations to study the effect of power dissipation on carrier transport. The simulated temperature increases in the channel region are shown to be in close agreement with recently measured data. Numerical simulation results also demonstrated accelerated turn-on of the parasitic bipolar transistor due to self-heating. Simulation results were used to identify scaling constraints caused by the parasitic bipolar transistor turn-on effect in SOI CMOS ULSI. For a quarter-micron n-channel SOI MOSFET, results suggest a maximum power supply of 1.8 V. In the deep submicron regime, SOI devices exhibited a negative differential resistance due to increased self-heating with drain bias voltage. Detailed comparison with bulk devices suggested significant reduction in the drain-source avalanche breakdown voltage due to increased carrier injection at the source-body junction     

New Layout Arrangement to Improve ESD Robustness of Large-Array High-Voltage nLDMOS

In high-voltage applications, large-array n-channel lateral DMOS (LA-nLDMOS) is usually required to provide high driving capability. However, without following the foundry-suggested electrostatic discharge (ESD) design guidelines in order to reduce total layout area, LA-nLDMOS is easily damaged once the parasitic bipolar junction transistor is triggered under ESD stresses. Accordingly, the bipolar triggering of LA-nLDMOS usually limits the ESD robustness of LA-nLDMOS, particularly in the open-drain structure. In this letter, a new layout arrangement for LA-nLDMOS has been proposed to suppress the bipolar triggering under ESD stresses. Measurement results in a 0.5- ${rm mu}hbox{m}$ 16-V bipolar CMOS DMOS process have confirmed that the new proposed layout arrangement can successfully increase the human-body-model ESD level of the LA-nLDMOS with effective width of 3000 ${rm mu}hbox{m}$ from the original 0.75 kV up to 2.75 kV.      

Recent progress of submicron CMOS using 6H-SiC for smart powerapplications

Silicon carbide (SiC) CMOS circuits have been developed recently to provide monolithic control for SiC MOS power switching devices. Although SiC CMOS is not well suited for high-end microprocessor applications, it must provide the necessary response time performance required for safe operation in high-voltage power switching applications. Despite previous developments in SiC CMOS process technology; which have enabled digital circuit operation using a 5 V power supply, circuit switching speeds were in the microsecond range. An obvious way to improve circuit performance is to scale device lateral and vertical dimensions. This paper describes recent progress in the development of a submicron, single metal, p-well CMBS process technology using 6H-SiC. Conventional NMOS transistors are fabricated with 0.5-mm (drawn) channel lengths and exhibit acceptable short-channel effects. Conventional PMOS transistors exhibit punchthrough at 0.8-mm channel lengths and require considerable channel engineering efforts which are also presented. Several digital logic gates and a ring oscillator have been fabricated with nanosecond gate switching performance. Performance limiting factors like parasitic series resistance is also investigated     

Optimized design of a merged bipolar MOSFET device

Numerical techniques have been applied to predict the steady-state characteristics of lateral bipolar-MOSFET (BIMOS) power switching devices. The BIMOS has the same structure as a lateral double-diffused MOSFET (LDMOS), with the p-type channel region acting as the base of an n-p-n transistor. By merging MOSFET and bipolar transistors in a lateral configuration, a monolithic power-integrated circuit is realized which retains some of the desirable features of both types of transistors for switching applications. Specifically, the structure of a switching device with low on-resistance high voltage capability, fast switching speed, and high input impedance is derived which does not require significantly increased device fabrication complexity. A special junction isolation design was used to limit the parasitic effects involving the substrate. These parasitic effects can degrade the performance of the BIMOS by reducing the gain of the n-p-n transistor and introducing a large substrate current. An off-state model has been developed in order to study the field shaping effects which occur with the inclusion of the junction isolation. The design is optimized to obtain a high-breakdown-voltage low-on-resistance parasitic-free monolithic-power integrated circuit.     

Leakage current mechanisms in Hydrogen-passivated fine-grain polycrystalline Silicon on insulator MOSFET's

In this paper we identify various sources of leakage current in thin-film silicon on insulator (SOI) MOSFET's made in hydrogen-passivated small-grain polycrystalline silicon. The action of a parasitic bipolar transistor that can amplify the leakage current due to the thermally generated carriers has been confirmed and characterized. A current gain (β) of more than 6 for the parasitic bipolar transistor has been experimentally measured in accumulation-mode devices, in spite of the presence of a large number of defects. This high gain is attributed to the presence of the vertical electric field, which separates the carriers, thus reducing the probability of recombination. The presence of field-enhanced generation is shown to be the cause of the observed increase in the leakage current with positive front- or back-gate bias for p-channel accumulation-mode devices. Reasonable agreement has been obtained between experimental data and theory based on field-enhanced generation due to Poole-Frenkel barrier lowering.