A precise MOSFET model for low-voltage circuits

A MOSFET model that is capable of handling the drain current above 10^-10A within the temperature range of 220-340 K is proposed. The key feature of the model is that surface potentials at source and pinchoff points are used for the purpose of obtaining a smooth connection between the current solutions in the tail and the saturation regions. Comparison of the model with experiments has been carried out using n-channel MOSFET's with 7 × 10¹³, 7 × 10¹⁴, and 4 × 10¹⁵cm^-3substrate impurity concentration and 675-, 1470-, and 5030-Å gate-oxide thickness. The theoretical calculations are in excellent agreement with the experimental measurements. It is shown that low-level current has a strong influence on the low-voltage static inverter circuit and dynamic memory.     

Novel low-voltage low-power full-swing BiCMOS circuits

A novel BiCMOS full-swing circuit technique with superior performance over CMOS down to 1.5 V is proposed. A conventional noncomplementary BiCMOS process is used. The proposed pull-up configuration is based on a capacitively coupled feedback circuit. Several pull-down options were examined and compared, and the results are reported. Several cells were implemented using the novel circuit technique; simple buffers, logic gates, and master-slave latches. Their performance, regarding speed, area, and power, was compared to that of CMOS for different technologies and supply voltages. Both device and circuit simulations were used. A design procedure for the feedback circuit and the effects of scaling on that procedure were studied and reported     

Ion-implanted complementary MOS transistors in low-voltage circuits

Simple but reasonably accurate equations are derived which describe MOS transistor operation in the weak inversion region near turn-on. These equations are used to find the transfer characteristics of complementary MOS inverters. The smallest supply voltage at which these circuits will function is approximately 8kT/q. A boron ion implantation is used for adjusting MOST turn-on voltage for low-voltage circuits.     

Design principles for low-voltage low-power analog integrated circuits

In this paper it is argued that there are good reasons to choose current as the information-carrying quantity in the case of low-voltage low-power design constraints. This paper focuses on the influence of the transfer quality on that choice. To obtain power-efficient transfer quality, indirect feedback is shown to be a good alternative to traditional feedback techniques.     

Optimization of word-line booster circuits for low-voltage flashmemories

Two word-line booster circuits, which output a word-line voltage for reading dash memory data, are analyzed and optimized. A capacitor-switched booster circuit outputs a voltage higher than the supply voltage by switching the connection state of one of more boosting capacitors with the load capacitor from parallel to series. The optimum number of capacitors and capacitance per boosting capacitor are obtained as a function of the voltage ratio of the required high voltage to the supply voltage. The operation current consumed by the boosting operation is also analytically derived. In addition, another booster circuit-Dickson charge-pump circuit-is optimized under the condition to maximize the output current at a high word-line voltage. Characteristics of the booster circuits are compared, and the selection of booster circuit for low-voltage flash memory is discussed     

Low-power low-voltage differential class-AB OTAs for SC circuits

Two new differential class-AB operational transconductance amplifiers (OTAs) for SC circuits that operate with a supply voltage of less than two transistor threshold voltages are introduced. They make use of a new class-AB pseudodifferential pair to generate signal currents much larger than quiescent currents. Both OTAs have been designed to operate with a supply voltage of V/sub DD/=1.1 V, using a 0.35 /spl mu/m CMOS technology. Simulation results for a load capacitance (C/sub L/) of 1 pF show 15 MHz gain-bandwidth product with a quiescent power consumption of 10 /spl mu/W.     

Back-gate forward bias method for low-voltage CMOS digital circuits

The back-gate forward bias method suitable for present standard bulk CMOS processes has been promoted for low-voltage digital circuit application. A CMOS inverter employing the method has experimentally exhibited the ability of electrically adjusting the transition region of the dc voltage transfer characteristics. Transient measurement has further shown that the inverter with a back-gate forward bias of 0.4 V can operate at low supply voltages down to 0.6 V without significant loss in switching speed. Guidelines for ensuring proper implementation of the method in a bulk CMOS process have been set up against latch-up, parasitic bipolar, impact ionization, and stand by current. Following these guidelines, a cost-effective low power, low-voltage, high-density mixed mode CMOS analog/digital integrated circuits chip with both reasonable speed and improved precision has been projected for the first time     

A new design topology for low-voltage CMOS current feedback amplifiers

A new topology for designing low-voltage current feedback amplifiers (CFAs) is presented. By employing a second-generation positive current conveyor followed by an operational amplifier in an unconventional manner, the design circumvents the problem of trying to achieve large transimpedance in a low-voltage environment. It is shown that this CFA configuration also results in near gain independent closed-loop bandwidth defined by a single feedback resistor. The proposed amplifier was verified experimentally by a chip designed using Taiwan Semiconductor Manufacturing Company's 0.18-/spl mu/m digital CMOS process of a single-ended power supply of 1.8 V.     

Schottky diode design for low-voltage rectification

Barrier height and impurity concentration of a power Schottky diode are optimized for maximum rectifying efficiency in DC-DC converter operation. An optimum barrier-height-impurity-concentration combination is calculated for a given output voltage and diode temperature. For a 1.5 – 2 V output converter, the optimum combination is found to be 17 kT/q and 1.5 × 10¹⁶ cm^?3. Based on the theoretical prediction, titanium- and hafnium-barrier diodes were fabricated as suitable diodes for low-voltage converters and compared with conventionally used molybdenum-barrier diodes. In the experiment on a 2-V output DC-DC converter, the new diodes show higher efficiency than molybdenum diodes at up to 85°C. They are fit for use in encapsulated converters because of their smaller heat generation.     

Approach to partially self-checking combinational circuits design

This paper presents a cost-effective, non-intrusive technique of partially self-checking combinational circuits design. The proposed technique is similar to duplication with comparison, wherein duplicated function module and comparator act as a function checker that detects any erroneous response of the original function module. However, instead of realizing checker with full error-detection capability, we select a subset of erroneous responses to implement partial, but simplified function checker. A heuristic procedure that tries to find the optimal sum-of-product expression for partial function checker that minimizes its area while providing specified error coverage is described here. Effectiveness of the technique is evaluated on a set of MCNC 91 benchmark combinational circuits.     

A feedforward technique with frequency-dependent current mirrorsfor a low-voltage wideband amplifier

A feedforward technique using frequency-dependent current mirrors for a low-voltage wideband amplifier is presented. In the conventional single-stage wideband amplifiers, the folded cascode structure is used. However, the common-gate transistor requires an additional V_{DS sat} and reduces the available output voltage range. In this study the cascode structure is avoided; instead, a frequency-dependent current mirror, whose input impedance becomes higher for a higher frequency, is used to form the feedforward path from the input of the current mirror with a feedforward capacitor. This technique is effective to improve a 100 MHz-1 GHz frequency characteristic of the amplifier. The amplifier has been fabricated using the standard 0.8 μm CMOS process. The phase margin is improved from 46-66° without sacrificing the unity gain frequency of 133 MHz compared with the amplifier without this technique. The amplifier operates at 2.5 V power supply voltage and consumes 12 mW     

Modeling of the bulk versus SOI CMOS performances for the optimal design of APS circuits in low-power low-voltage applications

In this paper, we present the top-down design of an active pixel sensor (APS) circuit using an analytical model of its architecture. The model is applied to compare the performances of bulk versus silicon-on-insulator (SOI) CMOS processes and devices on the designs and performance of several 50-frames/s imagers in 2-/spl mu/m and 0.25-/spl mu/m CMOS with different pixels array sizes. For 2-/spl mu/m SOI, results show a reduction by two of the power consumption and a dynamic range increase of 0.85 V under a 3-V supply. This results in an SNR of 79 dB instead of 76. Fixed pattern noise (FPN) is also reduced from 2.7 to 1.8 mV which represents 0.26% and 0.08% of the dynamic range, respectively. For 0.25-/spl mu/m CMOS SOI, results show a reduction by 6.5 of the power consumption, FPN more than five time better, and a dynamic range increase of 0.29 V under a 1.5-V supply. However, because of the increase of the thermal noise due to the particular design choice, an SNR of 60.3 dB is achieved compared to 63 in bulk. A better SNR in SOI than in bulk can be achieved but at the expense of power consumption and FPN. However, this could be combined with an increase in pixels number in SOI compared to bulk. Potential results achievable in SOI have to our knowledge never been reached by bulk APS imagers up to now.     

Body effect up- and down-conversion mixer circuits for low-voltage ultra-wideband operation

This article presents fully differential up- and down-conversion mixer circuits manufactured in a triple well 45 nm CMOS process for low-voltage Ultra-Wideband transmitter and receiver applications. The proposed circuits both employ the transistor bulk terminal for signal injection. While the down-conversion mixer uses the bulk for switching via threshold voltage modulation, the up-conversion mixer applies the baseband signal to the bulk, thereby implicitly incorporating the back-gate controlled current source of the MOS transistor. Both circuits offer resistive on-chip termination and DC coupled output buffering for measurement purposes. The down-conversion mixer features an input-referred compression point of −13.2 dBm and a maximum conversion gain of 9.4 dB at 2.5 GHz with the 3-dB corner frequency being beyond 10 GHz. The implemented up-conversion mixer offers a maximum conversion gain of −8.8 dB at 5.8 GHz together with an output-referred compression point of −9.7 dBm. The operational bandwidth ranges from 4.5 to 6.7 GHz. Both circuits operate at a low supply voltage of 1.1 V.     

Investigation on low-voltage low-power silicon bipolar designtopology for high-speed digital circuits

This paper investigates a bipolar design topology which is suitable to operate from a voltage supply well below 1.5 V, while maintaining the ability of high frequency operation. The topology has been applied in the design of different divide-by-4 circuits, utilizing a 20-GHz 0.6-μm Si bipolar technology. The different versions featured slight modifications in the architecture of the logic cells and the influence on the frequency and supply voltage range of operation has been investigated. Measurements have shown operation from 1.0-V supply voltage and up to 4.2-GHz input frequency to 1.5 V and up to 6 GHz. The power consumption is approximately 0.3 mW/latch and 1.2 mW/latch, respectively     

A framework to evaluate technology and device design enhancementsfor MOS integrated circuits

A hierarchical framework which connects device and technology design parameters to specific circuit applications is presented. The functional circuit blocks which are used in the framework are defined. Examples of the use of this framework for design-intensive circuits are given, and experimental data which show the impact of device design on these circuit applications are presented. Technology-intensive circuit examples are also given which demonstrate the effect of technology enhancements on specific circuit applications     

Practical implementation of a general computer aided design technique for switched capacitor circuits

A general and efficient CAD method for simulation of switched capacitor filters and A/D and D/A converters, is demonstrated. It is based on the direct implementation of controlled switch branches into the widely used modified nodal analysis technique and is therefore in contrast to other methods, directly compatible with existing CAD techniques. It allows for DC, time domain, and frequency response calculations for arbitrary clock cycles and all types of inputs (piecewise constant, sample and hold, and continuous). The circuit can also contain resistors and allows for nonlinear time domain analysis too. As implemented in the Diana program it allows for full top-down design from principle to transistor level, including clock drivers, control logic, etc. Input is directly from the circuit diagram. The method is illustrated by practical design examples.