Modeling and Neuro-Fuzzy adaptive attitude control for Eight-Rotor MAV

This paper focuses on modeling and intelligent control of the new Eight-Rotor MAV which is used to solve the problem of low coefficient proportion between lift and gravity for Quadrotor MAV. The dynamical and kinematical modeling for the Eight-Rotor MAV was developed which has never been proposed before. Based on the achieved dynamic modeling, two types of controller were presented. One type, a PID controller is derived in a conventional way with simplified dynamics and turns out to be quite sensitive to sensor noise as well as external perturbation. The second type controller is the Neuro-Fuzzy adaptive controller which is composed of two type-II fuzzy neural networks (TIIFNNs) and one PD controller: The PD controller is adopted to control the attitude, one of the TIIFNNs is designed to learn the inverse model of Eight-Rotor MAV on-line, the other one is the copy of the former one to compensate for model errors and external disturbances, both structure and parameters of T-IIFNNs are tuned on-line at the same time, and then the stability of the Eight-Rotor MAV closed-loop control system is proved using Lyapunov stability theory. Finally, the validity of the proposed control method has been verified through real-time experiments. The experimental results show that the performance of Neuro-Fuzzy adaptive controller performs very well under sensor noise and external disturbances, and has more superiority than traditional PID controller.     

Dedicated microprocessors for realtime identification of multivariable systems

In this paper, an algorithm is proposed for identifying multivariable systems in state-space form from noisy data, which is suitable for implementation on dedicated microprocessor systems. The proposed algorithm uses the normalized stochastic approximation criterion which reduces the computational complexity and memory requirements. It is shown that the overall performance of the proposed stochastic approximation algorithm when using a dedicated microprocessor with fixed point arithmetic is superior to the extended least-squares method in terms of memory requirements, execution speed per iteration, and the estimation results.     

A microprocessor controlled solar tracking system

In this contribution, a microprocessor based sun finder and solar tracking system is discussed. The system was designed and implemented on an 8080-based microprocessor. The paper gives the general hardware and software along with the circuitry. The system is able to locate the sun even during periods of very poor visibility. ‘Hunting’, which is usual in such schemes, has been eliminated by means of appropriate design of the motor circuit.     

通用处理器设计中硬件仿真验证

基于动态的RTL仿真依然是验证超大规模集成电路的主要方法。在使用动态仿真方法对通用微处理器这样大规模的设计进行功能验证时仿真速度成为了瓶颈,通常的解决方案是使用FPGA进行硬件的物理原型仿真,使用FPGA可以在较短的时间内测试大量的测试向量,但是使用FPGA物理原型验证的可调试很差。针对这一主要问题,提出了三级的层次化仿真验证环境,使用硬件仿真器的仿真加速作为中间层的解决方案,即可以提高仿真速度,也提供了良好的调试环境。同时针对大规模设计多片FPGA逻辑划分提出了改进的K—L算法,优化了FPGA的利用率和片间五连。     

Microprocessor design for embedded system

This paper discusses the two main approaches to the design of microarchitectures for embedded processors: VLIW and Superscalar. The latter is preferred for the particular needs of an embedded system. Then a methodology and a design flow for Superscalar microprocessor design is presented. The approach relies on the exploitation of the features of the application to which the processor is dedicated. Also particular attention is given to fast time-to-market and to re-usability issues that are key factors for embedded microprocessor design.     

Flex: A High-Level Language for Specifying Customized Microprocessors

Researchers at Bell Labs have recently developed a silicon compiler, named Plex, that automatically generates VLSI layouts of high performance and area efficient microprocessors. Plex takes as input a specification of the function to be executed and generates a complete mask-level layout of a customized microprocessor to execute that function. The Plex microprocessor interacts with the external world, via input and output wires, and interrupts. The dedicated function performed by a Plex microprocessor typically involves real-time handling of inputs and interrupts-and the real-time generation of output signals.     

Power, Thermal, and Reliability Modeling in Nanometer-Scale Microprocessors

System integration and performance requirements are dramatically increasing the power consumptions and power densities of high-performance microprocessors. High power consumption introduces challenges to various aspects of microprocessor and computer system design. It increases the cost of cooling and packaging design, reduces system reliability, complicates power supply circuitry design, and reduces battery life. Researchers have recently dedicated intensive effort to power-related design problems. Modeling is the essential first step toward design optimization. In this article, the power, thermal and reliability modeling problems are explained and recent advances in their accurate and efficient analysis are surveyed.     

基于F330单片机的智能排风系统设计

本文介绍一种基于08051F330混合信号ISP FLASH微处理器的智能高效排风系统的设计方案；它利用微处理器对高效无刷电机进行位置检测并发出控制信号，可使电机在300—3000r／m之间连续调速：并利用微处理器自身的温度传感器进行环境温度测量，实现排风的智能化；优化后的控制系统电路简单，成本低，可靠性好，应用广泛。     

基于自适应神经网络模糊系统的混沌音频水印盲检测

自适应神经网络模糊推理系统(AdaptiveNeuro FuzzyInferenceSystem, ANFIS)是将Sugeno一阶模糊系统以网络的形式来实现而得到的一种多输入单输出的神经网络。它能够很好的模拟出输入输出之间的关系,且收敛速度快,误差小,所需训练样本少,非常有利于水印信号的盲分离。利用ANFIS良好的自适应控制能力提出了一种具有较强鲁棒性的DCT域音频水印盲检测算法,实验证明,该水印检测算法准确性高,时间代价小,具有较强的抗攻击性,很有实用价值。     

马尔可夫系统瞬态不可用度计算的高效率蒙特卡罗方法

当马尔可夫系统规模较大时,需要采用蒙特卡罗方法计算其瞬态不可用度,如果系统的 不可用度很小,则需要采用高效率的蒙特卡罗方法.本文在马尔可夫系统寿命过程的积分方程的 基础上,给出了系统瞬态不可用度计算的蒙特卡罗方法的统一描述,由此设计了马尔可夫系统瞬 态不可用度计算的直接统计估计方法和加权统计估计方法.用直接仿真方法、拟仿真方法、基于 直接仿真的统计估计方法、基于拟方仿真的统计估计方法和加权统计估计方法计算了-可修 Con/3/30:F系统的瞬态不可用度.结果表明,由于同时采用了偏倚的抽样空间和逐次事件估计 量,加权统计估计方法的方差最小,当系统不可用度很小时,该方法效率最高.     

分布式架构在银行核心业务系统的应用

相对于主机集中式架构,以X86和云计算为基础的分布式架构在扩展性、低成本方面的优势明显,随着技术的进步,其可用性也在逐步提升,已经成为主流的架构方案.针对在数据库层应用分布式架构,本文从分库分表、读写分离、数据共享和访问性能优化、高效运维等方面,提出了一套适用于银行核心业务系统的分布式架构解决方案,并已取得应用实践的成功.     

嵌入式操作系统Nucleus的移植研究

嵌入式系统作为计算机应用的一个崭新领域,以其简洁、高效等优点越来越多地受到人们的关注,而要开发一个嵌入式应用系统,则需要嵌入式硬件、嵌入式操作系统及相应的开发工具等。其中嵌入式操作系统是嵌入式应用系统中的基础部分,占有十分重要的地位,针对不同硬件平台。往往要进行嵌入式操作系统的移植。Nucleus是一种典型的嵌入式操作系统,具有体积小、功能强大、易于定制等特点,通过对Nucleus系统结构特点的分析,在基于SEP4020微处理器的评估板上,详细地论述了将嵌入式Nucleus操作系统移植到具体硬件平台上需要完成的工作。     

Post-Failure Reconfiguration of CSP Programs

In this paper a technique called process merging is introduced. This technique allows the merging of two communicating sequential processes into a new single process. Thus, this technique can be used to reconfigure a distributed program after a faulty processing element has been detected. The technique is most applicable to dedicated multiple microprocessor systems where the need for continuous operation is critical. A process merging algorithm which operates on distributed programs using the CSP notation is presented in detail and its operation is discussed. In order to illustrate the merging technique, the algorithm's behavior is demonstrated using two classical distributed programs: the Bounded Buffer, Producer, Consumer program and the Dining Philosophers program. Finally, the merging technique is examined with respect to its demands on overall system operation and overhead. This examinatiQn leads to suggestions for future research.     

Microprocessor based codec for a new class of burst error correcting codes

In this paper, an entirely new class of burst error correcting codes are described, and a design of a codec (coder/decoder) based on a microprocessor is given. The codes described are applicable not only to the conventional 1-D telecommunications channels but also to the less conventional 2-D and 3-D channels in which the burst errors manifest themselves as patches and clusters respectively.The codes being cyclic, may be generated by the usual shift register arrangement and similarly for the decoder which consists of a programmable counter, some logic circuits and shift registers.It will be shown that great improvements can be achieved in the codec by the use of a microprocessor based system. Since the codec is dependent on the burst shape and the channel dimensions, an efficient way to cope with variations in these parameters is to design an adaptive codec which will cope with the various expected burst shapes in a given channel. For this purpose an experimental codec has been designed based on the 6809 microprocessor. In this design each component of the hardware design has been emulated by software routines. Each codec being stored in an individual ROM. This provides a highly versatile system in that for any given communication channel and burst shape, only the appropriate ROM need be selected to ensure effective decoding of erroneous data. The efficiency of the codes allows for correction of large bursts of errors for relatively small memory requirements.the experimental codec is to be used to investigate fully delays due to processing time in the decoder. The delays incurred set limitations on the bit rate capabilities of the system, which is a key factor in comparison of performance against the equivalent hardware design.The transition from a hardware orientated design to a software orientated design offers advantages not only in versatility, but also in reduced complexity and increased compatibility within a communications network.     

基于龙芯SoC的嵌入式网络收音机设计

针对嵌入式系统在高性能电子产品中的应用需求,研究并实现一个以龙芯SoC处理器HS3210为核心的嵌入式网络收音机的设计方案。以龙芯SoC处理器HS3210为核心,介绍Linux操作系统在龙芯SoC处理器上运行的实现,及外围部分电路芯片的选择与接口设计。实验结果表明,应用该方法设计的网络收音机成本低、性能高、功能易扩展。     

A New Micro-Payment System Using General Payword Chain

In recent years electronic commerce has grown rapidly as Internet and web technologies have progressed. Therefore, a secure and efficient payment system for general-purpose applications is undoubtedly becoming an important issue. Rivest and Shamir have proposed a micro-payment scheme which is user-specific and vendor-specific. However, in their scheme, it is required that the user generates a new payword chain for each vendor from which the user makes a purchase. In this paper, we propose a new micro-payment system that enables users to make purchases from multiple vendors. Only one payword chain has to be generated which makes this system very efficient. A sequence of payword chains which represents a set of small payments can be authenticated and payment can be made by an efficient method. A lower computation cost and improved system performance is also achieved. Therefore, the new micro-payment system has multiple practical applications.     

The use of a TMS 320 chip for a Cambridge ring-host computer interface

This paper describes a microprocessor interface based on a Texas TMS 320 signal processing chip which permits information to be transferred between a manufacturer supplied parallel interface on a GEC 4000 series computer and a Cambridge ring. The very high speed of the TMS microprocessor permitted features which would normally require hardware logic to be implemented in software. The interface is full duplex, independence of the receive and transmit functions being achieved by a simple process switch mechanism. The design is generally applicable; only the parallel port wiring and the software status testing would need to be modified to use this interface on other computing systems.     

DISCUS — a distributed control microprocessor system

DISCUS (distributed control microprocessor system) represents a simple, yet effective approach to multimicroprocessor applications. It is being developed and used at RSRE. The basic concept is of a collection of asynchronous microprocessors cooperating to perform a task, with each processor dedicated to one function, and one function only. Interprocess communication is achieved through an operating system resident in each processor, via a specified hardware and software interface. It is also possible to add, online, an extra processor, containing identical software to a similar processor already in the system, thus increasing the functions throughput by parallel working. The prototype system consists of Intel 8080 processors, and programs are written in CORAL.An experimental digital communications switch is being built in conjunction with other work at RSRE as the first application of DISCUS and its concepts.     

随机测试程序生成器研究

随机测试是微处理器设计过程的重要环节,按照一定原则生成的随机指令序列,能够构造出指令组合的各种情况,达到比较好的测试强度和较高的覆盖率。介绍了一种基于模拟器的动态随机测试程序生成器的实现机制,此生成器用多个状态机来抽象整个被测处理器的可能行为,具有简单和高效的特点。给出了测试的统计数据。随机测试生成器对清华大学具有自主知识产权的微处理器的测试过程中取得了良好的测试效果。     

浅谈嵌入式软件操作系统

嵌入式系统是以应用为中心,以计算机技术为基础,可进行软、硬件裁剪的专用计算机系统。嵌入式软件的发展,决定了选择可靠有效的嵌入式操作系统的重要性。本文阐述了选择嵌入式操作系统的要素,介绍了几种常见的嵌入式操作系统并进行了比较。